JP4940894B2 - Synchronous memory circuit - Google Patents

Description

  The present invention relates to a synchronous memory circuit.

  Some synchronous static RAMs have different burst lengths (the number of bits for continuously writing / reading data) for each product. In some synchronous dynamic RAMs, the burst length is made variable by mode setting by a mode register set before write / read operations.

  However, in all cases, the burst length after the start of the write / read operation is fixed, and there are cases where only a part of the burst data is used in an application that handles data of various numbers of bits, and the use efficiency of the memory capacity is increased. There was a case of decline.

  After the present invention, a known example was investigated from the viewpoint of a memory capable of changing the burst length. As a result, a patent document 1 was found. This known example discloses a memory circuit having a dedicated instruction for changing the burst length.

JP 2000-90665 A

  In computer systems such as servers, data is generally processed in units of bytes (1 byte = 8 bits), and operations such as writing to and reading from memory are often performed in units of 8 bits or 4 bits. The length is often set to 8 or 4. On the other hand, since the length of data handled in network systems, etc. is random, if the burst length is too long, some data is valid in the burst, and the rest is invalid data, and the memory usage efficiency May decrease. For this reason, when the burst length is set short, the invalid data area as described above is reduced, but it is necessary to frequently give a read command and a write command to the memory, resulting in complicated control and increased power consumption. Furthermore, if the period in which the memory can receive a read command or a write command is longer than the burst length, it takes time until all data is read or written, which hinders improvement in system performance.

  Therefore, if the inventor can freely change the burst length of the memory, the burst length can be changed according to the length of the data to be stored to improve the memory usage efficiency and performance, reduce power consumption, etc. Thought. For this purpose, the function to set the burst length with the mode register before power-on / read-out like the conventional synchronous dynamic RAM is insufficient, and it is optimal from the length of data at the time of writing / reading. It is desirable that the burst length can be selected and selected.

  An object of the present invention is to provide a semiconductor integrated circuit device including a memory circuit in which a burst length can be changed at any time when writing and reading are performed with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. In the memory read control circuit, a circuit is provided for determining whether or not the read command is given in the next cycle to which the read command is given, and the burst length is changed according to the result. Further, the write control circuit is provided with a circuit for determining whether or not the write command is given in the cycle before the write command is given, and the burst length is changed according to the result.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. Since the burst length can be switched when a read command or a write command is given, it is possible to achieve both improved memory use efficiency and simple control. In particular, the synchronous memory circuit of the present invention is effective in a system with many data length variations.

  FIG. 1 shows a functional block diagram of a synchronous memory circuit mounted on a semiconductor integrated circuit device. The decoder 102 and the memory array 103 constitute a bank 101 that is a unit that can operate independently. In the example of FIG. 1, 16 banks (101-10 to 101-15) are mounted. For example, the memory array 103 is composed of 64K × 144 = 9M bits composed of dynamic memory cells, and the entire memory circuit has a memory capacity of 144M bits.

  Note that it takes 5 cycles to complete the operation after one bank starts the read or write operation and to accept the next instruction. However, since the banks 101-0 to 101-15 can operate independently, it is possible to receive a read or write instruction every cycle by selecting different banks as the synchronous memory circuit.

  In addition to the clock supplied from the clock generation circuit 105, the control circuit 104 that controls the synchronous memory circuit receives a read command signal / R, a write command signal / W, a data rate instruction signal / F, and other commands. Various control signals are supplied to the read circuit 106 and the write circuit 107.

  As shown in FIG. 1, the read circuit 106 and the write circuit 107 are provided in common to the plurality of banks 101-100 to 101-15. Further, the read circuit 106 and the write circuit 107 are provided independently, and the synchronous memory circuit can receive both the read command / write command in one cycle. However, in that case, the read command and the write command must be given to different banks. Since the data bus is also divided into the read system Q [35: 0] / write system D [35: 0], it is possible to read / write simultaneously with the receipt of the instruction. The read circuit 106 includes an output register 108 that temporarily stores read data from the memory array 103 of the bank 101, and a selector 109 that selectively outputs the read data stored in the output register 108 to the read data bus. . The write circuit 107 also includes an input register 110 for temporarily storing write data from the write data bus, and a bank 101 specified by an address (BA, SA) among the write data stored in the input register 110. And a write buffer 111 in which data to be written to the memory array 103 is stored.

  Write data is captured at SDR (single data rate) or DDR (double data rate) depending on the polarity of the data rate instruction signal / F. Although details will be described later, by the burst length control signal (write) WRBL4T, when the burst length is 4, 36: 144 serial-parallel conversion is performed, and when the burst length is 2, 36:72 serial-parallel conversion is performed. Write to the memory array. Further, 144 bits are read out from the memory array 103 by a single instruction, and 144: 36 parallel-serial conversion is performed. Although details will be described later, according to the burst length control signal (read) RDBL4T, when the burst length is 4, all 144 bits are read from the memory circuit over 2 cycles, whereas when the burst length is 2, only 72 bits are read. Are read from the memory circuit.

  Although the above description has focused on the portions particularly relevant to the present invention, other circuit blocks will be briefly described below. The address register 112 stores a memory address to be accessed. The memory address consists of a bank address BA and a synchronous address SA. The clock generation circuit 105 is configured by, for example, a PLL. In this configuration example, the clock generation circuit 105 has two systems of a basic clock (K, / K) and an output clock (C, / C). Further, it is supplied to the outside of the synchronous memory circuit as an echo clock (CQ, / CQ) (see FIG. 6). The impedance control circuit 113 performs impedance control for the clock (CQ, / CQ) driver and the driver for the read data bus.

  FIGS. 2A and 2B are configuration examples of burst length control circuits (read / write) that generate burst length control signals (read / write) RDBL4T / WRBL4T, respectively. The burst length control circuit is included in the control circuit 104. FIG. 3 shows a timing chart of the burst length control signal (read / write) shown in FIG.

  First, the operation of the burst length control circuit (reading) will be described. In FIG. 3, the burst length control signal (read) in the case where the read command signal / R has a waveform that is high in the first cycle, low in the second to fourth cycles, and high again after the fifth cycle. The waveform of RDBL4T is shown. Based on the circuit operation of FIG. 2A, the burst length control signal (readout) RDBL4T is low in the first to fourth cycles, high in the fifth cycle, and low again after the sixth cycle. In this case, in the first cycle, the read command signal / R is High, and the read operation is not executed and is NOP (No Operation). In the second cycle, the read command signal / R becomes Low and the read operation is executed. In the second cycle, the burst length control signal (read) RDBL4T is Low, and a burst length 2 read operation is performed. While the read command signal / R is continuously low (second to fourth cycles), the burst length 2 read operation continues. When the read command signal / R becomes high (fifth cycle), the burst length control signal ( Read) RDBL4T becomes High, and a read operation with a burst length of 4 is performed. When the read command signal / R is High, the read operation is not performed on the new address, but when the burst length is 4, the data that has not been output among the read data for the previous address is output. And can fill the data bus.

  The operation of the burst length control circuit (reading) will be further described with reference to FIG. The output register 108 has a capacity of 144 bits in the configuration of FIG. 1, and is divided into four areas each having 36 bits. In the case of reading with a burst length of 2, two areas are selected by the selector 109 and output to the read data bus. The read data in the third to fifth cycles in FIG. 3 will be described in more detail. In the third cycle, in response to the read command signal / R (Low), A3 to D3 (A3 to D3 are each 36-bit read data) are transferred from the memory array to the output register 108 in accordance with the address signals (BA, SA). Read out. In the selector 109, since the burst length control signal (read) RDBL4T is Low, 72 bits of read data (for example, A3 and B3) of two areas are read to the data bus (read burst length 2). . In the fourth cycle, in response to the read command signal / R (Low), A4 to D4 (A4 to D4 are each 36-bit read data) are newly output from the memory array in accordance with the address signals (BA, SA). Read to 108. In the selector 109, since the burst length control signal (read) RDBL4T is Low, 72 bits of read data (for example, A4 and B4) in two areas are read to the data bus. Further, in the fifth cycle, in response to the read command signal / R (High), reading from the new memory array is not performed. On the other hand, in the selector 109, the burst length control signal (read) RDBL4T is High. The remaining 72 areas of read data (C4 and D4 in the above example) are read out to the data bus. As a result, reading with a burst length of 4 is realized.

  Next, the operation of the burst length control circuit (write) will be described. In FIG. 3, the burst length control signal (write) when the write command signal / W has a waveform such that it is high in the first cycle, low in the second to fourth cycles, and high again after the fifth cycle. The waveform of WRBL4T is shown. Based on the circuit operation of FIG. 2 (b), the burst length control signal (write) WRBL4T is output High in the first to second cycles, Low in the third to fourth cycles, and High again from the fifth cycle. The In this case, in the first cycle, the write command signal / W is High, and the write operation is not executed and is NOP (No Operation). At this time, the write data is latched every cycle so that the write operation can be started whenever a write command is received. When the write command signal / W becomes Low in the second cycle, the write operation is executed. At this time, the burst length control signal (write) WRBL4T is High and a burst length 4 write operation is performed. Further, when the write command signal / W is continuously low for two cycles or more, the burst length control signal (write) WRBL4T is low (third and fourth cycles), and a burst length 2 write operation is performed.

  The operation of the burst length control circuit (write) will be further described with reference to FIG. The input register 110 has a capacity of 144 bits in the configuration of FIG. 1, and is divided into four areas each having 36 bits. The write data in the first to third cycles in FIG. 3 will be described in more detail. In the first cycle, the write command signal / W (High) is latched, but write data a1 and b1 (a1 and b1 are each 36-bit write data) are latched. In the second cycle, since the write command signal / W (Low) becomes the burst length control signal (write) WRBL4T is High, the write data c1 and d1 (c1 and d1 are 36-bit write data, respectively) are latched, 144 bits of the write data a1 to d1 are transferred to the write buffer 111 and written to the designated address (BA, SA) (write with a burst length of 4). In the third cycle, since the write command signal / W (Low) and the burst length control signal (write) WRBL4T are Low, the write data a2 and b2 are latched, and 72 bits of the latched write data a2 and b2 are obtained. It is transferred to the write buffer 111 and written to the specified address (BA, SA) (burst length 2 write). When the burst length control signal (write) WRBL4T is input to the write buffer 111, the range to be activated is switched between 72 bits and 144 bits.

  In this embodiment, the burst length is switched between 2 and 4, so that if the NOP continues for 2 cycles or more, the data bus becomes empty, but by increasing the burst length to 8 or the like, for example, There is an advantage that the data bus efficiency can be increased even when read NOPs are continuous. However, if the burst length is long, read / write operations cannot be performed on a new address while data is being input / output, which may adversely affect system performance. The burst length to be switched may be determined so as to be advantageous for improving the system performance in which the synchronous memory circuit of the present invention is used.

  FIG. 6 shows an example of a timing chart of the synchronous memory circuit shown in FIG. 1 when reading / writing is simultaneously performed. During this period, the data rate instruction signal / F is Low, and a timing chart in the case of operating in DDR is shown. When the read command signal / R becomes Low in cycle # 0, a read command for the address # A0 of the bank address # B0 is given. The read data for this read command is 2 bits (Q0a, Q0b) in DDR from the second half of cycle # 5. Also in cycle # 1, since the read command signal / R is Low and the read command is given, the read data for the read command in cycle # 0 has a burst length of 2 and only the 2 bits (Q0a, Q0b). In cycle # 2, a read command is given to address # A4 of bank address # B4, but in the next cycle # 3, no read command is given, so the burst length is 4, and DDR from the second half of cycle # 7 4 bits (Q4a, Q4b, Q4c, Q4d) are read out.

  In cycle # 0, the write command signal / W is also low, and a write command is given to address # A1 of bank address # B1 given in the second half of cycle # 0. In the immediately preceding cycle # (-1), since the write command signal / W is High, a write operation with a burst length of 4 is performed, and data of 4 bits (D1a, D1b, D1c, D1d) is obtained by DDR from cycle # (-1). Written. In the next cycle # 1, since the write command signal / W is low, the burst length is 2, and data of 2 bits (D3a, D3b) is written from cycle # 1 by DDR.

  FIG. 7 shows an example in which a memory macro embodying the present invention is mounted in an LSI. FIG. 8 shows an example in which an integrated circuit device embodying the present invention is mounted on a board. In the example of FIG. 7, the control circuit and the memory macro corresponding to the configuration of FIG. 1 are integrated on one chip. In the example of FIG. 8, the control circuit of FIG. A memory LSI corresponding to the above configuration is integrated on one chip, and a plurality of these chips are mounted on a board. In either case, the control signal from the control circuit to the memory macro (FIG. 7) or the control signal from the controller LSI to the memory LSI (FIG. 8) is the control signal necessary for the basic read or write operation as shown in the figure. And has no signal for indicating the burst length.

It is a circuit block diagram of a synchronous memory circuit. It is a structural example of a burst length control circuit (read / write). 3 is a timing chart of the burst length control circuit (read / write) in FIG. 2. It is a figure for demonstrating reading operation | movement in detail. It is a figure for demonstrating a write-in operation | movement in detail. 2 is a timing chart of the synchronous memory circuit of FIG. This is an example in which a memory macro embodying the present invention is mounted on an LSI. This is an example in which an integrated circuit device (memory LSI) embodying the present invention is mounted on a board.

Explanation of symbols

BA ... bank address, SA ... synchronous address, / R ... read command signal (negative polarity), / W ... write command signal (negative polarity), / F ... data rate instruction signal, / BW ... byte write command signal (negative) Polarity), K ... basic clock (positive polarity), / K ... basic clock (negative polarity), C ... output clock (positive polarity), / C ... output clock (negative polarity), Q ... read data signal, D Write data signal, CQ ... Echo clock signal (positive polarity), / CQ ... Echo clock signal (negative polarity).

Claims (4)

  A first control circuit in which a burst length of read data is changed by a read command;
  A second control circuit that changes a burst length of write data according to whether or not a second write command is given in a cycle immediately before the first write command;
  Write the latched write data with the above burst length,
  A synchronous memory circuit characterized in that the second write instruction can be given in the same cycle as the read instruction.   In claim 1,
  The burst length of the write data by the first write command when the second write command is given is the burst length of the write data by the first write command when the second write command is not given. A synchronous memory circuit characterized by being shorter than a length.   In claim 1,
  A synchronous memory circuit, wherein a read command can be given in the same cycle as the first write command or the second write command.   In claim 3,
  A synchronous memory circuit comprising a plurality of banks, wherein the first write instruction, the second write instruction, and the read instruction act on different banks.

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