JP2005116167A - Memory system and method for setting operation mode by address signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system and a method selecting or changing the operation mode of a memory device without issuing any new MRS commands regarding a memory system for setting an operation mode by an address signal. <P>SOLUTION: This memory system includes: a memory cell array; a row/column decoder for selecting a row/column of the memory cell array according to a multibit address signal; and a mode control circuit for setting an operation mode according to at least one bit of the multibit address signal used for selecting the row/column, and the method is provided for setting an operation mode in the memory system. The operation mode is selected from a burst length mode, a DLL set mode, a test mode, a CAS latency mode, and a burst type mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory system, and more particularly, to a memory system and method for setting an operation mode using a multi-bit address signal.

The memory system usually has various different operation modes such as a data strobe mode, a separate data burst, and a separate CAS latency. Therefore, the memory system includes a mode register set MRS for setting various operation modes.

  FIG. 1 is a diagram related to a general memory system 10 having a memory device 30 and a memory controller 20. Typically, command and address information is supplied from the memory controller 20 to the memory device 30, and data is exchanged between them in response to the command and address information.

  FIG. 2 shows a data processing block of the memory device 30. As shown, the memory device 30 includes input / output buffers 40 and 50, a mode register set MRS generator 60, an instruction decoder 70, a row address buffer 80, a column address buffer 90, and an internal column address generator 100. , Row decoder 110, column decoder 120, burst length counter 130, memory cell array 140, sense amplifier 150, and data input / output buffer 160. Hereinafter, the operation of such a processing block will be described in detail.

  FIG. 3 shows the relationship between the contents of the MRS table and the address signal MA [1: n]. The address signal MA supplied from the memory controller 20 is used to set various operation modes such as DLL reset, test mode TM, CAS latency CL, burst BT type, and burst length BL.

  FIG. 4 illustrates the MRS command processing process performed by the memory controller 20 communicating with the memory device 30 in burst length mode. During power-up, the memory controller 20 applies an MRS command 170 to the memory device 30. Although not shown, this is done by setting a logical combination value corresponding to the command signal displayed in CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR. On the other hand, the bits MA [0: m] and MA [m + 1: n] of the mode address signal are respectively transmitted through the address lines ADDR [0: m] and ADDR [m + 1: n] in the process of the MRS command and are shown in FIG. Various operation mode parameters of the memory device 30 are provided. 3 and 4, when the MRS instruction 170 is introduced during power up and the burst length is set at 4, the address bits A2, A1 and A0 are 0, 1 and 0, respectively. Thereafter, during the normal operation, if another MRS command is introduced and the address bits A2, A1, and A0 are 0, 0, and 1, respectively, the burst length is changed to 2.

  The general operation of the functional block shown in FIG. 2 will be described below in connection with the setting of the burst length. The instruction decoder 70 decodes the MRS instruction from the logical combination values corresponding to the instruction signals CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR. In response to sensing the MRS command, the command decoder 70 sets the MRS signal or flag so that the MRS generator 60 receives the mode address signal through the address signal lines ADDR [0: m] and ADDR [m + 1: n]. To. Accordingly, the corresponding operation mode parameter is stored in the MRS table of the memory device 30. This MR table is arranged in the MRS generator 60.

  One such operational mode parameter is the burst length BL. “Burst length” specifies the number of consecutive operations (eg, data read and write) executed in the data burst mode. For example, if BL is 4, even if one memory address is provided from the memory controller 20 to the memory device 30, four data read operations are continuously executed in response to the data read command.

  When the memory controller 20 writes data to or reads data from the memory cell array 140, a corresponding memory access command (READ or WRITE) is transmitted to the memory device 30 along with the row and column addresses. The memory controller 20 designates read and write commands by setting logical combination values corresponding to the command signals CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR sequentially decoded by the command decoder 70. The row and column addresses received by the memory device 30 through the address signal lines ADDR [0: n] are supplied to the row and column address buffers 80 and 90 through the input buffers 40 and 50, respectively. Row address buffer 80 generates a row address RA.

  Meanwhile, the MRS generator 60 provides the burst length selection signal MRS_BLi to the burst length counter 130. The burst length selection signal MRS_BLi is generated corresponding to the burst length BL transmitted from the memory controller 20 to the memory device 30, and is stored in the MRS register as shown in FIG. The burst length counter 130 counts a desired burst period (for example, BL = 4) using the burst length selection signal MRS_BLi, and generates a burst termination signal BS as a flag signal at the end of the specific burst period. The burst length counter 130 provides the burst termination signal BS to the internal column address generator 100. The internal column address generator 100 also receives a column address CA. While the burst termination signal BS is activated, the internal column address generator 100 generates the internal column address signal PCA [0: m]. The internal column address generator 100 is used to provide an internal column address signal PCA [0: m] to the column address buffer 90 to generate a column address CA.

  The row decoder 110 receives the row address RA, generates a decoded row address, and activates the corresponding word line WL of the memory cell array 140. Similarly, the column decoder 120 receives a series of column address signals CA corresponding to the burst length, generates a decoded column address dollar, and activates a corresponding column line of the memory cell array 140. . Data is provided from the memory cell array through a data input / output buffer sense amplifier 150.

  FIG. 5 shows a process in which data is selected in the memory cell array 140 through a series of column selection lines CSL and word lines WL from the row decoder corresponding to the burst length (for example, BL = 4).

  On the other hand, in the memory device 30 of the memory system 10, the operation mode may need to be changed after the power-up initial setting is completed. For example, if the burst length BL has to be changed from 4 to 2, the memory controller may issue another MRS command to provide a new set of operating mode parameters stored in the MRS table. is necessary.

  However, repeating the MRS instruction is inefficient and reduces the operating speed of the memory system 10.

  Accordingly, the present invention seeks to provide a memory system and method that can select or change the operation mode of a memory device without issuing a new MRS instruction.

  The memory device of the present invention includes a memory cell array, a row decoder that selects a row of the memory cell array according to a multi-bit address signal, a column decoder that selects a column of the memory cell array according to the multi-bit address signal, and the row and column A mode control circuit that inputs at least one bit of the multi-bit address signal used for selection and sets an operation mode of the memory device according to the at least one bit, and the operation mode has a burst length. It is at least one of a mode, a DLL reset mode, a CAS latency mode, and a burst type mode.

  The memory device of the present invention selects a row of the memory cell array in accordance with a memory cell array and a multi-bit address signal of large m bits (n> m, nm = a ≧ 1) in response to a row activation signal. A row decoder that selects a column of the memory cell array according to an n-bit multi-bit address signal in response to a read and write command, and at least one of the read and write commands, A mode control circuit for determining an operation mode of the memory device in response to at least one of a bits of a multi-bit address signal that is not used to select the column by a column decoder; .

  The memory device includes a memory cell array, a first mode generation circuit that outputs a first mode selection signal in response to a mode setting command, and a row decoder that selects a row of the memory cell array according to a multi-bit address signal. A column decoder for selecting a column of the memory cell array according to the multi-bit address signal, and at least one received from the multi-bit address signal used to select the row or column by the row decoder or the column decoder, respectively. A second mode generation circuit for outputting a second mode selection signal in response to a bit; and a mode control circuit for setting an operation mode of the memory device in response to one of the first and second mode selection signals It is characterized by comprising.

  In addition, the memory device of the present invention includes a memory cell array, a first mode generation circuit that outputs a first mode selection signal in response to a mode setting command, and an n-bit multi-bit address signal in response to a row activation command. A row decoder for selecting a row of the memory cell array in accordance with the above, and a column of the memory cell array in accordance with a multi-bit address signal of m bits (n> m, nm = a ≧ 1) in response to a read command and a write command Responsive to at least one bit of a bits of the multi-bit address signal used to select each column by the column decoder during execution of at least one of the column decoder and the read and write commands. A second mode generation circuit for outputting a second mode selection signal and one of the first and second mode selection signals. To characterized by comprising a mode control circuit for setting the operation mode of the memory device.

  According to another aspect of the present invention, there is provided a memory system including a memory controller that outputs a multi-address signal, and a memory device that receives the multi-bit address from the memory controller. A row decoder for selecting a row of the memory cell array according to a bit address signal; a column decoder for selecting a column of the memory cell array according to the multi-bit address signal; and the multi-bit address signal used for selecting the row and column. A mode control circuit for inputting at least one bit and setting an operation mode of the memory device according to the at least one bit, wherein the operation mode includes a burst length mode, a DLL reset mode, a CAS length mode, and a burst type. mode Wherein the ones of the at least any one.

  The memory system of the present invention includes a memory controller that outputs one of a mode setting command, a row activation command, a read command, and a write command, and a multi-address signal, and the multi-bit address signal from the memory controller. In a memory system comprising a memory device for input, the memory device includes a memory cell array, a row decoder for selecting a row of the memory cell array according to an n-bit multi-bit address signal in response to the row activation command, A column decoder for selecting a column of the memory cell array according to a multi-bit address signal of m bits (n> m, nm−a ≧ 1) in response to the read and write commands; While performing at least one, each column is defined by the column decoder. A mode control circuit for setting an operation mode of the memory device in response to at least one bit of a bits of a multi-bit address signal used for selection, wherein the operation mode is a burst length mode. , At least one of a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

  The memory system of the present invention includes a memory controller that outputs one of a mode setting command, a row activation command, a read command, and a write command and a multi-address signal, and the multi-bit address signal from the memory controller, In the memory system comprising the memory device for inputting the mode setting command, the row activation command, the read command, and the write command, the memory device responds to the mode setting command with a first memory cell array. A first mode generation circuit for outputting a mode selection signal; a row decoder for selecting a row of the memory cell array in accordance with an n-bit multi-bit address signal in response to the row activation command; and a response to the read and write commands. M bits (n> m, nm = a ≧ 1) A column decoder for selecting a column of the memory cell array according to an address signal, and a multi-bit address signal a that is not used to select each column by the column decoder during execution of at least one of the read and write commands. A second mode generation circuit for outputting a second mode selection signal in response to at least one of the bits, and an operation mode of the memory device in response to one of the first and second mode selection signals And a mode control circuit for setting.

  According to another aspect of the present invention, there is provided a method for setting an operation mode of a memory device having a memory array, the step of receiving a multi-bit address signal; Selecting an operation mode of the memory device using at least one bit of the multi-bit address signal used to select the row or column, the operation mode comprising: It is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

  According to another aspect of the present invention, a method for setting an operation mode of a memory device having a memory array includes receiving one of a read command and a write command and an n-bit multi-bit address signal; Selecting a column of the memory array according to m bits (n> m, nm = a ≧ 1) of the multi-bit address signal in response to one of the write commands; and selecting the column And setting an operation mode of the memory device using at least one bit of a bits of the multi-bit address signal used in the operation, wherein the operation mode includes a burst length mode and a DLL reset mode. , At least one of a test mode, a CAS latency mode, and a burst type mode.

  According to another aspect of the present invention, there is provided a method for setting an operation mode of a memory device having a memory array, receiving a mode setting command, and generating a first mode selection signal in response to the mode setting command. Receiving a multi-bit address signal; decoding the multi-bit address signal to select a row of the memory array according to a row activation command; decoding the multi-bit address signal to read and write commands Selecting a column of the memory array according to one of the following: generating a second mode setting signal according to at least one bit used to select the row or column of the multi-bit address signal And an operation mode of the memory device according to one of the first and second mode selection signals. Characterized by comprising the step of setting.

  The present invention has an advantage that the operation mode of the memory device can be set efficiently because the operation mode can be selected without issuing a new MRS instruction. In addition, since a new MRS command processing process that is executed every time the operation mode is changed can be omitted, it is possible to contribute to an improvement in the operation speed of the memory device.

  Hereinafter, although an embodiment described later will be described as an example showing the best of the present invention, the present invention is not limited thereto.

  FIG. 6 is a block diagram illustrating an example of a memory system 210 according to the present invention. The memory system 210 includes a memory controller 220 and a memory device 225. The memory controller includes a mode parameter generator 225 that generates and provides operating mode parameters using multi-bit address signals transmitted with read and write commands (READ and WRITE). Meanwhile, the memory device 230 includes a mode set generator 235 that sets an operation mode of the memory device 230 according to an operation mode parameter received through an address line during a data read or write operation.

  FIG. 7 is a data processing block diagram showing an example of the memory device 230. The memory device 230 includes input / output buffers (input / output buffers) 40 and 55, a mode register set MRS generator 60, an instruction decoder 70, a row address buffer 80, a column address buffer 90, an internal column address generator 100, a row decoder 110, It includes a column decoder 120, a burst length counter 130, a memory cell array 140, a sense amplifier 150, a data input / output buffer 160, an MRS decoder 240, and a multiplexer (MUX) 250. Here, the mode set generator 235 of FIG. 6 includes an MRS generator 60, an MRS decoder 240, and a multiplexer 250.

  During power-up, the memory controller 220 applies an MRS instruction to the memory device 230 to address the address line ADDR while executing the MRS instruction, as described above in connection with FIGS. One or more operation modes of the memory device are set using [0: m] and ADDR [m = 1: n]. The selection of the operation mode is stored in the MRS table (also referred to as MR register) of the memory device 230. The MRS table is arranged in the mode set generator 235 of FIG. 6, that is, the MRS generator 60, the MRS decoder 240, and the multiplexer 250.

  On the other hand, in the memory device 230 of the memory system 210, the operation mode may be changed after the initial setting is completed during power-up. For example, the burst length BL should be changed from 4 to 2.

  In this case, in the memory system 210, one or more operation modes selected by data stored in the MRS table of the memory device 230 are selected or changed without generating an additional MRS command. Can be done. That is, the operation mode of the memory device 230 may be selected or changed using a column access command received from the memory controller 220. Preferably, the one or more operating modes may be one or more of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

  FIG. 8 illustrates a method for providing operating mode parameters to the memory device 230 during data reading. In FIG. 8, the set operation mode is the Hurst length mode, but it should be understood that the operation mode may be a DLL reset mode, a test mode, a CAS latency mode, or a burst type mode stored in the MRS table. I must.

  As shown in FIG. 8, during power up, mode address signals MA [0: m] 180 and MA [m + 1: n] provided through address lines ADDR [0: m] and ADDR [m + 1: n], respectively. Referring to 190, BL = 4 is selected in the initial burst length mode 200 of the memory device 230 by the MRS instruction 170.

  Subsequently, during data reading, the memory device 230 performs a row activation command (ROW ACTIVE) together with the row address signals RA [0: m] 280 and RA [m + 1: n] provided through the address lines ADDR [0: n]. First, 270 is received. Row activation instruction 270 is designated from logical combination values corresponding to instruction signals CS_BAR, RAS_BAR, CAS_BAR and WE_BAR, and such logical combination values are decoded by instruction decoder 70. Row address buffer 80 uses row address signals RA [0: m] 280 and RA [m + 1: n] 290 to generate row address RA that is subsequently decoded by row decoder 110 to select word line WL. .

  Next, the memory device 230 receives the read command 300 together with the column address CA [0: m] 310 provided through the address line ADDR [0: m]. The read instruction 300 is designated from logical combination values corresponding to the instruction signals CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR, and such logical combination values are decoded by the instruction decoder 70.

  As a result, even if a refresh or activation operation is requested for all address lines ADDR [0: m], all of the address lines ADDR [0: m] are not included in a column access operation (for example, a data read operation). It is not necessary to use an address line. That is, only the address line ADDR [0: m] (m <n) is only used for addressing the memory cell array 140 during the column access operation. Thus, one or more address lines ADDR [m + 1: n] are not used for addressing the memory cell array during a column access operation.

  Instead, one address line ADDR [m + 1: n], which is not used for addressing the memory cell array during the column access operation, is selected by the memory device 230 as a mode address signal MA [m + 1] for selecting one or more operation modes. : N] used to provide one or more bits of 330. In response to the mode address signal MA [m + 1: n] 330, the memory device 230 sets the burst length mode 340 to BL = 2.

  In FIG. 9, during the first data write operation, after the data burst mode is set to BL = 4 through the address lines ADDR [m + 1: n] in response to the write command, BL = 2 in the second data write operation. Shows the process of conversion to

  FIG. 10 illustrates a method for providing operation mode parameters to the memory device 230 during a data write operation. In FIG. 10, the set operation mode is the burst length mode, but it should be understood that the operation mode may be a DLL reset mode, a test mode, a CAS latency mode, or a burst type mode stored in the MRS table. It is.

  As shown in FIG. 10, during power up, mode address signals MA [0: m] 180 and MA [m + 1: n] provided through address lines ADDR [0: m] and ADDR [m + 1: n], respectively. Referring to 190, BL = 4 is selected in the initial burst length mode 200 of the memory device 230 by the MRS instruction 170.

  Subsequently, during the data write operation, the memory device 230 performs the row activation command (ROW ACTIVE) together with the row address signals RA [0: m] 280 and RA [m + 1: n] provided through the address lines ADDR [0: n]. ) 270 is received first. The row activation instruction 270 is designated from logical combination values corresponding to the instruction signals CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR, and such logical combination values are decoded by the instruction decoder 70. Row address buffer 80 uses row address signals RA [0: m] 280 and RA [m + 1: n] 290 to generate row address RA that is subsequently decoded by row decoder 110 to select word line WL. .

  Next, the memory device 230 receives the write command 400 together with the column address CA [0: m] 310 provided through the address line ADDR [0: m]. The write instruction 400 is designated from logical combination values corresponding to the instruction signals CS_BAR, RAS_BAR, CAS_BAR, CAS_BAR, and WE_BAR, and such logical combination values are decoded by the instruction decoder 70. Meanwhile, the address line ADDR [m + 1: n] provides one or more bits of the mode address signal MA [m + 1: n] 430 for selecting one or more operation modes in the memory device 230. Used for.

  In FIG. 11, during the first data read operation, after the data burst mode is set to BL = 4 through the address lines ADDR [m + 1: n] in response to the read command, BL = 2 in the second data read operation. Shows the process of conversion to

  FIG. 7 also illustrates the manner in which the burst length mode is selected for a data read or write operation of the memory device 230.

  The MRS generator 60 receives burst length mode information (for example, BL = 4) provided to the memory device 230 and stored in the MRS register during the MRS command processing process such as the power-up process shown in FIG. A first burst length selection signal MRS_BLi to be designated is generated. The MRS generator 60 provides the first burst length selection signal MRS_BLi to the multiplexer MUX250.

  On the other hand, the mode address signal MA [m + 1: n] received through the address line ADDR [m + 1: n] during the data read or write operation is provided to the MRS decoder 240. The MRS decoder 240 decodes the mode address signal MA [m + 1: n] and generates a second burst length selection signal DMA_BLi. The MRS decoder 240 provides the second burst length selection signal DMA_BLi to the multiplexer MUX250. 8 and 10, the mode address signal MA [m + 1: n] indicates the burst length mode BL = 2.

  The MUX 250 outputs the first burst length selection signal MRS_BLi or the second burst length selection signal DMA_BLi as the burst length signal BLi in response to the current command executed by the memory device 230. That is, in response to a read or write command (output of the READ or WRITE signal from the command decoder 70), the MUX 250 outputs the second burst length selection signal DMA_BLi provided from the MRS decoder 240 to the burst length signal BLi. To do. On the other hand, in response to the MRS command (when there is no MRS signal from the command decoder 70, or READ or WRITE signal), the MUX 250 uses the first burst length selection signal MRS_BLi provided from the MRS generator 60 as the burst length. Output to signal BLi.

  As described above, the burst length counter 130 uses the burst length selection signal MRS_BLi to count the desired burst period (for example, BL = 4), and provides the burst termination signal BS as a flag signal at the end of the specific burst period. To do. The internal column address generator 100 also receives a column address CA. While the burst termination signal BS is activated, the internal column address generator 100 generates internal column address signals PCA [0: m] 320 and 420. Internal column address generator 100 is used to provide internal column address signals [0: m] 320 and 420 to column address buffer 90 to generate column address CA. The column decoder 120 receives a series of column address signals CA corresponding to the burst length, generates a decoded column address or a column selection signal line CSL, and activates a corresponding column line of the memory cell array 140. Make it.

  In some memory devices, there may be address lines ADDR [0: n] that are not used during the row activation operation. FIG. 12 illustrates a method for providing operating mode parameters to the memory device 230 during a row activation operation.

  In FIG. 12, the set operation mode is the burst length mode, but it should be understood that the operation mode may be a DLL reset mode, a test mode, a CAS latency mode, or a burst type mode stored in the MRS table. It is.

  As shown in FIG. 12, during power up, mode address signals MA [0: m] 180 and MA [m + 1: n] provided through address lines ADDR [0: m] and ADDR [m + 1: n], respectively. Referring to 190, BL = 2 is selected in the initial burst length mode 200 of the memory device 230 by the MRS instruction 170.

  Subsequently, during the row activation operation, the memory device 230 receives a row activation command (ROW ACTIVE) 270 together with the row address signal RA [0: m] provided through the address line ADDR [0: m]. Row activation instruction 270 is designated from logical combination values corresponding to instruction signals CS_BAR, RAS_BAR, CAS_BAR and WE_BAR, and such logical combination values are decoded by instruction decoder 70. The row address buffer 80 uses the row address signal RA [0: m] to generate a row address RA that is subsequently decoded by the row decoder 110 to select the word line WL. Meanwhile, the address line ADDR [m + 1: n] provides one or more bits of the mode address signal MA [m + 1: n] 470 for selecting one or more operation modes in the memory device 230. Used for.

  Next, the memory device 230 receives the read command 300 along with the column address signals CA [0: m] and CA [m + 1: n] 480 provided through the address lines ADDR [0: m] and ADDR [m + 1: n], respectively. To do. The read instruction 300 is designated from logical combination values corresponding to the instruction signals CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR, and such logical combination values are decoded by the instruction decoder 70.

  In all the embodiments described above, the bits of the mode address signal MA [m + 1: n] can be used in various ways to set the burst length of the memory device 230. For example, if the mode address signal is composed of 2 bits A9 and A10, A9_A10 = 01 and A9_A10 = 11 specify BL = 2 and BL = 4, respectively. A9_A10 = 00 can be said to be the default state when the previous burst length value is maintained.

  The present invention is not limited to the above-described embodiments, and various modifications may be realized by those skilled in the art within the scope limited by the appended claims.

  The present invention is a technique used in a memory device capable of selectively operating various operation modes including a burst length mode. By expanding the application range of the memory device, the operation speed and utilization efficiency of the memory device can be increased by including information necessary for selecting an operation mode in the multi-bit address signal.

1 is a block diagram of a general memory system. It is a data processing block diagram of a general memory device. It is a figure which shows the MRS table of a general memory system. It is a figure which shows the process of a MRS command. It is a figure which shows the data processing process in a memory cell array. 1 is a block diagram illustrating an embodiment of a memory system according to the present invention. FIG. 4 is a data processing block diagram of a memory device according to an exemplary embodiment of the present invention. FIG. 6 illustrates a method for providing an operation mode parameter in a memory device during data reading. It is a figure which shows the aspect which cooperates with the write-in operation in case the read-out operation | movement when burst length BL = 4 is BL = 2. FIG. 5 illustrates a method for providing an operation mode parameter to a memory device during data writing. It is a figure which shows a mode that read-out operation in case burst length BL = 4 is connected with write-in operation in case BL = 2. FIG. 5 illustrates a method for providing an operation mode parameter to a memory device in a row active state.

Claims (56)

A memory cell array;
A row decoder for selecting a row of the memory cell array according to a multi-bit address signal;
A column decoder for selecting a column of the memory cell array according to the multi-bit address signal;
A mode control circuit that inputs at least one bit of the multi-bit address signal used for selecting the row and column, and sets an operation mode of the memory device according to the at least one bit;
The memory device according to claim 1, wherein the operation mode is at least one of a burst length mode, a DLL reset mode, a CAS latency mode, and a burst type mode.   The memory device according to claim 1, wherein the operation mode is a burst length mode.   The memory device of claim 1, further comprising a mode register set generator for inputting the at least one bit.   The memory device of claim 1, wherein the at least one bit is not used for the row and column selection by each of the row decoder and the column decoder. A memory cell array;
A row decoder for selecting a row of the memory cell array according to a large m-bit (n> m, nm−a ≧ 1) multi-bit address signal in response to a row activation signal;
A column decoder for selecting a column of the memory cell array according to an n-bit multi-bit address signal in response to a read and write command;
In response to at least one of a bits of a multi-bit address signal not used to select the column by the column decoder while executing at least one of the read and write instructions, the memory device And a mode control circuit for determining the operation mode of the memory device.   The memory device according to claim 5, wherein the operation mode is a burst length mode.   The memory device according to claim 5, wherein the operation mode is at least one of a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   The memory device of claim 5, further comprising a mode register set generator for inputting the at least one bit. A memory cell array;
A first mode generation circuit for outputting a first mode selection signal in response to a mode setting command;
A row decoder for selecting a row of the memory cell array according to a multi-bit address signal;
A column decoder for selecting a column of the memory cell array according to the multi-bit address signal;
A second mode generation circuit for outputting a second mode selection signal in response to at least one bit received from a multi-bit address signal used to select each of the row or column by the row decoder or the column decoder;
And a mode control circuit for setting an operation mode of the memory device in response to one of the first and second mode selection signals.   The memory device according to claim 9, wherein the operation mode is a burst length mode.   The memory device according to claim 9, wherein the operation mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   The memory device of claim 9, wherein the at least one bit is a bit that is not used in the multi-bit address signal used to select the row or column.   The memory device of claim 9, further comprising a decoder that decodes the multi-bit address signal to obtain the at least one bit.   10. The memory device of claim 9, wherein the mode control circuit comprises a multiplexer that switches the first and second mode selection signals in response to at least one control signal.   15. The memory device according to claim 14, further comprising an instruction decoder for decoding an instruction from a plurality of input signals, wherein the at least one control signal includes at least one instruction decoded by the instruction decoder. .   16. The memory device of claim 15, wherein the at least one control signal includes at least one of a decoded read instruction, a decoded write instruction, and a decoded MRS instruction. A memory cell array;
A first mode generation circuit for outputting a first mode selection signal in response to a mode setting command;
A row decoder for selecting a row of the memory cell array according to an n-bit multi-bit address signal in response to a row activation command;
A column decoder for selecting a column of the memory cell array according to a multi-bit address signal of m bits (n> m, nm−a ≧ 1) in response to a read command and a write command;
A second mode selection in response to at least one of the a bits of the multi-bit address signal used to select each column by the column decoder while executing at least one of the read and write instructions A second mode generation circuit for outputting a signal;
And a mode control circuit for setting an operation mode of the memory device in response to one of the first and second mode selection signals.   The memory device of claim 17, wherein the operation mode is a burst length mode.   18. The memory device of claim 17, wherein the operation mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   The memory device of claim 17, wherein the at least one bit is a bit that is not used in the multi-bit address signal used to select the row or column.   The memory device of claim 17, further comprising a decoder that decodes the multi-bit address signal to obtain the at least one bit.   18. The memory device of claim 17, wherein the mode control circuit comprises a multiplexer that switches the first and second mode selection signals in response to at least one control signal.   The memory device of claim 22, further comprising an instruction decoder for decoding an instruction from a plurality of input signals, wherein the at least one control signal includes at least one instruction decoded by the instruction decoder.   24. The memory device of claim 23, wherein the at least one control signal includes at least one of a decoded read instruction, a decoded write instruction, and a decoded MRS instruction. In a memory system comprising: a memory controller that outputs a multi-address signal; and a memory device that inputs the multi-bit address from the memory controller;
The memory device is
A memory cell array;
A row decoder for selecting a row of the memory cell array according to a multi-bit address signal;
A column decoder for selecting a column of the memory cell array according to the multi-bit address signal;
A mode control circuit for inputting at least one bit of the multi-bit address signal used for selecting the row and column, and setting an operation mode of the memory device according to the at least one bit;
The memory system according to claim 1, wherein the operation mode is at least one of a burst length mode, a DLL reset mode, a CAS length mode, and a burst type mode.   The memory system of claim 25, further comprising a mode register set generator for inputting the at least one bit.   26. The memory system of claim 25, wherein the at least one bit is a bit that is not used in the multi-bit address signal that was used to select the row or column.   26. The memory system of claim 25, further comprising a decoder that decodes the multi-bit address signal to obtain the at least one bit.   26. The memory system of claim 25, further comprising a plurality of data lines connected between the memory controller and the memory device and performing a data burst operation according to the burst length mode. A memory comprising: a memory controller that outputs one of a mode setting command, a row activation command, a read command, and a write command, and a multi-address signal; and a memory device that receives the multi-bit address signal from the memory controller In the system,
The memory device is
A memory cell array;
A row decoder for selecting a row of the memory cell array according to an n-bit multi-bit address signal in response to the row activation command;
A column decoder for selecting a column of the memory cell array in accordance with an m-bit (n> m, nm = a ≧ 1) multi-bit address signal in response to the read and write commands;
The memory device in response to at least one bit of a bits of a multi-bit address signal used to select each column by the column decoder while executing at least one of the read and write commands A mode control circuit for setting the operation mode of
The memory system, wherein the operation mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   The memory system of claim 30, further comprising a mode register set generator for inputting the at least one bit.   31. The memory system of claim 30, wherein at least one bit of the a bits includes a bit that is not used in the multi-bit address signal used to select the row or column.   The memory system of claim 30, further comprising a decoder that decodes the multi-bit address signal to obtain the at least one bit.   31. The memory system of claim 30, further comprising a plurality of data lines connected between the memory controller and the memory device and performing a burst operation of data according to the burst length mode. A memory controller that outputs one of a mode setting command, a row activation command, a read command and a write command, and a multi-address signal; the multi-bit address signal from the memory controller; the mode setting command; the row activation In a memory system comprising a memory device for inputting a command, the read command, and the write command,
The memory device is
A memory cell array;
A first mode generation circuit for outputting a first mode selection signal in response to the mode setting command;
A row decoder for selecting a row of the memory cell array according to an n-bit multi-bit address signal in response to the row activation command;
A column decoder for selecting a column of the memory cell array in accordance with an m-bit (n> m, nm = a ≧ 1) multi-bit address signal in response to the read and write commands;
A second mode selection in response to at least one of a bits of a multi-bit address signal not used to select each column by the column decoder while executing at least one of the read and write instructions A second mode generation circuit for outputting a signal;
And a mode control circuit for setting an operation mode of the memory device in response to one of the first and second mode selection signals.   36. The memory system of claim 35, wherein the operation mode is a burst length mode.   36. The memory system of claim 35, wherein the operation mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   36. The memory system of claim 35, wherein the at least one bit is a bit that is not used in the multi-bit address signal that was used to select the row or column.   39. The memory system of claim 38, further comprising a decoder that decodes the multi-bit address signal to obtain the at least one bit.   36. The memory system of claim 35, wherein the mode control circuit comprises a multiplexer that switches the first and second mode selection signals in response to at least one control signal.   41. The memory system of claim 40, further comprising an instruction decoder that decodes instructions from a plurality of input signals, wherein the at least one control signal includes at least one instruction decoded from the instruction decoder.   42. The memory system of claim 41, wherein the at least one control signal includes at least one of a decoded read instruction, a decoded write instruction, and a decoded MRS instruction.   36. The memory system of claim 35, further comprising a plurality of data lines connected between the memory controller and the memory device and performing a burst operation of data according to the burst length mode. In a method for setting an operation mode of a memory device having a memory array,
Receiving a multi-bit address signal;
Decoding the multi-bit address signal to select a row or column of the memory array;
Setting an operating mode of the memory device using at least one bit of the multi-bit address signal used to select the row or column;
The method is characterized in that the operation mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   45. The method of claim 44, wherein the operating mode is a burst length mode.   45. The method of claim 44, wherein the at least one bit is a bit that is not used in the multi-bit address signal that was used to select the row or column. In a method for setting an operation mode of a memory device having a memory array,
Receiving one of a read command and a write command and an n-bit multi-bit address signal;
Selecting a column of the memory array in accordance with m bits (n> m, nm = a ≧ 1) of the multi-bit address signal in response to one of the read and write commands;
Setting an operation mode of the memory device using at least one bit of a bits of the multi-bit address signal used to select the column,
The method is characterized in that the operation mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   48. The method of claim 47, wherein the operating mode is a burst length mode.   48. The method of claim 47, wherein the at least one bit is a bit that is not used in the multi-bit address signal that was used to select the row or column. In a method for setting an operation mode of a memory device having a memory array,
Receiving a mode setting command;
Generating a first mode selection signal in response to the mode setting command;
Receiving a multi-bit address signal;
Decoding the multi-bit address signal and selecting a row of the memory array according to a row activation instruction;
Decoding the multi-bit address signal to select a column of the memory array according to one of a read command and a write command;
Generating a second mode setting signal according to at least one bit used to select the row or column of the multi-bit address signal;
And setting an operation mode of the memory device according to one of the first and second mode selection signals.   51. The method of claim 50, wherein the mode of operation is a burst length mode.   51. The method of claim 50, wherein the operating mode is at least one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.   51. The method of claim 50, wherein the at least one bit is a bit that is not used in the multi-bit address signal that was used to select the row or column.   Setting the operation mode of the memory device according to one of the first and second mode selection signals includes switching the first and second mode selection signals in response to at least one control signal. 51. The method of claim 50, comprising.   The method of claim 54, further comprising decoding instructions from a plurality of input signals, wherein the at least one control signal includes at least one instruction decoded by the column decoder.   56. The method of claim 55, wherein the at least one control signal includes one of a decoded read and write instruction and at least one of a decoded MRS instruction.

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