CN101202115B - Method for implementing test mode of embedded non-volatility memory chip - Google Patents
Method for implementing test mode of embedded non-volatility memory chip Download PDFInfo
- Publication number
- CN101202115B CN101202115B CN200610147328A CN200610147328A CN101202115B CN 101202115 B CN101202115 B CN 101202115B CN 200610147328 A CN200610147328 A CN 200610147328A CN 200610147328 A CN200610147328 A CN 200610147328A CN 101202115 B CN101202115 B CN 101202115B
- Authority
- CN
- China
- Prior art keywords
- value
- test pattern
- chip
- status flag
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a test mode implementing method used for a built-in non-volatility memorizer chip. A state indicating value used for indicating whether the chip is in a test mode or a normal work mode is inducted at the outside of an address-searching range of the built-in memorizer of the chip so as to lead the built-in non-volatility memorizer chip to shift between the test mode and the normal work mode, avoiding additional arrangement of a test tube pin on the chip to realize the function; thus the area of the chip is reduced and the cost is reduced to some extent.
Description
Technical field
The present invention relates to a kind of test pattern implementation method of embedded non-volatility memory chip, relate in particular to a kind of test pattern implementation method that need not to reserve special test pin embedded non-volatility memory chip.
Background technology
At present, a kind of as DFT (design for Measurability, Drive Fitness Test) designing technique when the design embedded non-volatility memory chip, needs to reserve test pin (PIN) usually, is in test mode or normal operating conditions to be used for discrimination circuit.But caused the many PAD of circuit needs like this, made area increase, the cost of chip also improves thereupon.Especially chip area is being required very high, the number of spendable PIN is very limited, can't a PIN even multiplexing all becoming can't realize the time be set separately for testing, and the shortcoming of this method is especially outstanding.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of test pattern implementation method of embedded non-volatility memory chip, can under the situation of not reserving special test pin, realize test to described chip, and can be transformed under the duty from test mode, thereby can reduce area of chip, also can other normal functions of chip not had any impact.
For solving the problems of the technologies described above, the invention provides a kind of test pattern implementation method of embedded non-volatility memory chip, may further comprise the steps:
(1) the initial address value in the non-volatility memorizer addressing range of built-in chip type is made as the value of characterization test pattern, other values is made as the value that characterizes normal mode of operation;
(2) outside the addressing range of described non-volatility memorizer, introduce an extra extra address, be used for the storage configuration value of statistical indicant;
(3) one two input comparator of use is realized the switching between test pattern and normal mode of operation; The predefined data of the fixing input of one end of described comparer is the initial value of described non-volatility memorizer addressing range, and the other end is imported by described extra address described status flag value pointed; When described status flag value was the initial value of described non-volatility memorizer addressing range, described comparer made the signal of described chip operation under test pattern with output; And when described status flag value was worth for other, described comparer made the signal of described chip operation under normal mode of operation with output.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly be in the state flag bit that test pattern still is a normal mode of operation by outside the addressing range of built-in chip type storer, introducing a sign chip, thereby realized that described chip can change between test pattern and normal mode of operation, realize above-mentioned functions and need not on chip, to increase extra test pin, reduce area of chip to a certain extent, reduced cost; And because the address of described status flag value is outside the addressing range of described built-in chip type storer, therefore when described chip is in normal mode of operation, can't visit again and revise described status flag value, chip when having guaranteed thus to be in normal mode of operation can not enter test pattern more by mistake, thereby has guaranteed safety of data.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the synoptic diagram that two input comparators used according to the invention are implemented in the switching between test pattern and normal mode of operation;
Fig. 2 is an illustrative diagram of introducing the storage area after the extra address of storage configuration value of statistical indicant according to the present invention outside the memory addressing scope;
Fig. 3 is that comparer used according to the invention realizes avoiding the user to misread out the illustrative diagram of the status flag value in the extra address.
Embodiment
Initial address value in the non-volatility memorizer addressing range of built-in chip type is made as the value of characterization test pattern, other values is made as the value that characterizes normal mode of operation; If but under test pattern, need to visit other address values in the described memory addressing scope, then the address value that needs under these test patterns to visit also is made as the value of characterization test pattern, and the value that will be left is made as the value that characterizes normal mode of operation.
Outside the addressing range of the non-volatility memorizer of described built-in chip type, introduce an extra extra address, be used for the storage configuration value of statistical indicant; Why will be with extra address outside the memory addressing scope as the address of described status flag value, be user's normal use to be impacted because can guarantee so not.Therefore can guarantee chip when finishing communication protocol, under the prerequisite that does not influence normal protocol, the status flag value in this extra address be conducted interviews, thereby and need not increase the extra time and increase the extra read cycle and cause the incompatible of communication protocol.By certain logic, make and just can conduct interviews and revise in test pattern following time when chip operation this address, and when it is operated in normal mode of operation, can not conducts interviews and revise this address, thereby can avoid the wrong possibility that enters test pattern when chip is in normal mode of operation, therefore guarantee safety of data.But bring confusion to the user for fear of this status flag value, with described status flag value from this extra address read by described chip read in its circuit inside the back oneself judge, and do not output to the outside of this chip, in case and user mistake is 0 output by phase inverter with the transformation of data of being read then when the data in the described extra address are read.
As shown in Figure 1, one two input comparator of use is realized the switching between test pattern and normal mode of operation.The predefined data of the fixing input of one end of this comparer is the initial value of described non-volatility memorizer addressing range, and other end input is by described extra address described status flag value pointed.When described status flag value was the initial value of memory addressing scope, described comparer made the signal of described chip operation under test pattern with output; And when described status flag value was worth for other, described comparer made the signal of described chip operation under normal mode of operation with output.Wherein, described status flag value default setting is the initial value of described memory addressing scope, thereby can guarantee that chip must be under the test pattern during electrification reset for the first time.When described chip is in test pattern following time, described chip can carry out write operation to the address of described status flag value, thereby has guaranteed when chip testing finishes, and can change described status flag value, thereby make chip be converted to normal mode of operation.In order to improve the reliability of described chip when test pattern is transformed into normal mode of operation, can preestablish a special transition status value, this transition status value should be formed by a plurality of 1 and a plurality of 0, thereby guaranteed when status flag value is written as described transition status value, can enter normal mode of operation reliably, not make the value that writes in this status flag value become the value that is characterized by test pattern and can not be damaged owing to the individual bits in the described status flag value; And be in normal mode of operation following time when described chip, owing at this moment can not conduct interviews again or revise to this address, thereby avoided the possibility that the meeting mistake enter test pattern under normal mode of operation, therefore guarantee safety of data, be highly suitable for the situation that those need be tested chip in the Wafer level.
With a specific embodiment method of the present invention is described below:
With I2C serial EEPROM chip is example, and in the circuit operate as normal, the addressing range of this EEPROM is 00H～7FH, therefore at this moment the extra address of status flag value can be made as 80H, specifically can be with reference to figure 2.
At this moment, because the initial value of EEPROM is 00H, so 00H is made as the characterization test pattern; Simultaneously owing to when testing, carrying out the erasable test of 00H/FFH to EEPROM, so FFH also is made as the value of characterization test pattern.
Therefore reference table 1 when the status flag value in can proper extra address 80H is 00H or FFH, can make described two input comparators make described eeprom chip be operated in signal under the test pattern output, and at this moment chip will be operated under the test pattern; And after formally finishing test, when being written as 55H by the status flag value in extra address 80H, then can make two input comparators output make described eeprom chip be operated in signal under the normal mode of operation, at this moment described chip just is transformed into normal mode of operation from test pattern and has descended; Why with 55H as the transition status value that is transformed into normal mode of operation from test pattern, be because 55H is made up of 4 " 1 " and 4 " 0 ", even can not become 00H or FFH easily so the individual bits in the beautiful value of state is damaged also, thereby improve reliability.
Table 1
| 55H | Normal mode of |
| 00H | Test pattern |
| FFH | Test pattern |
| Other numerical value | Normal mode of operation |
The default 00H that is made as of status flag value among the described 80H, like this when described eeprom chip for the first time during electrification reset, after the I2C communication initial " beginning (Start) ", when circuit can utilize serial input " device address (DeviceAddress) ", status flag value among the 80H is read, read the back owing to being 00H, so can enter test pattern automatically through judgement, so neither can influence normally carrying out of I2C agreement, guarantee that also the data in the zone bit byte are gathered smoothly.
When described eeprom chip is in test pattern; can be to described extra address 80H write data again; when the data that write are 55H; normal mode of operation will be judged and enter to circuit automatically; after entering normal mode of operation, because described extra address 80H is outside the EEPROM addressing range, so the user just can't conduct interviews to this extra address 80H or revise forever again; so before answering end of test (EOT) 80H is write 55H, to protect this status flag value.
After communication next time initial " beginning ", when circuit utilizes serial input " device address " once more, the data among the extra address 80H among the EEPROM are read, at this moment as if judging that chip is in normal mode of operation after the value of reading 55H.
Because extra address 80H is outside the addressing range of EEPROM, therefore the user in use might misread out, status flag value in this extra address 80H is brought confusion to the user, it is oneself to judge after read circuit inside that data are read from this extra address 80H, does not output to chip exterior.By logic control,, then as shown in Figure 3, then can be in advance change the actual value of 55H into 00H output by 4 phase inverters in case client mistake is read the data among this extra address 80H.
Claims (6)
1. the test pattern implementation method of an embedded non-volatility memory chip is characterized in that, may further comprise the steps:
(1) the initial address value in the non-volatility memorizer addressing range of built-in chip type is made as the value of characterization test pattern, other values is made as the value that characterizes normal mode of operation;
(2) outside the addressing range of described non-volatility memorizer, introduce an extra extra address, be used for the storage configuration value of statistical indicant;
(3) one two input comparator of use is realized the switching between test pattern and normal mode of operation; The predefined data of the fixing input of one end of described comparer is the initial value of described non-volatility memorizer addressing range, and the other end is input as by described extra address described status flag value pointed; When described status flag value was the initial value of described non-volatility memorizer addressing range, described comparer made the signal of described chip operation under test pattern with output; And when described status flag value was worth for other, described comparer made the signal of described chip operation under normal mode of operation with output.
2. the test pattern implementation method of embedded non-volatility memory chip according to claim 1 is characterized in that, described status flag value is the initial value of described memory addressing scope under default situations.
3. the test pattern implementation method of embedded non-volatility memory chip according to claim 1 is characterized in that, preestablishes a special transition status value, and this transition status value should be formed by a plurality of 1 and a plurality of 0.
4. the test pattern implementation method of embedded non-volatility memory chip according to claim 1, it is characterized in that, in step (1), if under test pattern, need to visit other address values in the described memory addressing scope, then the address value that needs under these test patterns to visit also is made as the value of characterization test pattern, and the value that will be left is made as the value that characterizes normal mode of operation.
5. the test pattern implementation method of embedded non-volatility memory chip according to claim 1, it is characterized in that, described status flag value from this extra address read by described chip read in its circuit inside the back oneself judge, and do not output to the outside of this chip, in case and user mistake is 0 output by phase inverter with the transformation of data of being read then when the data in the described extra address are read.
6. the test pattern implementation method of embedded non-volatility memory chip according to claim 1, it is characterized in that, when described non-volatile memory chip is in test pattern, can conducts interviews and revise, when described non-volatile memory chip is in normal mode of operation, then can not conducts interviews and revise described status flag value to described status flag value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610147328A CN101202115B (en) | 2006-12-15 | 2006-12-15 | Method for implementing test mode of embedded non-volatility memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610147328A CN101202115B (en) | 2006-12-15 | 2006-12-15 | Method for implementing test mode of embedded non-volatility memory chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101202115A CN101202115A (en) | 2008-06-18 |
| CN101202115B true CN101202115B (en) | 2010-05-19 |
Family
ID=39517205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200610147328A Active CN101202115B (en) | 2006-12-15 | 2006-12-15 | Method for implementing test mode of embedded non-volatility memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101202115B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184130A (en) * | 2010-11-24 | 2011-09-14 | 北京天融信科技有限公司 | Method and device for testing chip assembly lines |
| CN104345265B (en) * | 2013-07-26 | 2018-06-05 | 北京兆易创新科技股份有限公司 | A kind of chip detecting method and device |
| CN110399257A (en) * | 2019-07-04 | 2019-11-01 | 上海创功通讯技术有限公司 | Detection method, electronic equipment and the computer readable storage medium of memory |
| CN113466671B (en) * | 2021-09-06 | 2021-11-23 | 苏州贝克微电子有限公司 | Chip testing method and device based on chip internal circuit structure reconstruction |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455932A (en) * | 2000-08-31 | 2003-11-12 | 恩益禧电子股份有限公司 | Semiconductor storage device, its testing method, and test circuit |
| CN1652248A (en) * | 2003-10-09 | 2005-08-10 | 三星电子株式会社 | Method and memory system in which operating mode is set using address signal |
-
2006
- 2006-12-15 CN CN200610147328A patent/CN101202115B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455932A (en) * | 2000-08-31 | 2003-11-12 | 恩益禧电子股份有限公司 | Semiconductor storage device, its testing method, and test circuit |
| CN1652248A (en) * | 2003-10-09 | 2005-08-10 | 三星电子株式会社 | Method and memory system in which operating mode is set using address signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101202115A (en) | 2008-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7397717B2 (en) | Serial peripheral interface memory device with an accelerated parallel mode | |
| CN1905068B (en) | Non-volatile memory device having improved programming speed and associated programming method | |
| JP4896450B2 (en) | Storage device | |
| CN101243451B (en) | Method and device for protecting embedded memory | |
| KR100248642B1 (en) | Memory ststem and semiconductor memory device used in the same | |
| US10971237B2 (en) | Semiconductor device | |
| US6888733B2 (en) | Multiple chip system including a plurality of non-volatile semiconductor memory devices | |
| US9082469B2 (en) | Semiconductor memory device and writing method of ID codes and upper addresses | |
| CN101236790A (en) | Chip with integrated read-only memory and built-in self-test system and its method | |
| CN103247345A (en) | Quick-flash memory and detection method for failure memory cell of quick-flash memory | |
| CN101202115B (en) | Method for implementing test mode of embedded non-volatility memory chip | |
| US11125816B2 (en) | Method of testing memory device employing limited number of test pins and memory device utilizing same | |
| US6259630B1 (en) | Nonvolatile semiconductor memory device equipped with verification circuit for identifying the address of a defective cell | |
| US20180165012A1 (en) | Memory device, controller, host apparatus, data processing system, computer-readable non-transitory recording medium, operation method of memory device, and operation method of host apparatus | |
| CN104184454A (en) | Circuit connection of SFP chip suitable for multi-type storage, and detection method thereof | |
| US7883020B2 (en) | Smart card and method of testing smart card | |
| JP2009099202A (en) | Semiconductor device | |
| US20090034340A1 (en) | Non-volatile memory control device | |
| EP2207100B1 (en) | System and method for data recovery in a disabled integrated circuit | |
| CN106205726A (en) | The rapid testing technology of eeprom memory | |
| US6785174B2 (en) | Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface | |
| KR102523270B1 (en) | eFuse OTP memory supporting I2C communication and operating method thereof | |
| CN115472206A (en) | Bad block detection method of memory, test equipment and storage medium | |
| CN100530119C (en) | Method and relevant apparatus for providing secondary basic input/output system code through synchronizing monitor and control | |
| US6870383B2 (en) | Semiconductor device with high speed switching of test modes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |