CN100530119C - Method and relevant apparatus for providing secondary basic input/output system code through synchronizing monitor and control - Google Patents
Method and relevant apparatus for providing secondary basic input/output system code through synchronizing monitor and control Download PDFInfo
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- CN100530119C CN100530119C CNB2005100759200A CN200510075920A CN100530119C CN 100530119 C CN100530119 C CN 100530119C CN B2005100759200 A CNB2005100759200 A CN B2005100759200A CN 200510075920 A CN200510075920 A CN 200510075920A CN 100530119 C CN100530119 C CN 100530119C
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Abstract
The invention discloses a method for providing assistance basic I/O system code; this computer has a CPU for carrying out an operating system program. That method: provide one host basic I/O system memory, being used to store host basic I/O system code, implementing on a host model; provide one auxiliary basic I/O system memory, being used to store assist basic I/O system code, implementing on a assist model; Among that host model, if it is failed to check synchronism information of the basic I/O system code on special time, the host basic I/O system code will be forbidden ,and auxiliary basic I/O system code will be used, and set again the computer to exchange pattern from a host model to an assist model.
Description
Technical field
The present invention is relevant for basic input/output system code (Basic Input/Output System code, BIOS code) reparation (recovery), especially referring to a kind ofly provides auxiliary (axiliary) method and the relevant apparatus of basic input/output system code with synchronization monitoring.
Background technology
Basic input/output (Basic Input/Output System, BIOS) (for example: personal computer) quite important for a computing machine.The basic input/output storer (BIOS memory) that is used for storing a basic input/output system code (BIOScode) is generally non-volatile (non-volatile) storer, flash for example known in the art (FLASH) storer.The damage that is stored in the basic input/output system code in the basic input/output storer tends to cause computing machine to operate.
A kind of typical method that is used for head it off, one main (main) basic input/output system code and auxiliary (auxiliary) basic input/output system code are provided, and wherein this main and auxiliary basic input/output system code that helps all is stored in same basic input/output storer.According to the method, if this main basic input/output system code generation memory mapped mistake (memory mapping error), then this secondary basic input/output system code will be performed.Another kind of with the method that solves same problem, then provide a main basic input/output system code and a secondary basic input/output system code, be stored in a main basic input/output storer and a secondary basic input/output system storer respectively, wherein this main and auxiliary basic input/output storer that helps all is connected to same interface, and has the memory capacity of identical size.For example: if the memory capacity of this main basic input/output storer is the 2M position, then the memory capacity of this secondary basic input/output system storer also is the 2M position.According to the method, there are differences if read from a special value of this main basic input/output storer and read between a corresponding numerical value of this secondary basic input/output system storer, then this secondary basic input/output system code will be performed.Compared to the structure of single basic input/output system code, above-mentioned two kinds of methods all need the memory capacity of twice in the requirement of basic input/output memory resource.
Summary of the invention
One of purpose of the present invention is to provide a kind of method and relevant apparatus that a secondary basic input/output system code (auxiliary Basic Input/Output System code, auxiliary BIOScode) is provided with synchronization monitoring.
A kind of computing machine is provided in the preferred embodiment of the present invention, and it includes: a CPU (central processing unit) is used for carrying out an operating system (operation system, OS) program; One main basic input/output storer (main BIOS memory) is coupled to this CPU (central processing unit), is used for storing a main basic input/output system code (main BIOS code), and this main basic input/output system code is executed in the holotype; One control circuit is coupled to this CPU (central processing unit), and wherein this control circuit can be used to carry out synchronization monitoring; And at least one secondary basic input/output system storer (auxiliary BIOSmemory), be coupled to this control circuit, be used for storing a secondary basic input/output system code, this secondary basic input/output system code is executed in the auxiliary mode.In this holotype, if fail to detect to synchronizing information (syncinformation) that should main basic input/output system code in a particular point in time, then this control circuit makes this main and auxiliaryly help basic input/output system code forbidding (disable) respectively, enables (enable), and resets (reset) this computing machine and switch to this auxiliary mode with this holotype certainly.
A kind of method that is used for providing at least one secondary basic input/output system code in a computing machine is provided in the preferred embodiment of the present invention in addition, and this computing machine has a CPU (central processing unit), is used for carrying out an operating system program.This method includes: a main basic input/output storer is provided, is used for storing a main basic input/output system code, this main basic input/output system code is executed in the holotype; At least one secondary basic input/output system storer is provided, is used for storing this secondary basic input/output system code, this secondary basic input/output system code is executed in the auxiliary mode; And in this holotype, if fail to detect to synchronizing information that should main basic input/output system code in a particular point in time, then make this main and auxiliaryly help basic input/output system code forbidding, enable respectively, and reset this computing machine and switch to this auxiliary mode with this holotype certainly.
Description of drawings
Fig. 1 is the synoptic diagram of the computing machine of one embodiment of the invention.
Fig. 2 is the process flow diagram of control circuit shown in Figure 1.
Fig. 3 is the synoptic diagram of the synchronization monitoring that control circuit carried out shown in Figure 1.
Fig. 4 is for being used for replacing the correlation step of step 952 shown in Figure 2 in the variation example of this embodiment.
The main element symbol description
| 100 computing machines |
| 110 CPU (central processing unit) |
| 120,220 interfaces |
| 130,230 basic input/ |
| 210 |
| 212 |
| 214 |
| 216 time control units |
Embodiment
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of the computing machine 100 of the present invention one first embodiment.Computing machine 100 includes a CPU (central processing unit) 110, is used for carrying out an operating system (operation system, OS) program.Computing machine 100 can also comprise the control chip group (not shown) in typical embodiment, for example: north bridge (North Bridge) group and south bridge (South Bridge) chipset, be used for maintaining CPU (central processing unit) 110, north bridge chipset, with the running of the residing motherboard of South Bridge chip group (motherboard).In addition, computing machine 100 also can comprise some memory storage (not shown)s in typical embodiment, for example: random access memory and hard disk.Above-mentioned CPU (central processing unit) 110, operating system program, north bridge chipset, South Bridge chip group, random access memory, with the running and the principle of hard disk, and the connection between the said elements, be all known in the art, so do not give unnecessary details at this.
According to present embodiment, computing machine 100 also includes a main basic input/output storer (main Basic Input/Output System memory, main BIOS memory) 130, one control circuit 210, and at least one secondary basic input/output system storer (auxiliary BIOSmemory) 230, wherein main basic input/output storer 130 all hangs down pin count (Low Pin Count by one with control circuit 210, LPC) interface 120 is coupled to CPU (central processing unit) 110, and (SerialPeripheral Interface SPI) 220 is coupled to control circuit 210 to secondary basic input/output system storer 230 by a serial peripheral interface.The main basic input/output storer 130 and the secondary basic input/output system storer 230 of present embodiment are all non-volatile (non-volatile) storer, especially flash (FLASH) storer.Main basic input/output storer 130 is used for storing a main basic input/output system code (main BIOS code), and this main basic input/output system code is executed in the holotype (main mode).According to present embodiment, this holotype is the general modfel of computing machine 100 normal operations.In addition, secondary basic input/output system storer 230 is used for storing a secondary basic input/output system code (auxiliary BIOScode), and this secondary basic input/output system code is executed in the auxiliary mode (auxiliary mode).According to present embodiment, if this main basic input/output system code is determined and damages, then computing machine 100 switches to this auxiliary mode from this holotype.
As shown in Figure 1, control circuit 210 can drive (assert)/anti-(de-assert) flash that drives and enable (FLASH enable) signal 211 so that (enable/disable) enabled/forbidden to this main basic input/output system code.That is to say, control circuit 210 is enabled signal 211 main basic input/output storer 130 and this main basic input/output system code is therein enabled by driving flash, and control circuit 210 is enabled signal 211 by anti-driving flash in addition and made main basic input/output storer 130 and therein this main basic input/output system code forbidding.Similarly, control circuit 210 also can drive/instead drive that another flash is enabled signal 211A (not shown) so that this secondary basic input/output system code is enabled/forbidden.That is to say, control circuit 210 is enabled signal 211A secondary basic input/output system storer 230 and this secondary basic input/output system code is therein enabled by driving flash, and control circuit 210 is enabled signal 211A by anti-driving flash in addition and made secondary basic input/output system storer 230 and therein this secondary basic input/output system code forbidding.
In the present embodiment, control circuit 210 includes a storage unit 212, for example: a register.Control circuit 210 can utilize storage unit 212 to store a parameter P, and parameter P is used for representing an operating mode in typical embodiment, for example: this above-mentioned holotype or this auxiliary mode.Fig. 2 is the process flow diagram 900 of control circuit 210 shown in Figure 1, wherein step 910,912,914,916, can be executed in this holotype with 918 together with step 920 and 922, step 910,930,950, and 952 then can be executed in this auxiliary mode.As shown in Figure 2, the parameter P of present embodiment includes two, represents this main basic input/output system code and this secondary basic input/output system code enabling/disabled status separately respectively.And for example shown in Figure 2, step 910,930,950, with the 970 inspections actions that have parameter P respectively, according to other embodiments of the invention, check whether parameter P equals 00,01,10, can adjust with 11 order and changed.Please be careful, the initial value of parameter P can be set at 11, so if this main basic input/output system code is determined and damages, then computing machine 100 can switch to this auxiliary mode from this holotype.
In addition, the control circuit 210 of present embodiment also can be used to carry out synchronization monitoring (syncmonitoring).As shown in Figure 1, control circuit 210 also includes a detecting unit 214 and a time control module 216.According to present embodiment, whether control circuit 210 utilizes detecting unit 214 to detect to exist among an analog/digital bus (A/D bus) the signal LAD that low pin count interface 120 transmitted to synchronizing information (sync information) SYNC that should main basic input/output system code, and utilize time control unit 216 control detection unit 214 to detect whether there is synchronizing information SYNC in a particular point in time Ts, to carry out synchronization monitoring.As shown in Figure 2, in step 910, if parameter P equals 11, then step 912 will be performed, so control circuit 210 begins to monitor analog/digital bus signals LAD, to carry out above-mentioned synchronization monitoring.One circulation that comprises step 914 and 916 repeatedly is performed, and the inspection condition up to step 914 and 916 forces this circulation to be interrupted.In step 914, if learning synchronizing information SYNC, control circuit 210 exists, then enter step 916.In step 916, control circuit 210 checks whether the address AD DR of corresponding this synchronizing information SYNC is the address that needs decoding, if address AD DR then enters step 912 to continue to carry out the monitoring of analog/digital bus signals LAD for needing the address of decoding; Otherwise, enter step 918 to stop the monitoring of analog/digital bus signals LAD.According to above-mentioned flow process,, just represent this main basic input/output system code not to be judged as yet and damage as long as the judged result of step 914 is that "Yes" enters step 916.
In this holotype, if fail to detect to synchronizing information SYNC that should main basic input/output system code in particular point in time Ts, then the judged result of step 914 is not for, so enter step 920, control circuit 210 just is set at 01 with parameter P.After step 920, step 922 can be performed, and then control circuit 210 makes this main and auxiliaryly help basic input/output system code forbidding, enable respectively, and resets (reset) computing machine 100 and switch to this auxiliary mode with this holotype certainly.Flow process according to above-mentioned enters step 920 in case the judged result of step 914 is a "No", just represents this main basic input/output system code to be judged as and damages.
See also Fig. 3, the synoptic diagram of the synchronization monitoring that Fig. 3 is carried out for control circuit 210 shown in Figure 1.The present invention utilizes control circuit 210 monitoring synchronizing information SYNC shown in Figure 3, and the rising edge (rising edge) of the corresponding clock signal LCLK of above-mentioned particular point in time Ts, as shown in Figure 3.About the relation between analog/digital bus signals LAD and the clock signal LCLK and related definition can repeat no more in this with reference to low pin count interface specification (LPC specifications).
According to present embodiment, because parameter P Be Controlled circuit 210 in this holotype is set at 01 (shown in step 920), so step 910,930, and 950 in this auxiliary mode, all be performed.After step 950, just enter step 952, then control circuit 210 makes this main basic input/output system code forbidding, and this secondary basic input/output system code is enabled.So this secondary basic input/output system code just is performed, standby as this main basic input/output system code.According to the present invention, because secondary basic input/output system storer 230 is coupled to CPU (central processing unit) 110 by control circuit 210, but not directly be coupled to CPU (central processing unit) 110 by low pin count interface 120, so secondary basic input/output system storer 230 does not need to possess the memory capacity identical with main basic input/output storer 130.Compared to known technology, the memory capacity of secondary basic input/output system storer 230 of the present invention and cost thereof can be lowered accordingly.
What need be careful is, is 00 by the setting value with parameter P, and this main and auxiliary basic input/output system code that helps is all forbidden.Under this situation, after the inspection action of parameter P is performed in step 910,930,950, with 970, just enter step 972, so this main and auxiliary basic input/output system code that helps is all forbidden.
It is similar to this first embodiment that one of this first embodiment changes example, and the computing machine 100 of this variation example has automatic reparation (auto-recovery) function of basic input/output system code in addition in this auxiliary mode.Change in the example in this, step 952 shown in Figure 2 is substituted by step 952-1 shown in Figure 4,952-2 and 952-3.Step 952-1 replaces the main basic input/output system code that damages in the main basic input/output storer 130 with the replica code of this secondary basic input/output system code in the secondary basic input/output system storer 230, to repair this main basic input/output system code.In step 952-2, parameter P Be Controlled circuit 210 is set at 11.In step 952-3, control circuit 210 makes this secondary basic input/output system code forbidding, the main basic input/output system code of reparation is enabled, and reseted signal RST and reset computing machine 100 and switch to this holotype with this auxiliary mode certainly by sending by low pin count interface 120 once again.
One second embodiment of the present invention is similar to this first embodiment, and in this second embodiment, above-mentioned secondary basic input/output system storer shown in Figure 1 230 by replacement for N secondary basic input/output system storer 230-1, the 230-2 similar to it ... with 230-N.So, be stored in respectively this N secondary basic input/output system storer 230-1,230-2 ..., can be scheduled to priority according to one and be selected an execution with N secondary basic input/output system code among the 230-N, as the standby of this main basic input/output system code.According to present embodiment, control circuit 210 also can utilize detecting unit 214 to detect whether to exist to synchronizing information SYNC-1, SYNC-2 that should N secondary basic input/output system code ..., SYNC-N.Control circuit 210 also can utilize time control unit 216 control detection unit 214 in a particular point in time detect whether exist synchronizing information SYNC-1, SYNC-2 ..., one among the SYNC-N, to carry out synchronization monitoring.
One the 3rd embodiment of the present invention is similar to this first embodiment, and in the 3rd embodiment, above-mentioned low pin count interface 120 is a FWH (Firmware Hub, FWH) interface by replacement.
The above only is the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (14)
1. computing machine, it includes:
One CPU (central processing unit) is used for carrying out an operating system program;
One main basic input/output storer is coupled to this CPU (central processing unit), is used for storing a main basic input/output system code, and this main basic input/output system code is executed in the holotype;
One control circuit is coupled to this CPU (central processing unit), and wherein this control circuit can be used to carry out synchronization monitoring; And
At least one secondary basic input/output system storer is coupled to this control circuit, is used for storing a secondary basic input/output system code, and this secondary basic input/output system code is executed in the auxiliary mode;
Wherein in this holotype, if fail to detect to synchronizing information that should main basic input/output system code in a particular point in time, then this control circuit makes this main and auxiliaryly help basic input/output system code forbidding, enable respectively, and resets this computing machine and switch to this auxiliary mode with this holotype certainly.
2. computing machine as claimed in claim 1, wherein this secondary basic input/output system code is used for repairing this main basic input/output system code, and in this auxiliary mode, this control circuit makes this auxiliary, main basic input/output system code forbidding respectively, enables, and resets this computing machine and switch to this holotype with this auxiliary mode certainly.
3. computing machine as claimed in claim 1, wherein this control circuit also includes:
One storage unit is used for storing a parameter;
Wherein this control circuit can set this parameter a numerical value so that this master or secondary basic input/output system code forbid/enable.
4. computing machine as claimed in claim 1, wherein this control circuit also includes:
One detecting unit is used for detecting whether have this synchronizing information; And
One time control module is used for controlling this detecting unit and detects whether there is this synchronizing information in this particular point in time, to carry out synchronization monitoring.
5. computing machine as claimed in claim 1, wherein this main basic input/output storer and this control circuit are coupled to this CPU (central processing unit) by one first interface, this control circuit can detect in the signal that this first interface transmitted whether have this synchronizing information, and this secondary basic input/output system storer is coupled to this control circuit by one second interface.
6. computing machine as claimed in claim 1, wherein this main and auxiliary basic input/output storer that helps is all nonvolatile memory.
7. computing machine as claimed in claim 6, wherein this main and auxiliary basic input/output storer that helps is all flash memory, and this control circuit can drive/instead drive that a flash is enabled signal so that this main basic input/output system code is enabled/forbidden.
8. method that is used in a computing machine, providing at least one secondary basic input/output system code, this computing machine has a CPU (central processing unit), is used for carrying out an operating system program, and this method includes:
One main basic input/output storer is provided, is used for storing a main basic input/output system code, this main basic input/output system code is executed in the holotype;
At least one secondary basic input/output system storer is provided, is used for storing this secondary basic input/output system code, this secondary basic input/output system code is executed in the auxiliary mode; And
In this holotype, if fail to detect to synchronizing information that should main basic input/output system code in a particular point in time, then make this main and auxiliaryly help basic input/output system code forbidding, enable respectively, and reset this computing machine and switch to this auxiliary mode with this holotype certainly.
9. method as claimed in claim 8, wherein this secondary basic input/output system code is used for repairing this main basic input/output system code, and this method also includes:
In this auxiliary mode, make this auxiliary, main basic input/output system code forbidding respectively, enable, and reset this computing machine and switch to this holotype with this auxiliary mode certainly.
10. method as claimed in claim 8, it also includes:
Store a parameter; And
Set this parameter a numerical value so that this master or secondary basic input/output system code forbid/enable.
11. method as claimed in claim 8, it also includes:
Detect whether there is this synchronizing information in this particular point in time, to carry out synchronization monitoring.
12. method as claimed in claim 8, it also includes:
Couple this main basic input/output storer to this CPU (central processing unit) by one first interface;
One control circuit is provided, and it is coupled to this CPU (central processing unit) by this first interface, and wherein this control circuit can be used to carry out synchronization monitoring, and this control circuit can detect in the signal that this first interface transmitted whether have this synchronizing information; And
Couple this secondary basic input/output system storer to this control circuit by one second interface.
13. method as claimed in claim 8, wherein this main and auxiliary basic input/output storer that helps is all nonvolatile memory.
14. method as claimed in claim 13, wherein this main and auxiliary basic input/output storer that helps is all flash memory, and this method also includes:
Drive/instead drive that a flash is enabled signal so that this main basic input/output system code is enabled/forbidden.
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| CNB2005100759200A CN100530119C (en) | 2005-06-01 | 2005-06-01 | Method and relevant apparatus for providing secondary basic input/output system code through synchronizing monitor and control |
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| CNB2005100759200A CN100530119C (en) | 2005-06-01 | 2005-06-01 | Method and relevant apparatus for providing secondary basic input/output system code through synchronizing monitor and control |
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| CN100530119C true CN100530119C (en) | 2009-08-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI427482B (en) * | 2011-10-21 | 2014-02-21 | Feature Integration Technology Inc | A firmware clone system and method of the serial peripheral interface |
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| CN103092705A (en) * | 2011-10-28 | 2013-05-08 | 精拓科技股份有限公司 | System and method for copying firmware by aid of serial peripheral interface |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI427482B (en) * | 2011-10-21 | 2014-02-21 | Feature Integration Technology Inc | A firmware clone system and method of the serial peripheral interface |
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