TW200519943A - Method and memory system in which operating mode is set using address signal - Google Patents

Method and memory system in which operating mode is set using address signal

Info

Publication number
TW200519943A
TW200519943A TW093130620A TW93130620A TW200519943A TW 200519943 A TW200519943 A TW 200519943A TW 093130620 A TW093130620 A TW 093130620A TW 93130620 A TW93130620 A TW 93130620A TW 200519943 A TW200519943 A TW 200519943A
Authority
TW
Taiwan
Prior art keywords
mode
memory system
bit
row
memory
Prior art date
Application number
TW093130620A
Other languages
Chinese (zh)
Other versions
TWI258143B (en
Inventor
Young-Gu Kang
Jong-Hyun Choi
Woo-Seop Jeong
Ki-Ho Jang
Jung-Yong Choi
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020030070311A external-priority patent/KR100560773B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200519943A publication Critical patent/TW200519943A/en
Application granted granted Critical
Publication of TWI258143B publication Critical patent/TWI258143B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The present invention discloses a memory system, a memory device and a method for setting an operation mode of the memory system. The memory system includes a memory unit array; a row and column decoder selecting a row and a column of memory unit array respectively in accordance with a multi-bit addressing signal; and a mode control circuit receiving at least one bit of the multi-bit addressing signal for selecting the row or the column and setting an operation mode of the memory device in accordance with the at least one bit. The operation mode can be one of the burst length mode, the DDL reset mode, the test mode, the CAS latency time mode and the burst type mode.
TW093130620A 2003-10-09 2004-10-08 Method and memory system in which operating mode is set using address signal TWI258143B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030070311A KR100560773B1 (en) 2003-10-09 2003-10-09 Semiconductor memory device capable of controlling burst length without resetting mode of operation and memory system including the same
US10/951,881 US7042800B2 (en) 2003-10-09 2004-09-29 Method and memory system in which operating mode is set using address signal

Publications (2)

Publication Number Publication Date
TW200519943A true TW200519943A (en) 2005-06-16
TWI258143B TWI258143B (en) 2006-07-11

Family

ID=34437023

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093130620A TWI258143B (en) 2003-10-09 2004-10-08 Method and memory system in which operating mode is set using address signal

Country Status (4)

Country Link
JP (1) JP2005116167A (en)
CN (1) CN1652248B (en)
DE (1) DE102004050037B4 (en)
TW (1) TWI258143B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724626B1 (en) 2005-08-29 2007-06-04 주식회사 하이닉스반도체 Circuit for controlling test mode
KR100656464B1 (en) 2005-12-28 2006-12-11 주식회사 하이닉스반도체 Apparatus and method for generating output enable signal of semiconductor memory
US7982511B2 (en) 2006-02-09 2011-07-19 Hynix Semiconductor Inc. DLL circuit and method of controlling the same
KR100695436B1 (en) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 Multi port memory device with serial input/output interface and method for controlling operation mode thereof
KR100799132B1 (en) 2006-06-29 2008-01-29 주식회사 하이닉스반도체 MRS circuit that can change its own default value
CN101202115B (en) * 2006-12-15 2010-05-19 上海华虹Nec电子有限公司 Method for implementing test mode of embedded non-volatility memory chip
JP4984872B2 (en) * 2006-12-15 2012-07-25 富士通セミコンダクター株式会社 Semiconductor memory, semiconductor memory operating method, memory controller and system
KR100892670B1 (en) 2007-09-05 2009-04-15 주식회사 하이닉스반도체 Circuit for Controlling Precharge in Semiconductor Memory Apparatus
JP5471406B2 (en) * 2009-12-18 2014-04-16 日本電気株式会社 Semiconductor verification apparatus and method
CN103336751B (en) * 2013-07-10 2015-12-30 广西科技大学 Addressing function memory controller integrated with storage unit
CN104698917B (en) * 2013-12-10 2018-12-28 爱思开海力士有限公司 The operation mode initialization circuit of semiconductor device and the data processing system for utilizing it
KR102164019B1 (en) * 2014-01-27 2020-10-12 에스케이하이닉스 주식회사 Burst Length control device and semiconductor device including the same
US9471254B2 (en) * 2014-04-16 2016-10-18 Sandisk Technologies Llc Storage module and method for adaptive burst mode
WO2020197925A1 (en) * 2019-03-26 2020-10-01 Rambus Inc. Multiple precision memory system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0929075B1 (en) * 1996-09-26 2003-08-20 Mitsubishi Denki Kabushiki Kaisha Synchronous type semiconductor memory device
JPH10208468A (en) * 1997-01-28 1998-08-07 Hitachi Ltd Semiconductor memory and synchronous semiconductor memory
DE19915081C2 (en) * 1999-04-01 2001-10-18 Infineon Technologies Ag Integrated memory, the memory cells of which are connected to plate lines
JP4011833B2 (en) * 2000-06-30 2007-11-21 株式会社東芝 Semiconductor memory
US6275437B1 (en) * 2000-06-30 2001-08-14 Samsung Electronics Co., Ltd. Refresh-type memory with zero write recovery time and no maximum cycle time

Also Published As

Publication number Publication date
TWI258143B (en) 2006-07-11
DE102004050037A1 (en) 2005-05-12
JP2005116167A (en) 2005-04-28
CN1652248B (en) 2011-06-01
DE102004050037B4 (en) 2015-01-08
CN1652248A (en) 2005-08-10

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees