JP6898498B1 - Memory device and its burst read / write method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device capable of providing a plurality of page start addresses when burst read and burst write are started to improve burst access efficiency, and a burst read / write method thereof. A memory device includes a pSRAM and a controller. The controller is configured to provide external commands to the pSRAM. When the memory device initiates a burst read or burst write operation, the controller provides multiple page start addresses to the pSRAM, which provides the burst read operation or burst write operation based on the order in which the multiple page start addresses were received. Perform a burst write operation. [Selection diagram] Fig. 6

Description

The present invention relates to a memory, and more particularly to a memory device and its burst read / write method.

In recent years, narrowband IoT (NB-IoT = Narrowband-Internet of Things), wearable devices and mobile displays are in demand for LPC memory (low pin count memory) having high access throughput. However, existing LPC memories (eg HyperRAM) do not support high throughput access. On the other hand, SDRAM (Synchronous Dynamic Random-Access Memory, SDRAM) supports a high-speed throughput function by page mode and bank-interleave mode.

In a well-known technique, a Micro Controller Unit (MCU) transmits a read transaction and a write transaction to a pSRAM (pseudo Static Random Access Memory). For read transactions, read data is output on the DQ bus after a latency period defined in the register space. For write transactions, the write data is transmitted to the pSRAM after the wait time.

However, well-known techniques cannot update the read and write addresses if they do not enter standby mode. This is because once read or write is initiated, the DQ bus is occupied by the data signal and no other address or command can be entered into the pSRAM. As a result, data transmission efficiency and access throughput are low.

Therefore, in the present invention, when burst read and burst write are started, a plurality of page start addresses are provided to update the burst access address space without entering the standby mode, thereby increasing the burst access efficiency. A memory device and a burst read / write method thereof are provided.

Embodiments of the present invention provide a memory device including a pSRAM and a controller. The controller is connected to the pSRAM. When the memory device initiates a burst read or burst write operation, the controller provides multiple page start addresses to the pSRAM, which provides the burst read operation or burst write operation based on the order in which the multiple page start addresses were received. Perform a burst write operation.

Another embodiment of the present invention provides a burst read / write method applied to a memory device including a pSRAM and a controller. The burst read / write method provides multiple page start addresses when a burst read operation or burst write operation is started, and performs a burst read operation or burst write operation based on the order in which multiple page start addresses are received. Including doing.

As described above, in the embodiment of the present invention, the memory device and the burst read / write method described above provide a plurality of page start addresses to the pSRAM when the burst read or burst write is started. Therefore, the pSRAM bursts. In the read command cycle or burst write command cycle, it is not necessary to go through the standby mode as in the conventional example, so that multiple page start addresses can be accessed consecutively, and as a result, the data occupancy rate of the DQ bus is improved. This can be achieved and burst access efficiency can be improved.

To better understand the above and other objects, features, and advantages of the present invention, some embodiments in conjunction with the drawings are described below.

The accompanying drawings are included for further understanding of the principles of the present invention, incorporated herein by reference, and constitute a portion thereof. The drawings exemplify embodiments of the present invention and serve to explain the principles of the present invention as well as explain them.

It is the schematic of the memory device of one Embodiment of this invention. It is a circuit block diagram of the pSRAM of one Embodiment of this invention. It is a judgment flow figure of the command bit of one Embodiment of this invention. It is a circuit block diagram of the address latch decoding circuit of one Embodiment of this invention. It is a sequence diagram of the page access order of one Embodiment of this invention. It is a flow chart of the burst read / write method of one Embodiment of this invention.

Referring to FIG. 1, the memory device 10 may include a pSRAM 110 and a controller 120, the controller 120 being connected to the pSRAM 110. In different embodiments, the memory device 10 is a Flash memory, a Ferroelectric Random Access Memory (FRAM), an EEPROM (Electrically-Erasable Programmable Read-Only Memory, EEPROM), or other memory. You may.

In one embodiment, the pSRAM 110 is configured with one DRAM (Dynamic Random Access Memory, DRAM) as a core and an SRAM (Static Random Access Memory, SRAM) as an interface.

Based on design requirements, the controller 120 can be a Central Processing Unit (CPU) or other programmable microprocessor, Digital Signal Processor (DSP), programmable controller, application specific integrated circuit. It may be an application specific integrated circuit (ASIC), or other similar element, or a combination of the above-mentioned elements.

In one embodiment, when the memory device 10 initiates a burst read operation or burst write operation, the controller 120 provides the pSRAM 110 with a plurality of page starting addresses. To do. The pSRAM 110 receives a plurality of page start addresses, and the pSRAM 110 executes a burst read operation or a burst write operation based on the order in which the plurality of page start addresses are received. Specifically, the page start address is used to read or write to the start address of the page burst address of the memory array in the pSRAM 110. The burst read operation is used to burst read in the burst address range in memory based on the page start address, and the burst write operation bursts the write data in the burst address range in memory based on the page start address. Used to light.

By way of example, when the memory device 10 starts a burst read operation or a burst write operation, the controller 120 provides the page start addresses A0 to AN to the pSRAM 110. The pSRAM 110 sequentially receives the page start addresses A0 to AN, and the pSRAM 110 executes a burst read operation or a burst write operation based on the order in which the page start addresses A0 to AN are received. That is, first, a burst read operation or a burst write operation is executed for the page start address A0, then a burst read operation or a burst write operation is executed for the page start address A1, and the page start address AN is subjected to the burst read operation or the burst write operation. Do the same until you perform a burst read or burst write operation. The number of N is not limited in the present invention as it is determined based on the design requirements.

Referring to FIG. 2, the pSRAM 110 includes an input / output circuit 210, a command decoder 220, an address latch decoding circuit 230, and a memory array 240. In one embodiment, the pSRAM 110 may further include other circuits, such as a data path circuit, and the present invention is not limited thereto.

The input / output circuit 210 may be a well-known input / output circuit (IO circuit) or other interface circuit, and in one embodiment, the input / output circuit 210 is connected to the controller 120 and The input / output circuit 210 receives the external command ECMD and the external address EADD from the controller 120, provides the external command ECMD to the command decoder 220, and provides the external address EADD to the address latch decoding circuit 230. This external address EADD includes page start addresses A0 to AN.

The command decoder 220 is connected to the input / output circuit 210, and the command decoder 220 receives the external command ECMD, decodes the external command ECMD, and outputs the external read / write signal ERW and the burst read / write signal BRW to the address latch decoding circuit. Used to provide to 230. In one embodiment, the command decoder 220 may be a well-known command decoder or other decoding circuit.

The address latch decoding circuit 230 is connected to the input / output circuit 210 and the command decoder 220, the address latch decoding circuit 230 receives the external address EADD from the input / output circuit 210, and the external read / write signal ERW and burst read from the command decoder 220. While receiving the write signal BRW, the page start addresses A0 to AN in the external address EADD are sequentially latched based on the external read / write signal ERW and the burst read / write signal BRW, and the burst address BADD is provided to the memory array 240. It is also used to sequentially perform burst read or burst write operations on the memory array 240 based on the page start addresses A0 to AN in the burst address BADD. The number of N is not limited in the present invention as it is determined based on the design requirements.

The memory array 240 is connected to the command decoder 220 and the address latch decoding circuit 230, and the memory array 240 receives the burst address BADD and sequentially burst reads based on the page start addresses A0 to AN in the burst address BADD. Perform an operation or burst light operation. In one embodiment, the memory array 240 may be a well-known sense amplifier, X decoder, Y decoder, and memory cell array, and the present invention is not limited thereto.

With reference to FIGS. 1, 2, and 3, the controller 120 is further configured to provide an external command ECMD to the pSRAM 110. The external command ECMD includes the command address CA, and the command address CA includes the address space bit AS and the page access bit P. In one embodiment, the command address CA may further include a read or write bit, a burst type bit, and the like, and the present invention is not limited thereto.

Referring to FIG. 3, in step S310, the memory device 10 starts a burst read operation or a burst write operation. Subsequently, in step S320, the memory device 10 determines that the burst read operation or burst write operation is register access or memory array access based on the value of the address space bit AS in the command address CA. When the value of the address space bit AS is 1, the process proceeds to step S330. When the value of the address space bit AS is 0, the process proceeds to step S340. In step S330, the pSRAM 110 performs register access, and the register access accesses a register (not shown) in the memory device 10. In step S340, the pSRAM 110 determines whether the memory array access is a page access based on the page access bit P in the command address CA. When the value of the page access bit P is 1, the pSRAM 110 receives the next page start address A1 following the received page start address A0, and executes step S340 once again. This operation is repeated to fetch the required page address, and the value of the page access bit P is set to 0 when fetching the page address AN to be fetched at the end. When the value of the page access bit P is 0, the process proceeds to step S350. Subsequently, in step S350, the pSRAM 110 performs a memory array access, and the memory array access accesses the memory array 240 in the pSRAM 110.

In other words, when the memory device 10 initiates a burst read or burst write operation, the memory device 10 burst reads in the memory array 240 in the pSRAM 110 based on between the value of the address space bit AS and the page access bit P. Determine if you want to perform an operation or burst light operation.

Based on the value of the address space bit AS in the command address CA, it is determined that the burst read operation or burst write operation is the memory array access (that is, AS = 0 in the command address CA in FIG. 5), and the command When it is determined that the memory array access is a page access (that is, P = 1 in the command address CA in FIG. 5) based on the page access bit P in the address CA, the pSRAM 110 is set to the page start addresses A0 to AN. Based on this, the burst read operation or burst write operation is executed in order.

When it is determined that the burst read operation or burst write operation is register access, that is, the address space bit AS = 1 based on the value of the address space bit AS in the command address CA, the pSRAM 110 performs register access. .. When it is determined that the burst read operation or burst write operation is a memory array access, that is, the address space bit AS = 0, based on the value of the address space bit AS in the command address CA, the pSRAM 110 determines that the command address CA Based on the page access bit P in, it is determined whether the memory array access is a page access. When it is determined that the memory array access is a page access, that is, the page access bit P = 1 based on the page access bit P in the command address CA, the pSRAM 110 sequentially captures the page start addresses A0 to AN. .. When the page start address AN is taken in, the page access bit P = 0 is set, and the pSRAM 110 starts the memory array access.

Referring to FIG. 4, the address latch decoding circuit 230 includes an input indicator 410_0 to 410_N, a latch 420_0 to 420_N, and an output indicator 430_0 to 430_N.

The input indicators 410_0 to 410_N are connected in series. Specifically, the input indicator 410_1 is connected to the input indicator 410_0 and is similarly connected until it is connected to the input indicator 410_N. The input indicator 410_0 receives an external read / write signal ERW from the command decoder 220.

Latch 420_0 to 420_N are connected to input indicators 410_0 to 410_N, respectively. Specifically, the latch 420_0 is connected to the input indicator 410_0, the latch 420_1 is connected to the input indicator 410_1, and is similarly connected until the latch 420_N is connected to the input indicator 410_N. The latches 420_0 to 420_N receive the external address EADD including the page start addresses A0 to AN from the input / output circuit 210.

The output indicators 430_0 to 430_N are connected in series. Specifically, the output indicator 430_1 is connected to the output indicator 430_0 and is similarly connected until it is connected to the output indicator 430_N. The output indicators 430_0 to 430_N are connected to latches 420_ to 420_N, respectively, the output indicator 430_0 is connected to latch 420_0, the output indicator 430_1 is connected to latch 420_1, and until the output indicator 430_N is connected to latch 420_N. Connected in the same way. The output indicators 430_0 to 430_N receive the burst read / write signal BRW from the command decoder 220.

In one embodiment, the input indicators 410_0 to 410_N generate latch input control signals LIN_0 to LIN_N based on the external read / write signal ERW, and the latch input control signals LIN_0 to LIN_N are page start addresses in the external address EADD. It is used to latch A0 to AN in sequence to latch 420_0 to 420_N. The output indicator 430_0 to 430_N generates a latch output control signal LOUT_0 to LOUT_N based on the burst read / write signal BRW, and the latch output control signal LOUT_0 to LOUT_N is a page in the external address EADD to which the latch 420_0 to 420_N is latched. The start addresses A0 to AN can be output as the latch address ADDL0, the latch address ADDL1, ... The latch address ADDLN in order, and the burst address BADD is output, and the page start addresses A0 to AN are output to the memory array 240 in order. Used to be able to.

In one embodiment, latches 420_0 to 420_N are used to latch the external address EADD and output the burst address BADD based on the latch input control signals LIN_0 to LIN_N and the latch output control signals LOUT_0 to LOUT_N, and burst. The address BADD is used to sequentially and continuously provide the page start addresses A0 to AN in the external address EADD to the memory array 240 to perform a burst read operation or a burst write operation.

More specifically, as can be seen by referring to FIGS. 4 and 5 at the same time, the chip selection signal / CS is used to select the chip to be read. In the present embodiment, when the chip selection signal / CS reaches a low logic level, the memory device 10 starts a burst read operation or a burst write operation on the chip selected by the chip selection signal / CS. When a burst read operation or burst write operation is started, a burst read operation or burst write operation is executed in the memory array 240 in the pSRAM 110 based on the value of the address space bit AS and the value of the page access bit P in the command address CA. Decide if you want to. When the address space bit AS is 0 and the page access bit P is 1, the pSRAM 110 captures the page start addresses A0 to AN in the external address EADD. The input indicators 410_0 to 410_N generate latch input control signals LIN_0 to LIN_N based on the external read / write signal ERW, and the latch input control signals LIN_0 to LIN_N sequentially assign page start addresses A0 to AN in the external address EADD. Used to latch to latch 420_0 to 420_N. The output indicator 430_0 to 430_N generates a latch output control signal LOUT_0 to LOUT_N based on the burst read / write signal BRW, and the latch output control signal LOUT_0 to LOUT_N is a page in the external address EADD to which the latch 420_0 to 420_N is latched. The start addresses A0 to AN can be output as latch address ADDL0, latch address ADDL1, ... Latch address ADDLN in order, and latch address ADDL0, latch address ADDL1, ... Latch address ADDLN are output as burst address BADD, and the page is displayed. It is used to enable the start addresses A0 to AN to be sequentially output to the memory array 240. The burst address BADD sequentially and continuously provides the page start addresses A0 to AN in the external address EADD to the memory array 240. It should be explained that the plurality of gray areas in FIG. 5 are Don't care.

Referring to FIG. 6, in step S610, when the memory device initiates a burst read or burst write operation, the controller provides a plurality of page start addresses to the pSRAM. Subsequently, in step S620, the pSRAM executes a burst read operation or a burst write operation based on the order in which the plurality of page start addresses are received.

As described above, in the embodiment of the present invention, the memory device and the burst read / write method described above provide a plurality of page start addresses to the pSRAM when the burst read or burst write is started. Therefore, the pSRAM bursts. Multiple page start addresses can be accessed in the read command cycle or burst write command cycle, and burst access efficiency can be improved. Thereby, data transmission efficiency and access throughput can be improved, and system functions can be improved.

As described above, the present invention has been disclosed by an embodiment, but of course, it is not intended to limit the present invention, and as can be easily understood by those skilled in the art, it is appropriate within the scope of the technical idea of the present invention. Moreover, since appropriate changes and amendments can be made, the scope of the patent protection must be determined based on the scope of claims and the area equivalent thereto.

10 Memory device 110 pSRAM
120 Controller 210 Input / Output Circuit 220 Command Decoder 230 Address Latch Decoding Circuit 240 Memory Array 410_0, 410_1, 410_N Input Indicator 420_0, 420_1, 420_N Latch 430_0, 430_1, 430_N Output Indicator ECMD External Command EADD External Address ERW External Read / Write Signal BRW Burst Read / Write Signal BADD Burst Address AS Address Space Bit P Page Access Bits LIN_0, LIN_1, LIN_N Latch Input Control Signals LOUT_0, LOUT_1, LOUT_N Latch Output Control Signals ADDL0, ADDL1, ADDLN Latched Address
/ CS chip selection signal CA command address A0, A1, AN page start address S310, S320, S330, S340, S350, S610, S620 Step

Claims (14)

pSRAM and
With the controller connected to the pSRAM,
When the memory device initiates a burst read operation or a burst write operation, the controller provides a plurality of page start addresses to the pSRAM, and the pSRAM receives the plurality of page start addresses in this order. Based on this, a memory device that executes the burst read operation or the burst write operation. The controller is further configured to provide an external command to the pSRAM, wherein the external command includes a command address.
When the memory device initiates the burst read operation or the burst write operation, the burst read operation or the burst read operation in the memory array in the pSRAM is based on the value of the address space bit and the value of the page access bit in the command address. The memory device according to claim 1, wherein the memory device determines whether or not to execute the burst write operation. Based on the value of the address space bit in the command address, it is determined that the burst read operation or the burst write operation is a memory array access, and based on the value of the page access bit in the command address, the memory. The memory device according to claim 2, wherein when the array access is determined to be page access, the pSRAM executes the burst read operation or the burst write operation based on the order in which the plurality of page start addresses are received. .. When it is determined that the burst read operation or the burst write operation is a register access based on the value of the address space bit in the command address, the pSRAM performs the register access.
When it is determined that the burst read operation or the burst write operation is a memory array access based on the value of the address space bit in the command address, the pSRAM is based on the page access bit in the command address. Determine if the memory array access is a page access
When it is determined that the memory array access is the page access based on the page access bit in the command address, the pSRAM sequentially performs the page access based on the plurality of page start addresses.
The memory device according to claim 2, wherein the pSRAM performs the memory array access after all of the plurality of page start addresses are used to execute the page access. The pSRAM
An input / output circuit connected to the controller and configured to receive external commands and addresses from the controller.
A command decoder connected to the input / output circuit, receiving the external command from the input / output circuit, decoding the external command, and providing an external read / write signal and a burst read / write signal.
It is connected to the input / output circuit and the command decoder, receives the external address from the input / output circuit, receives the external read / write signal and the burst read / write signal from the command decoder, and receives the external read / write signal and the external read / write signal. Based on the burst read / write signal, the plurality of page start addresses in the external address are sequentially latched, the burst address is output to the memory array, and the burst address is sequentially sent to the memory array based on the burst address. An address latch decode circuit configured to perform a burst read or burst write operation against it,
A memory array connected to the command decoder and the address latch decoding circuit, receiving the burst address, and sequentially executing the burst read operation or the burst write operation based on the burst address. ,
The memory device according to claim 1. The address latch decoding circuit
A plurality of series-connected input indicators configured to receive the external read / write signal from the command decoder, and
A plurality of latches, each connected to the plurality of input indicators and configured to receive an external address including the plurality of page start addresses from the input / output circuit.
A plurality of series-connected output indicators, each connected to the plurality of latches and configured to receive the burst read / write signal from the command decoder.
A plurality of latch input control signals used by the plurality of input indicators to sequentially latch a plurality of page start addresses in the external address to the plurality of latches based on the external read / write signal. And so that the plurality of output indicators can sequentially output a plurality of page start addresses in the latched external address as the burst address based on the burst read / write signal. The memory device according to claim 5, wherein a plurality of latch output control signals used in the above are generated. The plurality of latches are used to latch the external address and output a burst address based on the plurality of latch input control signals and the plurality of latch output control signals, and the burst addresses are sequentially used. The memory device according to claim 6, further configured to continuously provide a plurality of page start addresses within the external address to the memory array. Applies to memory devices including pSRAM and controllers
When a burst read operation or a burst write operation is started, a plurality of page start addresses are provided, and a step of executing the burst read operation or the burst write operation based on the order in which the plurality of page start addresses are received is performed. Burst read / write methods including. The controller is further configured to provide an external command to the pSRAM, wherein the external command includes a command address.
When the burst read operation or the burst write operation is started, the burst read operation or the burst write operation is performed in the memory array in the pSRAM based on the value of the address space bit and the value of the page access bit in the command address. The burst read / write method according to claim 6, wherein it is determined whether or not to execute. The burst read operation or the burst write operation is determined to be a memory array access based on the value of the address space bit in the command address, and the memory array access is based on the page access bit in the command address. The burst read / write method according to claim 9, wherein the burst read operation or the burst write operation is executed based on the order in which the plurality of page start addresses are received when is determined to be page access. When it is determined that the burst read operation or the burst write operation is a register access based on the value of the address space bit in the command address, the register access is performed.
When it is determined that the burst read operation or the burst write operation is the memory array access based on the value of the address space bit in the command address, the burst read operation or the burst write operation is based on the value of the page access bit in the command address. Determine if memory array access is page access,
When it is determined that the memory array access is the page access based on the value of the page access bit in the command address, the plurality of page start addresses are fetched.
The burst read / write method according to claim 9, wherein the memory array access is performed after all of the plurality of page start addresses are captured. The pSRAM includes an input / output circuit, a command decoder, an address latch decoding circuit, and a memory array.
The input / output circuit receives an external command and an external address from the controller, and receives the external command and the external address.
The command decoder receives the external command from the input / output circuit, decodes the external command, and provides an external read / write signal and a burst read / write signal.
The address latch decoding circuit receives the external address from the input / output circuit, receives the external read / write signal and the burst read / write signal from the command decoder, and receives the external read / write signal and the burst read / write signal. Based on, the plurality of page start addresses in the external address are sequentially latched, the burst address is output to the memory array, and the burst read operation or the burst read operation to the memory array is performed in order based on the burst address. Perform a burst light operation,
The burst read / write method according to claim 8, wherein the memory array receives the burst address and sequentially executes the burst read operation or the burst write operation based on the burst address. The address latch decoding circuit includes a plurality of input indicators connected in series, a plurality of latches, and a plurality of output indicators connected in series.
The plurality of input indicators receive the external read / write signal from the command decoder.
An external address is received from the input / output circuit by the plurality of latches, and the external address is received from the input / output circuit.
The burst read / write signal is received from the command decoder by the plurality of output indicators.
The plurality of input indicators generate a latch input control signal based on the external read / write signal, which is used to sequentially latch a plurality of addresses within the external address to the latch.
Latch output control used by the plurality of output indicators to allow the latch to sequentially output a plurality of addresses within the latched external address as the burst address, based on the burst read / write signal. The burst read / write method according to claim 12, wherein a signal is generated. The plurality of latches latch the external address and output a burst address based on the plurality of latch input control signals and the plurality of latch output control signals, and the burst addresses are sequentially and continuously. The burst read / write method according to claim 13, wherein a plurality of addresses within the external address are provided.

Images