TWI749598B - Memory apparatus and method of burst read and burst write thereof - Google Patents

Abstract

A memory apparatus includes a pseudo static random access memory and a controller. The controller is configured to provide an external command to the pseudo static random access memory. When the memory apparatus starts a burst read operation or a burst write operation, the controller provides a plurality of page starting addresses to the pseudo static random access memory, so that the pseudo static random access memory sequentially performs the burst read operation or the burst write operation according to the plurality of page starting addresses.

Description

Memory device and its continuous reading and writing method

The present invention relates to a memory, and more particularly to a memory device and its continuous reading and writing method.

Recently, narrowband Internet of Things (NB-IOT), wearable devices, and mobile displays are in demand for low pin count memory with high throughput. However, the existing low-pin-bit memory (such as HyperRAM) does not support high-speed throughput access. On the other hand, Synchronous Dynamic Random-Access Memory (SDRAM) supports high-speed throughput in page mode and bank-interleave mode.

In the prior art, a microcontroller (Micro Controller Unit, MCU) issues a read transaction and a write transaction to a pseudo Static Random Access Memory (pseudo Static Random Access Memory). Regarding the read transaction, after a defined latency period (latency period) in the register space, the read data is output on the DQ bus. Regarding the write transaction, after the delay time, the written data will be transferred to the virtual static random processing memory.

However, if the standby mode is not entered, the conventional technology cannot update the read address and the write address. This is because once the reading or writing is started, the DQ bus will be occupied by the data signal, so it is impossible to input other addresses and commands to the virtual static random processing memory. This will result in lower data transmission efficiency and access throughput.

In view of this, the present invention provides a memory device and a continuous reading and writing method thereof, which are used to provide multiple page start addresses without entering the standby mode when continuous reading or continuous writing is started, so as to improve continuous access efficient.

An embodiment of the present invention provides a memory device. The memory device includes a virtual static random processing memory and a controller. The controller is coupled to the virtual static random processing memory. When the memory device starts a continuous read operation or continuous write operation, the controller provides multiple page start addresses to the virtual static random processing memory, and the virtual static random processing memory receives multiple page start addresses according to Continuous read operation or continuous write operation is performed in the order of the sequence.

The embodiment of the present invention provides a continuous reading and writing method, which is suitable for a memory device, and the memory device includes a virtual static random processing memory and a controller. Continuous read and write methods include: when a continuous read operation or continuous write operation is started, multiple page start addresses are provided, and continuous read operations or continuous write operations are performed according to the order of receiving multiple page start addresses .

Based on the above, in the embodiment of the present invention, when the memory device and its continuous reading and writing method start continuous reading or continuous writing, since multiple page start addresses are provided to the virtual static random processing memory, This allows the virtual static random processing memory to enter the standby mode during the continuous read command cycle or the continuous write command cycle, without the need to enter the standby mode as in the prior art. Therefore, the data occupancy rate of the DQ bus can be increased, and the continuous access efficiency can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1, the memory device 10 may include a virtual static random processing memory 110 and a controller 120, and the controller 120 is coupled to the virtual static random processing memory 11. The memory device 10 may be, for example, a flash memory (Flash memory) or other memory.

In one embodiment, the virtual static random access memory 110 is composed of a dynamic random access memory (Dynamic Random Access Memory, DRAM) as the core and a static random access memory (Static Random Access Memory, SRAM) as the interface. composition.

According to design requirements, the controller 120 may be, for example, a central processing unit (Central Processing Unit, CPU) or other similar elements or a combination of the foregoing elements.

In one embodiment, when the memory device 10 starts a burst read operation (burst read operation) or a burst write operation (burst write operation), the controller 120 may provide multiple page starting addresses (page starting addresses) To the virtual static random processing memory 110. The virtual static random processing memory 110 receives multiple page start addresses, and the virtual static random processing memory 110 performs continuous read operations or continuous write operations according to the order of receiving the multiple page start addresses. Specifically, the page start address is used to read or write the start address of the continuous page address of the memory array in the virtual static random processing memory 110. The continuous read operation is used to continuously read the continuous address range in the memory according to the page start address, and the continuous write operation is used to continuously write the written data into the memory according to the page start address. Address range.

For example, when the memory device 10 starts a continuous read operation or a continuous write operation, the controller 120 may provide the page start address A0~AN to the virtual static random processing memory 110. The virtual static random processing memory 110 sequentially receives the page start addresses A0~AN, and the virtual static random processing memory 110 performs continuous read operations or continuous write operations according to the order of the received page start addresses A0~AN. It means to perform continuous read operation or continuous write operation on the page start address A0 first, and then perform continuous read operation or continuous write operation on the page start address A1, and so on, until the page start bit Address AN performs continuous read operation or continuous write operation. The number of N is determined by design requirements.

2, the virtual static random processing memory 110 includes an input/output circuit 210, a command decoder 220, an address latch decoding circuit 230, and a memory array 240. In an embodiment, the virtual static random processing memory 110 may also include other circuits, such as a data path circuit.

The input-output circuit 210 may be a conventional input-output circuit (IO circuit) or other interface circuits. In one embodiment, the input-output circuit 210 is coupled to the controller 120, and the input-output circuit 210 is used to receive data from the controller 120. The external command ECMD and the external address EADD are provided, the external command ECMD is provided to the command decoder 220, and the external address EADD is provided to the address latch decoding circuit 230. The external address EADD includes the page start address A0~AN.

The command decoder 220 is coupled to the input and output circuit 210. The command decoder 220 receives the external command ECMD and decodes the external command ECMD to provide the external read-write signal ERW and the continuous read-write signal BRW to the address latch decoding circuit 230 . In an embodiment, the command decoder 220 may be a conventional command decoder or other decoding circuit.

The address latch decoding circuit 230 is coupled to the input output circuit 210 and the command decoder 220. The address latch decoding circuit 230 is used to receive the external address EADD from the input output circuit 210 and the external read/write signal ERW from the command decoder 220 And continuous read/write signal BRW, and according to the external read/write signal ERW and continuous read/write signal BRW, sequentially latch the page start addresses A0~AN in the external address EADD to provide continuous address BADD to the memory array 240 , And sequentially perform continuous read operations or continuous write operations on the memory array 240 according to the page start addresses A0~AN in the continuous address BADD. The number of N is determined by design requirements.

The memory array 240 is coupled to the command decoder 220 and the address latch decoding circuit 230. The memory array 240 receives the continuous address BADD, and proceeds sequentially according to the page start addresses A0~AN in the continuous address BADD Continuous read operation or continuous write operation. In an embodiment, the memory array 240 may include conventional sense amplifiers, X decoders, Ý decoders, and memory cell arrays, but is not limited thereto.

1, 2 and 3, the controller 120 is further configured to provide an external command ECMD to the virtual static random processing memory 110. The external command ECMD includes a command address CA, and the command address CA includes an address space bit AS and a page access bit P. In an embodiment, the command address CA may also include a read or write bit, a burst type bit, etc. The present invention is not limited to this.

3, in step S310, the memory device 10 starts a continuous read operation or a continuous write operation. Next, in step S320, the memory device 10 determines whether the continuous read operation or the continuous write operation is a register access or a memory array access according to the value of the address space bit AS in the command address CA. When the value of the address space bit AS is 1, go to step S330. When the value of the address space bit AS is 0, step S340 is entered. In step S330, the virtual static random processing memory 10 performs register access, which is to access a register (not shown) in the memory device 10. In step S340, the virtual static random processing memory 110 further determines whether the memory array access is a page access according to the page access bit P in the command address CA. When the value of the page access bit P is 1, the virtual static random processing memory 110 receives the next page start address A1 after receiving the page access address A0, and performs step S340 again. Repeat this operation to obtain the required page address, and when receiving the last received page address AN, set the value of the page access bit P to 0. When the value of the page access bit P is 0, step S350 is entered. Next, in step S350, the virtual static random processing memory 110 performs memory array access, and the memory array access is to access the memory array 240 in the virtual static random processing memory 110.

In other words, when the memory device 10 starts a continuous read operation or continuous write operation, the memory device 10 determines whether it is performing virtual static random processing according to the value of the address space bit AS and the value of the page access bit P Continuous read operations or continuous write operations are performed in the memory array in the memory 110.

When the continuous read operation or continuous write operation is determined as the memory array access according to the value of the address space bit AS in the command address CA (that is, AS=0 in the command address CA in FIG. 5), And according to the value of the page access bit P in the command address CA, it is determined that the memory array access is page access (that is, when P=1 in the command address CA in FIG. 5), the virtual static random processing memory 110 According to the page start address A0~AN, the continuous read operation or continuous write operation is performed in sequence.

When the continuous read operation or the continuous write operation is determined as the register access according to the value of the address space bit AS in the command address CA, that is, the address space bit AS=1, then virtual static random processing The memory 110 performs register access. When the continuous read operation or continuous write operation is determined as the memory array access according to the value of the address space bit AS in the command address CA, that is, the address space bit AS=0, the memory is processed virtual statically and randomly 110 determines whether the memory array access is a page access according to the page access bit P in the command address CA. When the memory array access is judged to be page access according to the value of the page access bit P in the command address CA, that is, the page access bit P=1, the virtual static random processing memory 110 sequentially receives pages from The starting address is A0~AN. When the page start address AN is received, the page access bit P=0, and the virtual static random processing memory 110 performs memory array access.

4, the address latch decoding circuit 230 includes input indicators 410_0~410_N, latches 420_0~420_N, and output indicators 430_0~430_N.

The input indicators 410_0~410_N are coupled in series. Specifically, the input indicator 410_1 is coupled to the input indicator 410_0, and so on, until it is coupled to the input indicator 410_N. The input indicator 410_0 receives the external read and write signal ERW from the command decoder 220.

The latches 420_0~420_N are respectively coupled to the input indicators 430_0~430_N. Specifically, the latch 420_0 is coupled to the input indicator 410_0, the latch 420_1 is coupled to the input indicator 410_1, and so on, the latch 420_N is coupled to the input indicator 410_N. The latches 420_0~420_N receive the external address EADD from the input/output circuit 210, where the external address EADD includes the page start address A0~AN.

The output indicators 430_0~430_N are coupled in series. Specifically, the output indicator 430_1 is coupled to the output indicator 430_0, and so on, until it is coupled to the output indicator 430_N. The output indicators 430_0~430_N are respectively coupled to the latches 420_0~420_N, wherein the output indicator 430_0 is coupled to the latch 420_0, the output indicator 430_1 is coupled to the latch 420_1, and so on, the output indicator 430_N Coupled to the latch 420_N. The output indicators 430_0~430_N receive continuous read and write signals BRW from the command decoder 220.

In one embodiment, the input indicators 410_0~410_N generate latch input control signals LIN_0~LIN_N according to the external read/write signal ERW, and the latch input control signals LIN_0~LIN_N are used to change the page start address in the external address EADD A0~AN are latched to the latches 420_0~420_N in sequence. The output indicators 430_0~430_N generate latch output control signals LOUT_0~LOUT_N according to the continuous read and write signal BRW. The latch output control signals LOUT_0~LOUT_N are used to make the latches 420_0~420_N latch the external addresses in EADD. The page start address A0~AN are output in sequence as the latched address ADDL0, the latched address ADDL1...the latched address ADDLN, and the continuous address BADD is output to change the page start address A0~AN Sequentially output to the memory array 240.

In one embodiment, the latches 420_0~420_N are used to latch the external address EADD according to the latch input control signal LIN_0~LIN_N and the latch output control signal LOUT_0~LOUT_N to output the continuous address BADD, where the continuous address The BDD is used to sequentially and continuously provide the page start addresses A0 to AN in the external address EADD to the memory array 240 for continuous read operations or continuous write operations.

In detail, referring to FIGS. 4 and 5 at the same time, the chip selection signal /CS is used to select the chip to be read and written. In this embodiment, when the chip select signal /CS transitions to a low logic level, the memory device 10 starts to perform continuous read operations or continuous write operations on the chip selected by the chip select signal /CS. When a continuous read operation or continuous write operation is started, the value of the address space bit AS in the command address CA and the value of the page access bit P are used to determine whether the memory in the virtual static random processing memory 110 is processed. In the volume array 240, a continuous read operation or a continuous write operation is performed. When the address space bit AS is 0 and the page access bit P is 1, the virtual static random processing memory 110 receives the page start addresses A0~AN in the external address EADD. The input indicator 410_0~410_N generates the latch input control signal LIN_0~LIN_N according to the external read/write signal ERW. The latch input control signal LIN_0~LIN_N is used to sequentially latch the page start address A0~AN in the external address EADD Lock to the latches 420_0~420_N. The output indicators 430_0~430_N generate latch output control signals LOUT_0~LOUT_N according to the continuous read and write signal BRW, and the latch output control signals LOUT_0~LOUT_N are used to make the latches 420_0~420_N latch the external addresses EADD The page start addresses A0~AN are output as the latched address ADDL0, the latched address ADDL1...the latched address ADDLN, and the latched address ADDL0, the latched address ADDL1...by The latch address ADDLN is output as a continuous address BADD to output the page start addresses A0 to AN to the memory array 240 in sequence. Wherein, the continuous address BADD sequentially and continuously provides the page start addresses A0 to AN in the external address EADD to the memory array 240. It must be noted that the multiple shaded areas in Figure 5 are in an undetermined state (Don’t Care).

Referring to FIG. 6, in step S610, when the memory device starts a continuous read operation or a continuous write operation, the controller provides a plurality of page start addresses to the virtual static random processing memory. Then, in step S620, the virtual static random processing memory performs a continuous read operation or a continuous write operation according to the order of receiving the start addresses of the multiple pages.

In summary, in the embodiment of the present invention, the memory device and its continuous reading and writing method provide multiple page start addresses to the virtual static random processing memory when starting continuous reading or continuous writing , So that the virtual static random processing memory can access multiple page start addresses in a continuous read command cycle or a continuous write command cycle to improve continuous access efficiency, thereby improving data transmission efficiency and access throughput, And improve system performance.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10: Memory device 110: Virtual static random processing memory 120: Controller 210: Input and output circuit 220: command decoder 230: address latch decoding circuit 240: memory array 410_0, 410_1, 410_N: input indicator 420_0, 420_1, 420_N: latch 430_0, 430_1, 430_N: output indicator ECMD: External command EADD: external address ERW: External read and write signal BRW: Continuous read and write signal BADD: continuous address AS: address space bit P: page access bit LIN_0, LIN_1, LIN_N: latch input control signal LOUT_0, LOUT_1, LOUT_N: latch output control signal ADDL0, ADDL 1, ADDL N: Latched address /CS: Chip selection signal CA: Command address A0, A1, AN: page start address S310, S320, S330, S340, S350, S610, S620: steps

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. FIG. 2 is a circuit block diagram of a virtual static random processing memory according to an embodiment of the present invention. Fig. 3 is a flow chart of judging command bits according to an embodiment of the present invention. 4 is a circuit block diagram of an address latch decoding circuit according to an embodiment of the present invention. FIG. 5 is a timing diagram of a page access sequence according to an embodiment of the invention. Fig. 6 is a flowchart of a continuous reading and writing method according to an embodiment of the present invention.

S610, S620: steps

Claims (14)

A memory device includes: Virtual static random processing memory; and A controller, coupled to the virtual static random processing memory, Wherein, when the memory device starts a continuous read operation or continuous write operation, the controller provides a plurality of page start addresses to the virtual static random processing memory, and the virtual static random processing memory The body performs the continuous read operation or the continuous write operation according to the order of receiving the start addresses of the multiple pages. The memory device according to claim 1, wherein the controller is further configured to provide an external command to the virtual static random processing memory, wherein the external command includes a command address, Wherein, when the memory device starts the continuous read operation or the continuous write operation, it is judged whether it is in the address space according to the value of the address space bit in the command address and the value of the page access bit. The continuous read operation or the continuous write operation is performed in a memory array in the virtual static random processing memory. In the memory device according to claim 2, when it is determined that the continuous read operation or the continuous write operation is the memory array access according to the value of the address space bit in the command address, And when it is determined that the memory array access is a page access according to the value of the page access bit in the command address, the virtual static random processing memory is processed according to the order of receiving the start addresses of the multiple pages The continuous read operation or the continuous write operation. The memory device according to claim 2, wherein When it is determined that the continuous read operation or the continuous write operation is the register access according to the value of the address space bit in the command address, the virtual static random processing memory performs the temporary Memory access When it is determined that the continuous read operation or the continuous write operation is the memory array access according to the value of the address space bit in the command address, the virtual static random processing memory is based on the command The page access bit in the address determines whether the memory array access is page access; When it is determined that the memory array access is the page access according to the value of the page access bit in the command address, the virtual static random processing memory depends on the start address of the multiple pages. To perform the page access in sequence; and After the multiple page start addresses are used for the page access, the virtual static random processing memory performs the memory array access. The memory device according to claim 1, wherein the virtual static random processing memory includes: An input and output circuit, coupled to the controller, configured to receive external commands and external addresses from the controller; A command decoder, coupled to the input-output circuit, is configured to receive external commands from the input-output circuit, and decode the external commands to provide external read-write signals and continuous read-write signals; An address latch decoding circuit, coupled to the input output circuit and the command decoder, and configured to receive the external address from the input output circuit and the external read/write signal from the command decoder And the continuous read/write signal, and sequentially latch the multiple page start addresses in the external address according to the external read/write signal and the continuous read/write signal to output the continuous address to the memory Array, and sequentially perform continuous read operations or continuous write operations on the memory array according to the continuous addresses; and The memory array is coupled to the command decoder and the address latch decoding circuit, and is configured to receive the consecutive addresses so as to perform the consecutive read operations or all the consecutive addresses in sequence according to the consecutive addresses. The continuous write operation. The memory device according to claim 5, wherein the address latch decoding circuit includes: A plurality of input indicators coupled in series, configured to receive the external read/write signal from the command decoder; A plurality of latches, respectively coupled to the plurality of input indicators, configured to receive an external address from the input/output circuit, wherein the external address includes the plurality of page start addresses; and A plurality of output indicators coupled in series, respectively coupled to the plurality of latches, and configured to receive the continuous read and write signal from the command decoder, The plurality of input indicators are configured to be generated according to the external read/write signal to sequentially latch the plurality of page start addresses in the external address to the plurality of latches. A latch input control signal, and the plurality of output indicators are configured to generate according to the continuous read-write signal for causing the latch to start a plurality of pages in the latched external address The initial address sequentially outputs a plurality of latch output control signals of the consecutive addresses. The memory device according to claim 6, wherein the plurality of latches are used for latching the external address to output according to the plurality of latch input control signals and the plurality of latch output control signals A continuous address, wherein the continuous address is configured to sequentially and continuously provide a plurality of page start addresses in the external address to the memory array. A continuous reading and writing method is suitable for a memory device, the memory device includes a virtual static random processing memory and a controller, and the continuous reading and writing method includes: When a continuous read operation or a continuous write operation is started, multiple page start addresses are provided, and the continuous read operation or the continuous write operation is performed according to the order in which the multiple page start addresses are received . The continuous reading and writing method according to claim 8, wherein the controller is further configured to provide an external command to the virtual static random processing memory, wherein the external command includes a command address, Wherein when the continuous read operation or the continuous write operation is started, it is determined whether the virtual static random processing is performed according to the value of the address space bit in the command address and the value of the page access bit The continuous read operation or the continuous write operation is performed in a memory array in the memory. The continuous reading and writing method according to claim 9, wherein when the continuous read operation or the continuous write operation is determined to be the memory array memory according to the value of the address space bit in the command address When it is determined that the memory array access is a page access according to the value of the page access bit in the command address (CA), the continuous sequence is performed according to the order of receiving the start addresses of the multiple pages Read operation or the continuous write operation. The continuous reading and writing method as described in claim 9, wherein When it is determined that the continuous read operation or the continuous write operation is the temporary memory access according to the value of the address space bit in the command address, the temporary memory access is performed; When it is determined that the continuous read operation or the continuous write operation is the memory array access according to the value of the address space bit in the command address, the page access bit in the command address is used The value of the element determines whether the memory array access is a page access; When it is determined that the memory array access is the page access according to the value of the page access bit in the command address, receiving the multiple page start addresses; and After receiving the start addresses of the multiple pages, access the memory array. The continuous reading and writing method according to claim 8, wherein the virtual static random processing memory includes an input and output circuit, a command decoder, an address latch decoding circuit, and a memory array, wherein: Receiving external commands and external addresses from the controller through the input and output circuit; Receiving external commands from the input/output circuit by the command decoder to decode the external commands to provide external read and write signals and continuous read and write signals; The address latch decoding circuit receives the external address from the input/output circuit and receives the external read/write signal and the continuous read/write signal from the command decoder, and according to the external read The write signal and the continuous read/write signal sequentially latch the start addresses of the multiple pages in the external addresses to output the continuous addresses to the memory array, and the sequential addresses are aligned according to the continuous addresses The memory array performs continuous read operations or continuous write operations; and The continuous address is received by the memory array to sequentially perform the continuous read operation or the continuous write operation according to the continuous address. The continuous reading and writing method according to claim 12, wherein the address latch decoding circuit includes a plurality of input indicators coupled in series, a plurality of latches, and a plurality of output indicators coupled in series, wherein Receiving the external read-write signal from the command decoder through the plurality of input indicators; Receiving an external address from the input/output circuit through the plurality of latches; Receiving the continuous read and write signal from the command decoder through the plurality of output indicators; Generating a latch control signal for sequentially latching a plurality of addresses of the external addresses to the latch by the plurality of input indicators according to the external read-write signal; and The plurality of output indicators are generated according to the continuous read/write signal to enable the latch to sequentially output a plurality of addresses of the latched external addresses as the continuous external bits The output control signal of the address. The continuous reading and writing method according to claim 13, wherein the external address is latched by the plurality of latches according to the plurality of latch input control signals and the plurality of latch output control signals To output a continuous address, wherein the continuous address is configured to sequentially and continuously provide a plurality of addresses of the external addresses.

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