JP5256879B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using a DRAM core that requires high-speed operation.

  Conventionally, a burst operation is performed in order to access a semiconductor memory device having a DRAM (Dynamic Random Access Memory) core at high speed. This burst operation is to access (write / read) data for each word by fixing the row address and changing the column address in synchronization with the external clock. Therefore, the burst length is limited to the length of the column address.

  In recent years, along with various uses of semiconductor memory devices, some users require a burst operation with a burst length (BL length) equal to or longer than the column address. is there. Therefore, it is desired to provide a semiconductor memory device having a burst operation function capable of performing data access of a plurality of words beyond data access for each word.

  Generally, a semiconductor memory device (memory) often performs a burst operation when high speed access is required. In this case, the burst operation refers to an address given when a READ / WRITE command (read / write command) is input from the outside as an initial value, and a necessary address thereafter is internally generated to generate an external signal (external clock). (CLK), data input / output with the outside is performed at high speed. An SDRAM (Synchronous DRAM) or the like has such a function. (For example, see Patent Documents 1 to 6.)

  In recent years, burst lengths longer than the column address may be required for burst operations of semiconductor memory devices. That is, as a burst operation of the semiconductor memory device, data access of a plurality of words may be required beyond data access for each word.

Japanese Patent Laid-Open No. 4-157893 JP 10-144073 A JP-A-11-283385 JP 11-353874 A JP 2000-11645 A JP 2000-82287 A

  By the way, in order to realize a burst length (BL length) longer than the column address, it is necessary to change the row address during the burst operation to switch the word line and continue the operation. In addition, when a column signal (CL signal) is output a plurality of times while shifting the timing within one cycle, a CL signal of a plurality of CL signals (signals for extracting cell data in the memory core after activation of the sense amplifier) as necessary -Word lines must be switched between CL signals or after all CL signals are output.

  In addition, when an asynchronous SRAM (Static Random Access Memory) interface (pseudo SRAM) is employed, a burst operation must be performed while performing an internal refresh operation. It is also necessary to deal with requests that overlap. Furthermore, since the burst core needs to operate the memory core at the end of the operation, the recovery time (interval from the end of the operation to the start of the next operation) also becomes long.

  An object of the present invention is to provide a semiconductor memory device that has a burst operation with virtually no limit on the burst length and can minimize the recovery time.

According to the embodiment of the present invention, a semiconductor memory that internally generates a request signal for a refresh operation, performs a burst write operation, and changes a column address and a row address for accessing a memory core during the burst write operation. The device generates a column signal from the final external clock and fetches it into the semiconductor memory device if all the data is fetched when the chip enable signal is deactivated during the burst write operation. Write data to the memory core, then generate a word line reset signal internally, reset the word line to end the burst write operation , and the chip enable signal is deactivated during the burst write operation if there is to unincorporated when data, said final external black The semiconductor memory device is characterized in that the column signal is generated from the chip enable signal instead of the memory and the data taken into the semiconductor memory device is written to the memory core until the chip enable signal is deactivated. Is provided.

  According to the semiconductor memory device of the present invention, it is possible to perform a burst operation with virtually no restriction on the burst length by changing the column address and the row address for accessing the memory core during the burst operation.

  By the way, considering the data input / output timing to the memory core during the burst operation, there is some free time (tCL) in the core operation. The semiconductor memory device according to the present invention performs the switching of word lines and the refresh operation by using this idle time tCL. In addition, when the column signal (CL signal) is output a plurality of times, the semiconductor memory device according to the present invention interrupts word line switching between the CL signals according to the column address. Further, the semiconductor memory device according to the present invention gives priority to the switching of the word lines when the generation of the internal refresh request and the generation of the word line switching request overlap. Furthermore, the semiconductor memory device according to the present invention reduces the recovery time by reducing unnecessary operations at the end of the operation.

  As described above, according to the semiconductor memory device of the present invention, it is possible to perform word line switching and refresh operation during burst operation, and to realize burst operation with virtually no limit on burst length. Time can be minimized.

  According to the present invention, it is possible to provide a semiconductor memory device capable of performing a burst operation with virtually no limitation on the burst length and minimizing the recovery time.

Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram schematically showing the overall configuration of an embodiment of a semiconductor memory device according to the present invention.

  In FIG. 1, reference numeral 1 is a burst column signal generation circuit (burst CL generation circuit), 2 is a column signal output circuit (CL output circuit), and 3 is a word line switching request signal generation circuit (WL switching request signal generation circuit). ) 4 is a word line restart signal generating circuit (WL restart signal generating circuit), 5 is a refresh control circuit, 6 is a second column signal counter (CL2 counter), 7 is an unwritten write request signal generating circuit (unwritten) WR request signal generation circuit), and 8 represents an unwritten write control circuit (unwritten WR control circuit). Reference numeral 9 is a precharge control circuit, 10 is a final write control circuit (final WR control circuit), 11 is a command generation circuit, 12 is a clock logic circuit (CLK logic circuit), and 13 is a burst length counter (BL counter). , 14 is a normal column signal generator (normal CL generator), 15 is a core control circuit, and 16 is an input / output address counter. Reference numeral 17 denotes a burst column timing signal generation circuit (burst CL timing signal generation circuit), 18 denotes an input / output data control circuit, 19 denotes a data latch, 20 denotes an address latch (ADD latch), and 21 denotes a column address counter ( CL address counter), 22 an oscillator (OSC), 23 an address decoder, and 24 a memory core. Note that FIG. 1 does not show all connection relationships between circuit blocks.

  Here, the semiconductor memory device shown in FIG. 1 outputs two column signals (two CL signals: first column signal CL1 and second column signal CL2) in one cycle, and four per one CL signal. This is a case where data for 8 words in total is read / written (READ / WRITE) by CL signals (CL1 and CL2) twice, and READ (latency = 2) will be described as an example. Note that latency = 2 means that a read command (READ command) is input and the first data is output to the outside from the rising edge of the second CLK counted from the rising edge of the first clock (CLK).

  Specifically, four words to be read by one CL signal are extracted from each of four segments selected by addresses A00 and A01, for example. At this time, for example, the address A02 is different between the first column signal CL1 and the second column signal CL2. Here, address A00 = A01 = A02 = low level “L” data is “1” (first word data), and address A00 = A01 = A02 = high level “H” (“1” to “8”). ”(From the first word data to the eighth word data), if the address is A00 = A01 =“ H ”and A02 =“ L ”(“ 4 ”),“ Data “1” to “4” is read out, and data “5” to “8” is read out at CL2. At this time, the first data “1” to “3” are not output to the outside. The next CL signal is output from the CLK that outputs the data “8”. This operation continues until the BL length ends or until there is an EXIT command by changing / CE1 (chip enable terminal) from “L” to “H”.

  The data of 8 words “1” to “8” is read from the memory core 24 to the data latch 19 and latched, and the input / output data control circuit according to the output (CL signal) of the CL output circuit 2 18 from the data terminal (DQ).

  FIG. 2 is a block circuit diagram showing an example of the burst column signal generating circuit 1 and the column signal output circuit 2 in the semiconductor memory device of FIG. 1, and FIG. 3 is a waveform for explaining the basic read operation in the circuit of FIG. FIG.

  As shown in FIG. 2, the burst-system CL generation circuit 1 includes flip-flops 101 to 104, delay lines 105 and 106, and a plurality of logic gates, and the CL output circuit 2 includes inverters 201 and 202, NAND gates. 203 and a NOR gate 204, and the output (/ cl) of the CL output circuit 2 is input to the burst CL generation circuit 1 via the delay line 200.

  As shown in FIG. 2 and FIG. 3, when a command is input, the input (signal) / bact, wlchp, and endmask of the burst CL signal generation circuit 1 are all “L”, and the inputs / endwrp, / pbcl are “H”. The output (signal) / bcl is “H” and the output clmask is “L”.

  When the chip enable signal / CE1 becomes “L”, a READ command is issued and a READ operation is started. The signal pcl is a pulse generated in the normal path from an external command (at the start of a burst operation), and is output at the fastest speed after the command is input, taking the timing from the rise of the word line WL. This signal pcl becomes the first CL signal / cl (first column signal CL1) via the CL output circuit 2. The signal pcl sets the flip-flop 101 in the burst CL generation circuit 1 to set the nodes n01 and n02 to “H” and “L”. The first column signal CL1 (/ cl) output from the CL output circuit 2 is delayed by the delay line 200 and returned to the burst system CL generation circuit 1 as the signal pcl2, and transferred to the node n04 via the NAND gate 107. (At this time, the node n03 is “H”).

  The signal at the node n04 sets the flip-flop 102, and is delayed by the delay line 105 to reset the flip-flop 101, thereby setting the nodes n01 and n02 to “L” and “H”. Since the flip-flop 102 performs a self-reset after the delay by the delay line 106, the output becomes a pulse (/ bcl). The signal / bcl becomes the second CL signal / cl (second column signal CL2) via the CL output circuit 2. Here, the signal pcl2 is generated again from the second column signal CL2, but since the node n01 in the burst CL generation circuit 1 is "L", the node n04 remains "H" and the signal / bcl is not output. The 8 words read from the memory core 24 are latched in the data latch 19 and are output to the outside from the data terminal (DQ) via the input / output data control circuit 18 one word at a time when CLK rises. . The internal address holds an initial value, and thereafter is internally generated by a counter. A00 and A01 are degenerated, and when the CL signal is output, the internal address is incremented from A02.

  When the burst operation is continued, unless the word line WL is raised, pcl is not output after the first CL1 is output. Therefore, the burst CL timing signal generation circuit 17 outputs the data “8”. / Pbcl is output and flip-flops 101 and 102 are set. The flip-flop 102 outputs / bcl similar to the first second column signal CL2, and the signal / cl is output from the CL output circuit 2. In this case, this signal / cl is the next first column signal CL1. become. Thereafter, as described above, the next second ram CL2 is output.

  The above operation continues until the chip enable signal / CE1 becomes “H” (EXIT).

Next, the word line switching operation will be described.
4 is a block circuit diagram showing an example of a word line switching request signal generating circuit, a word line restart signal generating circuit, and a refresh control circuit in the semiconductor memory device of FIG. 1, and FIG. 5 is a word line in the circuit of FIG. FIG. 6 is a waveform diagram (after CL1) for explaining the switching operation, and FIG. 6 is a waveform diagram (after CL1) for explaining the word line switching operation in the circuit of FIG.

  As shown in FIG. 4, the WL switching request signal generation circuit 3 includes a flip-flop 301 and a plurality of logic gates, and the WL restart signal generation circuit 4 includes flip-flops 401 and 402, delay lines 403 and 404, and The refresh control circuit 5 includes flip-flops 501 to 503, a delay line 504, and a plurality of logic gates.

  First, in the burst system CL signal generation circuit 1 shown in FIG. 2, all of the inputs (signals) / bact, wlchp, and endmask are “L” and the outputs (signals) / pbcl are “H”. To do. Addresses A02 to A06 indicate internally generated addresses of columns (in opposite phase to the external addresses). Further, in the WL switching request signal generation circuit 3 shown in FIG. 4, it is assumed that the inputs endwr, ce1b, / actset are “H”, write, stop are “L”, and outputs wlchp, wlch are “L”. Further, in the WL restart signal generation circuit 4 shown in FIG. 4, the input active is a signal that becomes “L” during the activation of the memory core 24, the input stop is “L”, and the output / bact is “H”. In the refresh control circuit 5 shown in FIG. 4, the output refpre is assumed to be “L”. It is assumed that the refresh control circuit 5 does not operate now.

  As shown in FIG. 5, when the word line is switched after the second column signal CL2, when the internal column addresses A02 to A06 are output as the signal CL2, the signal / cl is supplied to the WL switching request signal generation circuit 3 shown in FIG. 4), the switching request signals wlchp (pulse) and wlch (status signal) are output from the WL switching request signal generation circuit 3 in FIG. Here, the signal wlch resets the word lines (WL-0, WL-1) and resets the core control circuit 15. The signal wlchp sets the flip-flops 401 and 402 in the WL restart signal generation circuit 4 in FIG. However, the setting of the flip-flop 402 is later than the timing at which the flip-flop 401 is set by the delay line 403. When the flip-flop 401 is set, the node n05 in the WL restart signal generation circuit 4 in FIG. 4 becomes “L”, and the set information output of the flip-flop 402 is put on standby.

  While the memory core 24 is activated, the input active is “L”, but the timing is set so that the input active becomes “H” at the timing when the reset of the core control circuit 15 ends. When active becomes “H”, the flip-flop 401 is reset, the node n05 becomes “H”, and a pulse (/ bact) having a width determined by the delay line 404 is output. The signal / bact activates the normal path of the operation of the memory core 24, becomes a signal / actset whose timing is adjusted by the delay line 400, and raises the word line. The row address is counted up with the signal / bact. At this time, the signal / bact is input to the burst CL signal generation circuit 1 shown in FIG.

  Since the node n02 in the burst CL signal generation circuit 1 is “H”, the flip-flop 103 is set, and the signal clmask becomes “H”. Since the signal / actset is a normal path signal, pcl is output. Since unnecessary / cl is generated when pcl is output, pcl is stopped in the CL output circuit 2 of FIG. 2 when clmask is “H”. In this way, after outputting the second column signal CL2, the word line is switched from WL-0 to WL-1, and the memory core 24 is in a standby state until the third column signal (the next first column signal CL1) is generated. It becomes. In the meantime, 8-word data held in the data latch 19 is sequentially outputted to the outside through the input / output data control circuit 18 in synchronization with CLK. The signal wlch is reset by the signal / actset, and the signal clmask is held until the next column signal (CL signal) is output.

  When the column address is counted up to the highest level by the second column signal CL2, it is necessary to switch the word line after outputting the third column signal (next first column signal) CL1. In that case:

  The initial state of signals other than the address is the same as when the word line is switched after the second column signal CL2. As shown in FIG. 6, when the first column signal CL1 is output, the signal wlchp and the signal wlch are output, and the word lines (WL-0, WL-1) and the memory core 24 are reset as in FIG. The signal wlchp is input to the burst CL signal generation circuit 1 in FIG.

  Since the node n02 in the burst CL signal generation circuit 1 is “L”, the flip-flop 104 is set, and the node n03 is set to “L”. Since the node n03 is “L”, the signal pcl2 from the first column signal CL1 is stopped and the second column signal CL2 is not output. Similarly to FIG. 5, the signal / bact is output and the next word line (WL-1) rises. Since the signal clmask is “L”, the signal / cl is output from the normal path of / bact → / actset → pc1. This is effectively the second column signal CL2. The signal pcl2 is output from the second column signal CL2. However, since the node n02 in the burst system CL signal generation circuit 1 in FIG. 2 is “L”, the signal pcl2 is stopped and an unnecessary CL is generated after the second column signal CL2. No signal is output. As described above, after the first column signal CL1 is output, the word line is switched from WL-0 to WL-1, and then the second column signal CL2 is output from the normal path. Meanwhile, as in FIG. 5 described above, 8-word data held in the data latch 19 is sequentially output to the outside via the input / output data control circuit 18 in synchronization with CLK. The signal wlch is reset by the signal / actset, and the signal clmask is held until the next column signal is output.

Next, the refresh operation will be described.
FIG. 7 is a waveform diagram for explaining the refresh operation in the circuit of FIG.

  The input (signal) active of the refresh control circuit 5 shown in FIG. 4 is the same as the signal active input to the WL restart signal generation circuit 4, and the input (signal) ref is an internal ring oscillator (22). ), And the input (signal) cl2cnt is a pulse for refresh operation (details will be described later) generated from the second column signal CL2. It is assumed that the outputs (signals) refact and refpre are at “L”. In addition, the initial state of input / output in other circuits is the same as that when switching the word lines.

  First, when the refresh request signal ref is generated, the flip-flop 502 in the refresh control circuit 5 of FIG. 4 is set, and the node n06 becomes “H”. At this time, since the word line is raised (the memory core 24 is activated), the signal active is “L”, the node n07 of the flip-flop 501 is “L”, and the “H” signal is supplied to the node n06. Is waiting for the output. In this state, when the second column signal CL2 is output, the signal cl2cnt is generated. The signal cl2cnt sets the flip-flop 503, and the signal refpre becomes “H”. The signal refpre resets the word line WL and the memory core 24 in the same manner as the signal wlch at the time of switching the word line. Further, the flip-flops 401 and 402 in the WL restart signal generation circuit 4 of FIG. 4 are set in the same manner as the signal wlchp at the time of switching the word line.

  When the memory core 24 is reset and the signal active becomes “H”, the flip-flop 501 becomes “H” and the signal refact is output as a pulse whose width is determined by the delay line 504. At this time, the signal refpre is also reset. The signal refact becomes an activation signal for the refresh operation, and the word line to be refreshed is activated to perform the refresh operation. The signal active becomes “H” before the refresh operation, but during that time, the signal refpre maintains “H”, so that the flip-flop in the WL restart signal generation circuit 4 in FIG. 4 also during the refresh operation. The group 401 holds the set state.

  When the refresh operation ends (auto-precharge) and the signal active becomes “H”, the signal / bact is output and the word line is restarted (the row address is the same as before the refresh) as in the case of switching the word line. To do. At this time, the signal pcl is output from the normal path, but since the signal clmask becomes “H” as in FIG. 5, the signal / cl is not output. Note that when the word line is switched, the signal wlch is “H”, so that the signals refact and refpre are not output.

  As described above, if there is a refresh request, the refresh operation can be performed in the free time (tCL) after the CL signal is output, and then the word line can be restarted.

  Next, the signal cl2cnt input to the refresh control circuit 5 of FIG. 4 will be described.

  FIG. 8 is a block circuit diagram showing an example of the second column signal counter in the semiconductor memory device of FIG. 1, and FIG. 9 is a waveform diagram for explaining the counting operation of the second column signal in the circuit of FIG.

  As shown in FIG. 8, the CL2 counter 6 includes a counter 601, delay lines 602 and 603, and a plurality of logic gates.

  By the way, since the operation of the first memory core in the burst read operation is started asynchronously with the CLK (clock), the interval between the CL signal (orum signal) at that time and the CL signal from the next CLK is reduced. There is. Since the refresh operation cannot be performed within the narrow interval, it is necessary to perform the refresh operation after the CL signal is output from CLK.

  That is, as shown in FIGS. 8 and 9, the CL2 counter 6 always counts the second column signal CL2, outputs the signal cl2cnt when the second column signal CL2 is output, and then again the second column signal. The signal cl2cnt is output at CL2. When a word line switching request is generated, the counter 601 is reset by the signal wlch, and the signal cl2cnt is not output and the word line switching is prioritized. The counter 601 is also reset by a command pulse (CMD) output at the start of the burst operation.

Next, the end of the burst read (burst READ) operation will be described.
FIG. 10 is a block circuit diagram showing an example of an unwritten write request signal generation circuit, an unwritten write control circuit, and a precharge control circuit in the semiconductor memory device of FIG. Here, it is assumed that the inputs (signals) stop, endwr, wlch, and refpre are at “L”.

  The signal ce1b is a signal that becomes “L” when the burst length ends or the EXIT command is generated (the chip enable signal / CE1 changes from “L” to “H”). When the second column signal CL2 is generated (however, when the first column signal CL1 ends, from the first column signal CL1), the signal / rst is output after the completion of the cell restoration in the memory core 24. The flip-flop 901 in the precharge control circuit 9 shown in FIG. In this state, when the burst length ends or an EXIT command is generated, the signal ce1b and the node n13 become “L”, the precharge signal / pre is output, the word line WL and the memory core 24 are reset, and the burst operation is performed. finish. When there is a word line switching request or a refresh operation request, the signals wlch and refpre become “H”, and similarly, the signal / pre is generated to perform the reset operation. Note that the flip-flop 901 in the precharge control circuit 9 is reset by the next CL signal (/ pbcl).

  Next, the end of burst write (burst WRITE) operation will be described. The basic operation is the same as when reading.

  Note that the write operation fetches 8 words of data in synchronization with CLK and reverses the read operation, and generates a CL signal from the rising edge of CLK when it is held (when A00 = A01 = A02 = “H”). In the first column signal CL1, data “1” to “4” (first word data to fourth word data) is generated, and in the second column signal CL2, data “5” to “8” ( 5th word data to 8th word data) are written to the cells of the memory core 24.

  This continues until the burst length (BL length) ends or until there is an EXIT command by changing the chip enable signal (chip enable terminal) / CE1 from “L” to “H”. Here, the write operation is significantly different from the read operation in the case where the operation is terminated at a CLK other than “8” data fetching CLK. In the case of reading, the operation circuit including the memory core may be immediately reset when the BL length ends or the EXIT command is generated. However, in the case of writing, if the BL length ends or the EXIT command is generated when the data “7” is received, the CL signal for writing “1” to “7” is not related to the CLK (asynchronously). Need to be generated.

  FIG. 11 is a waveform diagram (part 1) for explaining an unwritten write operation in the circuit of FIG. 10, and shows a case where the operation ends with the write operation of data “5”. Here, the input (signal) stop of the unwritten WR request signal generation circuit 7 in FIG. 10 is “L”, and “write” is a state signal that becomes “H” at the time of writing.

  The signal WR-CMD input to the unwritten WR request signal generation circuit 7 and the unwritten WR control circuit 8 in FIG. 10 is a command pulse output at the start of the write operation. At the time of writing, the flip-flop 701 of the WR request signal generation circuit 7 and the flip-flop 801 of the WR control circuit 8 are set by the signal WR-CMD. It is assumed that the output (signal) endwr of the unwritten WR control circuit 8 in FIG. 10 is “H”, and the output / endwrp and endact of the unwritten WR request signal generating circuit 7 are “H”. The flip-flop 701 of the WR request signal generation circuit 7 is reset by the signal / pbcl immediately before the output of the CL signal, but is set again by the signal / rst. Further, the flip-flop 702 of the WR request signal generation circuit 7 is set by the signal pcl output when the word line WL rises, and the node n11 is “H”.

  In the above state, when the chip enable signal / CE1 becomes “H” (when the EXIT command is input), if wlch = refpre = “L”, endwr = “H”, but the precharge control of FIG. Since the node n13 in the circuit 9 is “H”, the signal / pre is not output. On the other hand, since the flip-flop 701 of the WR request signal generation circuit 7 is set and the node n10 is at “H”, if ce1b = “L” (and stop = wlch = refpre = “L”), then FIG. 10 unwritten WR request signal generation circuit 7 outputs a pulse whose width is determined by delay line 704 as signal / endwrp. The signal / endwrp sets the flip-flop 703 and simultaneously sets the signal endact to “L” (the signal endact will be described later).

  The signal / endwrp resets the flip-flop 901 in the precharge control circuit 9, and further resets the flip-flop 801 of the unwritten WR control circuit 8 after the delay time by the delay line 802 in the unwritten WR control circuit 8, The signal endwr is set to “L”. Further, the signal / endwrp is input to the burst CL signal generation circuit 1 of FIG. 2 to generate the first column signal CL1, perform the write operation of data “1” to “4”, and then the second time The column signal CL2 is generated in the same manner as the normal burst operation, and the data “5” is written. Thereafter, the signal / rst is generated from the second column signal CL2, and since endwr = “L” and ce1b = “H”, the signal / pre is generated, the reset operation is performed, and the burst write operation is completed.

  The last unwritten write operation is performed asynchronously with CLK. In the above, the unwritten WRITE operation has been described, but there is a problem that the recovery time is long as it is. The reason is shown below.

    (1) If the data “1” to “4” are written, the second column signal CL2 is output although it is not necessary.

    (2) When data “8” is written, the CL signal is output from CLK and the CL signal is written again from the EXIT command even though the CL signal is output from CLK and the data “8” is written. .

    (3) A word line switching request may be generated from a CL signal for unwritten writing, and in this case, a word line switching operation is performed although it is not necessary.

  Therefore, the semiconductor memory device of this embodiment is configured as follows in order to solve the above problem.

  FIG. 12 is a circuit diagram showing an example of a final write control circuit in the semiconductor memory device of FIG. 1, and FIGS. 13 and 14 illustrate an unwritten write operation (operation after taking measures) in the circuits of FIGS. FIG. Here, FIG. 13 shows a waveform when EXIT is written by writing data “4”, and FIG. 14 shows a waveform when EXIT is written by writing data “8”.

  The input (signal) clkp of the final WR control circuit 10 is a pulse generated from the rising edge of CLK during the burst operation, and becomes “L” after EXIT. The signal WA02 is an internal address A02 counted up with CLK (the count-up timing is different from the internal A02 for CL signal). In this circuit, the signal clkp always takes in and latches the signal WA02.

  As shown in FIG. 14, when the data “4” is written, the node n14 is “L” (A02 = “L” is latched), and therefore, when the signal endact is output at the time of unwritten writing, the signal endmask Becomes “H”. The signal endmask is input to the burst CL signal generation circuit 1 in FIG. 2 to stop the signal pcl2 generated from the first column signal CL1 and stop the output of the second column signal CL2. At this time, when endmask = “H”, the signal / rst is generated from the first column signal CL1 (the circuit diagram is omitted), and the word line WL and the memory core 24 are reset from the first column signal CL1 to operate. End. The signal endmask is held until the next command is generated.

  Next, as shown in FIG. 14, when the exit is performed by writing the data “8”, the node n14 is “H”, and since the signal / pbcl is output from the CLK of the data “8”, the flip-flop 1001 is set. As a result, the signal stop becomes “H”.

  The signal stop is input to the unwritten WR request signal generation circuit 7 in FIG. 10, and the generation of the signal / endwrp is stopped. Further, the signal stop is input to the precharge control circuit 9 of FIG. 10 and invalidates the signal endwr. Therefore, if ce1b = “L”, the signal / pre is generated, and the word line WL and the memory core 24 are reset. To finish the operation. The signal stop is held until the next burst operation. As described above, when the exit is performed by writing the data “8”, the unwritten writing is not performed.

  Further, the signal endwr is input to the WL switching request generation circuit 3 in FIG. 4 so that the word switching request (wlchp) is not output during the unwritten writing.

  Further, when the signal stop is input to the WL restart signal generation circuit 4 of FIG. 4 and the exit is performed by writing the data “8”, the word line WL is not restarted. In the case where the exit is performed by writing the data “8” and the word switching request is generated, if the flip-flop 301 in the WL switching request generating circuit 3 in FIG. 4 is not reset, the refresh operation is performed in the standby state thereafter. Since it becomes impossible (wlch = “H”), when stop = “H” and ce1b = “L”, the flip-flop 301 is reset and the signal wlch is set to “L”.

  As described above, according to the embodiment of the semiconductor memory device of the present invention, it is possible to perform the burst operation with virtually no burst length limitation by performing the switching of the word line and the refresh operation during the burst operation, and the recovery time. Can be minimized.

  (Supplementary Note 1) A semiconductor memory device that internally generates a refresh operation request signal and performs a burst operation, wherein a column address and a row address for accessing a memory core are changed during the burst operation. A semiconductor memory device.

  (Supplementary note 2) The semiconductor storage device according to supplementary note 1, wherein the column address selects a sense amplifier connected to a bit line, and the row address selects a word line.

  (Supplementary note 3) In the semiconductor memory device according to supplementary note 2, in the burst operation, an external address is used as an initial address, the column address and the row address are changed in synchronization with an external clock, and the memory core is accessed. A semiconductor memory device, wherein a plurality of data are input / output at a time, and data is input / output to / from the outside in synchronization with the external clock.

  (Supplementary Note 4) In the semiconductor memory device according to Supplementary Note 1, during the burst operation, an address is generated internally, the lower bit of the address is set to the column address, and the upper bit of the address is set to the row address When the column address reaches the highest level, the row address is incremented by the next external clock.

(Supplementary Note 5) In the semiconductor memory device according to Supplementary Note 1, the semiconductor memory device includes:
A semiconductor memory device characterized in that a word line is first activated and a column signal is output in synchronization with an external clock during the burst operation to input / output the data.

  (Supplementary note 6) The semiconductor storage device according to any one of supplementary notes 1 to 5, wherein the memory core is a DRAM memory core that requires a refresh operation.

  (Supplementary note 7) The semiconductor storage device according to supplementary note 6, wherein the word line is not reset until the column address becomes the highest order or a refresh operation is performed.

  (Supplementary note 8) In the semiconductor memory device according to supplementary note 7, when the column address becomes the highest, a word line switching request signal is generated from the column signal at that time, and after the cell restore time in the memory core is secured, A semiconductor memory device, wherein a word line is reset and switched to a word line of a next row address after a preset time interval.

  (Supplementary note 9) In the semiconductor memory device according to supplementary note 8, the word line switching processing after the column address becomes the highest order is performed within a predetermined number of times of the external clock for reading data corresponding to the word line. A semiconductor memory device.

  (Supplementary note 10) The semiconductor storage device according to supplementary note 1, wherein the semiconductor storage device outputs the first column signal in a burst read operation at the highest speed asynchronous with an external clock.

  (Additional remark 11) In the semiconductor memory device according to additional remark 1, if the first column address in the burst read operation is other than the highest column, the highest column -1 or the highest column -2, the word A semiconductor memory device characterized in that data is continuously output even during line switching and synchronization of an external clock is maintained.

  (Supplementary note 12) In the semiconductor memory device according to supplementary note 11, in the burst write operation, the semiconductor memory device always captures external data in synchronization with the external clock even during switching of the word lines. A semiconductor memory device.

  (Supplementary note 13) In the semiconductor memory device according to supplementary note 1, when the semiconductor memory device takes out data from the memory core, it outputs the column signal twice, that is, the first column signal and the second column signal twice. A semiconductor memory device characterized by being taken out separately.

  (Supplementary note 14) In the semiconductor memory device according to supplementary note 13, in the burst write operation, the semiconductor memory device always captures external data in synchronization with the external clock even during switching of the word lines. A semiconductor memory device.

  (Supplementary Note 15) In the semiconductor memory device according to Supplementary Note 13, the first column signal is output in synchronization with the external clock, and the second column signal is provided from the first column signal by an internal delay circuit. A semiconductor memory device characterized by being output after a predetermined time interval.

  (Supplementary note 16) In the semiconductor memory device according to supplementary note 15, when the row address is different between the first column signal output and the second column signal output, the first column signal output and the second column signal output A semiconductor memory device, wherein the word line is switched between the output of a second column signal.

(Supplementary Note 17) In the semiconductor memory device according to Supplementary Note 16, further,
A circuit for stopping the output of the second column signal generated by the internal delay circuit; after switching the word line, a column signal is generated by the same path as the normal path from the next word line rising, A semiconductor memory device characterized by being used as a second column signal.

(Supplementary note 18) In the semiconductor memory device according to supplementary note 17,
A semiconductor memory device comprising: a circuit for stopping the output of the third column signal when the third column signal is used by the internal delay circuit.

  (Supplementary Note 19) In the semiconductor memory device according to Supplementary Note 15, the row address is equal when the first column signal is output and when the second column signal is output, and the row address is changed when the next column signal is output. In this case, the word line is switched from the second column signal before the row address changes.

(Supplementary note 20) In the semiconductor memory device according to supplementary note 19,
2. A semiconductor memory device comprising: a circuit for stopping a column signal when the column signal is to be output after the word line is restarted at the next row address.

  (Supplementary note 21) In the semiconductor storage device according to supplementary note 6, if there is a refresh operation request during the burst operation, the semiconductor storage device waits for a column signal to be output, and waits for a cell in the memory core. A semiconductor memory device characterized by performing a refresh operation by resetting a word line after securing a restore time.

  (Supplementary note 22) In the semiconductor memory device according to supplementary note 21, the refresh operation performed in response to a request for a refresh operation during the burst operation is performed within a predetermined number of times of the external clock for reading data corresponding to the word line. A semiconductor memory device.

  (Supplementary note 23) The semiconductor storage device according to supplementary note 21, wherein data input / output with the outside is performed in synchronization with a continuous external clock.

  (Supplementary Note 24) In the semiconductor memory device according to Supplementary Note 21, when the refresh operation is completed, the word line that was started up before the refresh operation is restarted after a preset time interval. Semiconductor memory device.

  (Additional remark 25) In the semiconductor memory device according to additional remark 6, when the request for both the refresh operation and the word line switching operation occurs during the burst operation, the semiconductor storage device gives priority to the word line switching operation. A semiconductor memory device.

(Supplementary note 26) In the semiconductor memory device according to supplementary note 13, further,
A semiconductor memory device comprising a second column signal counter for counting the second column signal.

(Supplementary note 27) In the semiconductor memory device according to supplementary note 26,
If there is a refresh request during the burst operation, the refresh request is held, and the refresh operation is performed when the second column signal counter counts the second column signal twice.

(Supplementary note 28) In the semiconductor memory device according to supplementary note 26,
2. The semiconductor memory device according to claim 1, wherein the second column signal counter is reset when there is a word line switching request.

(Supplementary note 29) In the semiconductor memory device according to supplementary note 26,
The semiconductor memory device, wherein the second column signal counter is reset immediately after the start of a burst operation.

(Supplementary Note 30) In the semiconductor memory device according to Supplementary Note 1, the semiconductor memory device includes:
If there is an operation end signal during the burst operation, a word line reset signal is generated internally, the word line is reset, and the operation ends.

  (Supplementary Note 31) In the semiconductor memory device according to Supplementary Note 30, if there is remaining data that has not yet been written to the memory core when the operation end signal is generated during a write operation, the operation end signal is used instead of the external clock. A semiconductor memory device, wherein a column signal is generated and the remaining data is written.

  (Supplementary note 32) The semiconductor memory device according to supplementary note 30, wherein the operation end signal is a signal generated internally or given from the outside.

  (Additional remark 33) The semiconductor memory device according to additional remark 1, wherein even when a plurality of column signals are output by one write operation, an unnecessary column signal is not output at the time of unwritten write.

  (Additional remark 34) In the semiconductor memory device according to additional remark 1, even if a word line switching request is generated from a column signal at the time of unwritten writing, the unwritten writing is performed without performing the word line switching operation after the unwritten writing. A semiconductor memory device characterized by resetting the word line to end the burst operation when it is completed.

  (Appendix 35) In the semiconductor memory device according to Appendix 1, if a column signal is generated from the final external clock at the end of the burst write operation, the word line is reset without generating the column signal from the operation end signal. A semiconductor memory device, characterized in that the operation is terminated.

  (Supplementary note 36) The semiconductor memory device according to supplementary note 35, wherein even if a word line switching request is generated by a column signal from the final external clock, the word line is not started up. Storage device.

1 is a block diagram schematically showing an overall configuration of an embodiment of a semiconductor memory device according to the present invention. FIG. 2 is a block circuit diagram showing an example of a burst column signal generation circuit and a column signal output circuit in the semiconductor memory device of FIG. 1. FIG. 3 is a waveform diagram for explaining a basic read operation in the circuit of FIG. 2. FIG. 2 is a block circuit diagram showing an example of a word line switching request signal generation circuit, a word line restart signal generation circuit, and a refresh control circuit in the semiconductor memory device of FIG. FIG. 5 is a waveform diagram (after CL2) for explaining a word line switching operation in the circuit of FIG. 4; FIG. 5 is a waveform diagram (after CL1) for explaining a word line switching operation in the circuit of FIG. FIG. 5 is a waveform diagram for explaining a refresh operation in the circuit of FIG. 4. FIG. 2 is a block circuit diagram showing an example of a second column signal counter in the semiconductor memory device of FIG. 1. FIG. 9 is a waveform diagram for explaining a second column signal counting operation in the circuit of FIG. 8. FIG. 2 is a block circuit diagram illustrating an example of an unwritten write request signal generation circuit, an unwritten write control circuit, and a precharge control circuit in the semiconductor memory device of FIG. 1. FIG. 11 is a waveform diagram (No. 1) for explaining an unwritten writing operation in the circuit of FIG. FIG. 2 is a circuit diagram showing an example of a final write control circuit in the semiconductor memory device of FIG. 1. FIG. 13 is a waveform diagram (No. 2) for explaining an unwritten writing operation in the circuits of FIGS. 10 and 12; FIG. 13 is a waveform diagram (part 3) for explaining an unwritten-in write operation in the circuits of FIGS. 10 and 12;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Burst type | system | group column signal generation circuit 2 Column signal output circuit 3 Word line switching request signal generation circuit 4 Word line restart signal generation circuit 5 Refresh control circuit 6 Second column signal counter 7 Unwritten write request signal generation circuit 8 Unwritten write control Circuit 9 Precharge control circuit 10 Final write control circuit 11 Command generation circuit 12 Clock logic circuit 13 Burst length counter 14 Normal column signal generation unit 15 Core control circuit 16 Input / output address counter 17 Burst column timing signal generation circuit 18 Input / output data Control circuit 19 Data latch 20 Address latch 21 Column address counter 22 Oscillator 23 Address decoder 24 Memory core

Claims (3)

A semiconductor memory device that internally generates a request signal for a refresh operation, performs a burst write operation, and changes a column address and a row address for accessing a memory core during the burst write operation,
If all the data is captured when the chip enable signal is deactivated during the burst write operation , a column signal is generated from the final external clock, and the data captured in the semiconductor memory device is transferred to the memory core. , Then generate a word line reset signal internally, reset the word line and end the burst write operation,
During the burst write operation , if there is data that is not captured when the chip enable signal is deactivated, the column enable signal is generated from the chip enable signal instead of the final external clock, and the chip enable signal A semiconductor memory device, wherein data taken in the semiconductor memory device before the deactivation is written into the memory core.   2. The semiconductor memory device according to claim 1, wherein, even when a plurality of column signals are output in one burst write operation, if a signal for ending the unwritten write is output at the time of unwritten write, it is necessary after that. A semiconductor memory device characterized in that no column signal is output.   2. The semiconductor memory device according to claim 1, wherein even if a word line switching request is generated from a column signal at the time of unwritten writing, the unwritten writing is completed without performing the word line switching operation after the unwritten writing. A semiconductor memory device comprising: resetting the word line to end the burst write operation.

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