JPH06111561A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To make a reading out by a burst accessing at a high speed possible by fetching an access end detection output by an access control circuit and starting the transmission of a series of address specifying information following this detection output. CONSTITUTION:An overall operation is decided by a control circuit 13 using controlling signals CE and OE, the output of a line decoder 15 by an access control circuit 11 inputting an upper address A2-An and the data of an appropriate line is transferred to a sense amplifier 16 and a lin buffer 17. Here, the case of the burst accessing among four addresses is indicated by the lower address of A0-A1 and the output of (m) bit is read out by the output of a word decoder 18 decided by A0 and A1. Then, the fourth address selection of addresses decided by the addresses A0 and A1 is detected by an access end detection circuit 12, data between next addresses is transferred to a buffer 17 by the circuit 11 and the reading out is continuously executed in burst accessing time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used to read data stored in a semiconductor memory device. The present invention relates to a semiconductor memory device that can perform data reading by burst access at high speed.

[0002]

2. Description of the Related Art In the reading of data from a conventional semiconductor memory device, data corresponding to a specified address is output after a lapse of a delay time (hereinafter referred to as an access time) when an address is selected in a pair. . FIG. 5 is a diagram showing the read timing. In recent years, the demand for high-speed access time is increasing for semiconductor memory devices, and data delay time t _ACC from addressing, delay time t _CE from chip enable signal [outer 1], output enable signal [outer 2] from It is necessary to shorten the access time such as the delay time t _OE .

[0003]

[Outer 1]

[0004]

[Outside 2] As a means for responding to such a demand, the process time such as the two-layer metal wiring technology has been used to speed up the access time, but there is a technical limit and a cost problem remains.

Therefore, as a circuit measure, there has been proposed a method of speeding up access between specific addresses by a read method according to the timing shown in FIG. 6, which is 70 + 1 seconds in a normal access time. However, it is shortened to 20 + 1 seconds between specific addresses. This read method is called burst access, and FIG. 4 is a block diagram showing the configuration of a semiconductor memory device by this burst access.

[0006]

In such a conventional burst access method, for example, the access time of the specific addresses A ₀ and A ₁ shown in FIG. 6 is fast, but from other addresses it is the same as the normal access. becomes, can not access the high speed over consecutive addresses, thus between specific address predetermined continuous four addresses (a ₀ -A _1), 8 address (a ₀ -
Since there are cases of A ₂ ), 16 addresses (A ₀ -A ₃ ) ... In the case of continuous 4 addresses, there is a drawback that the normal access time is between 4 addresses and the next 4 addresses.

The present invention solves such a problem, and an object of the present invention is to provide a device capable of high-speed reading by burst access.

[0008]

According to the present invention, a memory array in which data is stored, a peripheral circuit for supporting writing and / or reading of the memory array, and an access control of the peripheral circuit by inputting an address signal are performed. A semiconductor memory device having an access control circuit for performing the access end detection circuit for detecting the final address of a series of address designation information, wherein the access control circuit takes in the detection output of the access end detection circuit and performs the detection. It is characterized by including means for starting the transfer of the next series of address specifying information following the output.

The peripheral circuit is arranged between the line decoder and the word decoder forming the memory array, the sense amplifier for amplifying a minute signal to the memory array, and the data arranged between the sense amplifier and the word decoder. It can include a line buffer for temporarily holding output data and an output buffer for temporarily holding output data.

[0010]

The access end detection circuit detects the final address of the word decoder, and the detection signal is sent to the access control circuit,
It is sent to peripheral circuits such as a word decoder. The access control circuit immediately starts the transfer of the address data of the next address section to the line buffer according to the detection signal.

As a result, it is possible to eliminate the access time conventionally required between the address areas next to the fixed continuous access address area, and to make the access time substantially the same as the burst access time. You can read the data with. In addition, even if a conventional process is used, it can be handled in a circuit manner, and a device that operates at high speed can be manufactured at low cost.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention,
FIG. 2 is a diagram showing operation timings in the first embodiment of the present invention.

In the first embodiment of the present invention, a memory array 14 in which data is stored, a peripheral circuit for supporting writing and reading of the memory array 14, and an address signal are input to perform access control of the peripheral circuit. Access control circuit 11
Further, as a feature of the present invention, an access end detection circuit 12 for detecting the final address of the series of address designation information is provided, and the access control circuit 11 takes in the detection output of the access end detection circuit 12, It includes means for initiating the transfer of the next series of addressing information for the detected output.

The peripheral circuits include a line decoder 15 and a word decoder 18 which constitute the memory array 14, and a sense amplifier 1 which amplifies a minute signal to the memory array 14.
6, a line buffer 17 arranged between the sense amplifier 16 and the word decoder for temporarily holding data,
An output buffer 19 for temporarily holding output data is included.

The control circuit 13 determines the whole operation by the control signals [outer 1] and [outer 2], and the access control circuit 11 determines the output of the line decoder 15 by the input of the upper address A ₂ -A _n. , The data of the corresponding line is transferred to the sense amplifier 16 and the line buffer 17. In the present invention embodiment have the meanings indicated in the case of burst access 4 address range by the lower address A _0, A _1, the output of the m bits are read by the output of Wadodegoda 18 as determined by A _0, A ₁ .

Here, the access end detection circuit 12 detects the fourth address selection of the addresses determined by the addresses A ₀ and A ₁ , and the data of the next address section is controlled by the access control circuit 11 to the line buffer. 2, the access t _ACC during the address section is eliminated as shown in FIG. 2, and continuous reading is performed at the burst access time t _BAC .

FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. The difference from the first embodiment is that a word address setting circuit 22 that can arbitrarily set a burst access section is provided, and 4 addresses A ₀ and A _1
0 -A ₂ 8 addresses, it is possible to arbitrarily set the 16 addresses A ₀ -A _3. Therefore, it is possible to output data at high speed by burst access and change the address section as needed.

[0018]

As described above, according to the present invention, in the data read by the burst access, the access time conventionally required between the address section next to the fixed continuous access address section is provided by the burst access. Since it can be the same as the access time, data can be read out at high speed, and since it can be handled in a circuit even using a conventional process, a device that operates at high speed can be manufactured at low cost. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing operation timing in the first embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a diagram showing a read timing in a conventional example.

FIG. 6 is a diagram showing operation timing in a conventional example.

[Explanation of symbols]

 11, 21, 31 Access control circuit 12 Access end detection circuit 13 Control circuit 14 Memory array 15 Line decoder 16 Sense amplifier 17 Line buffer 18 Word decoder 19 Output buffer 22 Word address setting circuit

Claims (2)

[Claims] 1. A memory array for storing data, a peripheral circuit for supporting writing and / or reading of the memory array, and an access control circuit for inputting an address signal to control access to the peripheral circuit. In the semiconductor memory device, an access end detection circuit for detecting the final address of a series of address designation information is provided, and the access control circuit takes in the detection output of the access end detection circuit, A semiconductor memory device comprising means for initiating transfer of addressing information. 2. The peripheral circuit is arranged between a line decoder and a word decoder forming the memory array, a sense amplifier for amplifying a minute signal to the memory array, and the sense amplifier and the word decoder. 2. The semiconductor memory device according to claim 1, further comprising a line buffer that temporarily holds data and an output buffer that temporarily holds output data.