JPH08195080A - Dram element - Google Patents

Abstract

PURPOSE: To access a continuous data block extending over adjacent and different row addresses at high speed. CONSTITUTION: The row address and a column address inputted from a DRAM controller 1 to a DRAM 2 are inputted to the memory cell 2a of the DRAM 2 respectively through a row address buffer/decoder 3, a column address buffer/ decoder 4. An AND circuit 5 inputting the column address inputted from the DRAM controller 1 is provided, and the fact that all bits of the column address become one is detected by the AND circuit 5 in page mode access, and the row address of the row address buffer 3 is increased automatically according to that.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM device, and more particularly to a DRAM for data input / output by page mode access.
It is related to the element.

[0002]

2. Description of the Related Art Conventionally, a DRAM row address is fixed and a column address is changed.
A so-called page mode access method is known in which reading and writing are performed at high speed on a DRAM.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In AM, page mode access is valid only within the same row address, and high-speed access is possible for data at the same row address, but continuous data blocks that span adjacent different row addresses are accessed. In this case, it is necessary to set the row address again at a position where the row address changes from the DRAM controller, which causes a problem of impairing high speed access.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a DRAM device capable of accessing a continuous data block extending over adjacent different row addresses at high speed.

[0005]

In order to solve the above problems, in the present invention, in a DRAM device for performing data input / output by page mode access, all column addresses supplied to the DRAM device in page mode access. Is provided with a detecting means for detecting that all the bits have become 1, and when the detecting means detects that all the bits have become 1, the row address in the buffer for supplying the row address is incremented. Adopted.

[0006]

With the above configuration, the row address can be automatically incremented in page mode access.
It is possible to access a continuous data block across different row addresses adjacent to each other at high speed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 1 shows the structure of a DRAM device adopting the present invention. In the figure, reference numeral 2 is a DRAM, and data input / output, address control, and refresh of the DRAM 2 are performed by the DRAM controller 1. DR
The AM controller 1 decodes the linear addresses AD0 to ADi into row addresses and column addresses when inputting / outputting data to / from the DRAM 2. The DRAM controller 1 also controls the page mode access of the DRAM 2.

The row address and column address input from the DRAM controller 1 to the DRAM 2 are input to the memory cell 2a of the DRAM 2 via the row address buffer / decoder 3 and the column address buffer / decoder 4, respectively.

When the DRAM 2 is set to the page mode access mode, the row address buffer / decoder 3 is fixed to the row address input from the DRAM controller 1. Then, by sequentially incrementing the column address via the column address buffer / decoder 4, it is possible to read and write the memory cell 2a at high speed.

The operation within the same row address is as described above and is the same as the conventional one. However, in this embodiment, the DRAM controller 1 is used in order to access the continuous data blocks across the adjacent different row addresses at high speed. An AND circuit 5 for inputting the column address input from is provided, and the output of the AND circuit 5 is connected to the clock terminal 6 of the row address buffer / decoder 3.

In this embodiment, the row address buffer / decoder 3 can be incremented by hitting the clock terminal 6 in page mode access without resetting the row address once set.

Therefore, in the page mode access operation, when accessing a continuous data block across different row addresses adjacent to each other, the DRAM controller 1 sets DR after setting the first row address.
The row address is automatically incremented when the column address is full bit (all the bits have become 1) under the control of the AND circuit 5 in the AM2, and a continuous data block spans adjacent different row addresses. You will be able to access at high speed.

Further, according to the present embodiment, since it is not necessary to reset the row address at the change point of the row address as in the conventional case, the structure of the DRAM controller 1 and the processing at the time of page mode access are simplified. It

[0015]

As is apparent from the above, according to the present invention, in a DRAM device which performs data input / output by page mode access, all bits of the column address supplied to the DRAM device are set to 1 in page mode access. Since the detection means for detecting that the row address has been detected is provided, and when the detection means detects that all the bits have become 1, the row address in the buffer for supplying the row address is incremented. ,
In page mode access, the row address can be automatically incremented, continuous data blocks that span different adjacent row addresses can be accessed at high speed, and the configuration and processing load of the DRAM controller can be reduced. A DRAM device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a DRAM and a DRAM controller adopting the present invention.

[Explanation of symbols]

 1 DRAM controller 2 DRAM 2a memory cell 3 row address buffer / decoder 4 column address buffer / decoder 5 AND circuit 6 clock terminal

Claims (1)

[Claims] 1. A DRAM device for inputting / outputting data by page mode access is provided with detection means for detecting that all bits of a column address supplied to the DRAM device have become 1 in page mode access. DR which increments the row address in the buffer supplying the row address when it is detected by the means that all bits have become 1
AM element.