JPH07192458A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the interval of a read-out time by assigning continuously supplied read-out addresses to plural memory arrays in rotation and reading out data from respective memory arrays while overlapping them at the time of a read-out mode. CONSTITUTION:At the time of the read-out mode, addresses supplied continuously by the address control parts of corresponding address latches 107 and column decoders, etc., are assigned to respective memory arrays 110 in rotation. Then, since data are read out from respective arrays 110 while being overlapped, the interval of a data read-out time is shortened and a high speed read-out access is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable as a memory around a CPU that requires high speed access.

[0002]

2. Description of the Related Art Conventional semiconductor memory devices usually have one set of memory circuit and control circuit for one address.
FIG. 4 schematically shows a configuration of a conventional semiconductor memory device, which includes an address signal for designating an address from outside, an address latch signal for instructing fetching of the address signal, a write mode (L) / read mode. A write enable signal / WE designating (H) and write data Din are supplied to the semiconductor memory device. Further, read data Dout is output from the semiconductor memory device.

In the write mode of the semiconductor memory device, an address signal, an address latch signal ALE, a write enable signal / WE (L level), and write data Din are supplied. The address signal is supplied to the address buffer 2 via the address input terminal 1. The address signal supplied to the address buffer 2 is fetched by the address latch 3 which operates in response to the address latch enable signal ALE supplied to the input terminal 4. Address latch 3
Divides the held address signal into high-order bits and low-order bits and supplies them to the row decoder and the column decoder of the memory section 5 to select the address (storage area) of the memory array corresponding to the address signal. Write data Din
Is supplied to the input buffer 8 via the data input terminal 7. The data input / output / sense amplifier control circuit 9 supplies the data signal held in the input buffer 8 to the sense amplifier 10 in response to the write enable signal / WE (L), and is addressed by the row decoder and the column decoder. The write data Din is written in the area.

In the read mode, the address signal, the address latch signal ALE and the write enable signal / WE (H level) are supplied. The address signal is supplied to the address buffer 2 via the address input terminal 1 and taken in by the address latch 3 by the address latch enable signal ALE. The address latch 3 supplies the held address signal to the row decoder and the column decoder of the memory unit 5, and selects the address (storage area) of the memory array corresponding to the address signal. The data input / output / sense amplifier control circuit 9 uses the write enable signal / WE
In response to (H), the signal held in the memory cell at the corresponding address is read out by the sense amplifier 10 and taken out by the output buffer 11. The read data Dout is output from the output buffer 11 to the data output terminal 12.

[0005]

In the conventional circuit having such a configuration, one memory circuit corresponds to one memory address, and the peripheral circuit that accesses this memory circuit is always dedicated to reading one data. The time required to access one piece of data is determined by the sum of the delay times in the respective constituent circuits such as the input circuit, the control circuit, the memory circuit, the output circuit, etc. When accessing a plurality of n pieces of data, It takes about n times as long as the time required to access one data. Therefore, in order to realize high speed access, the operation of the element itself is accelerated.

However, there is a limit to the speeding up of elements, and if the conventional manufacturing process cannot be used for production, an expensive semiconductor memory device is not preferable.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of high speed access by devising the entire structure of the semiconductor device.

[0008]

In order to achieve the above object, the semiconductor memory device of the present invention comprises a plurality of memory cell array portions (108, 109, 110) for holding a data signal in a memory location corresponding to a given address signal, and a write controller. In the write mode, continuously supplied write address signals are commonly applied to each of the plurality of memory cell array sections, and in the read mode, continuously supplied read address signals are sequentially provided to each of the plurality of memory cell array sections. And the address control section (106, 107) to be distributed to the plurality of memory cell array sections in common in each of the plurality of memory cell array sections in the write mode. Data input / output control unit (111, 1) that sequentially selects each data that is read from each unit
12) and are provided.

[0009]

According to the structure of the present invention, writing of data to the semiconductor memory device is performed so that a plurality of memory cell arrays share the same data group. Then, the data read is
Read addresses that are continuously supplied are sequentially distributed to a plurality of memory cell arrays, and data is read by overlapping the memory cell arrays. The data read from each memory cell array is selected corresponding to the order in which the addresses are given, and is made continuous read data.

As a result, since the data reading is continuously performed in an overlapping manner, the continuous data reading time is greatly shortened.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, 101 is an address input terminal, 102 is an address buffer, 103 is an address transition detection circuit for detecting an address transition, and 104 is a write enable signal / WE.
Input terminal of the write enable signal / WE, 105 is an input buffer of the write enable signal / WE, and 106 is the output signal of the address transition circuit 103 and the write enable signal / WE for taking in the address signal supplied to the address buffer 102 to the address latch 107. It is an address latch control circuit which is controlled based on the above. N address latches 107 are prepared from address latches 1 to n. The address latch control circuit 106 and the address latch 107 form an address control unit. Reference numeral 108 is a row decoder that decodes the upper address supplied from the address latch 107 to select the word line, 109 is a column decoder that decodes the lower address supplied from the address latch 107 to select the bit line, and 110 is , A memory cell array that holds or reads a data signal in a memory location selected by a word line and a bit line of a row decoder 108 and a column decoder 109. Row decoder 108, column decoder 10
9, n memory cell arrays 110 are prepared as one set. The row decoder 108, the column decoder 109, and the memory cell array 110 form a memory cell array section. 111
Is a sense amplifier that amplifies the level of the data signal held in the memory cell. N sense amplifiers 1 to n are prepared. Reference numeral 112 denotes a sense amplifier and data input / output, and an address transition detection circuit 103.
I / O / sense amplifier control circuit, which controls in response to the output signal and the write enable signal / WE of the IC
Reference numeral 12 constitutes an input / output data control unit. Reference numeral 113 is a data output buffer, and 114 is a data output terminal. 11
5 is an input terminal of the data signal Din, 116 is a data signal D
The buffer for in.

Next, the write mode for writing the data signal Din to the memory cell array will be described with reference to FIG. First, in the write mode, the write enable signal / WE
Is at the L level. The address buffer 102 outputs address signals Am-1, Am, Am + 1, Am + 2, .... The clock φ is output from the address transition detection circuit 103 in synchronization with the change of the address. The address latch control circuit 106 addresses the control signal at the same timing so that all the address latches 1 to n take in the same address signal in response to the L level of the write enable signal / WE and the generation of the clock φ. Apply to latches 1-n. As a result, the cells of the same address in each memory cell array are selected with respect to the same address signal.

On the other hand, the write data Din supplied to the input terminal 115 is supplied to the data input / output / sense amplifier control circuit 112 via the input buffer 116. In the write mode, the data input / output / sense amplifier control circuit 112
Is the write data Din supplied from the input buffer 116.
Is commonly applied to each of the bus lines 1 to n. This allows
The write data Din is branched into a plurality of lines via the data bus lines 1 to n and the sense amplifiers 1 to n, and the same content is written in the selected memory cell in each memory cell array.

The reading of the data Dout from the memory cell will be described with reference to FIG. In the read mode, write enable signal / WE is set to H level. When the address signal is supplied to the input terminal 101, it is supplied to the address transition circuit 103 via the address input buffer 102. The address transition circuit 103 generates the clock φ in synchronization with the address transition. The address latch control circuit 106, in the H level state of the write enable signal / WE, synchronizes with the address latch 1 in synchronization with the clock φ.
Sequentially enable n. After the latch n, the latch operation in which the latch 1 is enabled and the circuit is circulated is repeated. For example, read addresses Am, Am + 1, Am + 2, ...
When Am + (n-1) is sequentially supplied, address latch 1
, Am + 1 in the address latch 2, Am + 2 in the address latch 3, Am + 3 in the address latch 4, ..., And Am + (n-1) in the address latch n. When the address latches 1 to n are sequentially enabled, the address input of each memory cell array is, for example, Am at the memory cell array 1 and Am at the memory cell array 2.
Address +1 is assigned to the memory cell array 3 at address Am + 2, .... Therefore, the memory cell array 1 starts accessing the address m, and the memory cell array 2
Starts accessing the address m + 1 without waiting for the operation of the memory cell array 1 to end. The memory cell array 3 starts accessing the address m + 2 without waiting for the operation of the memory cell arrays 1 and 2 to end. Such an access without waiting for the completion of the reading of the other memory cell arrays is performed for the n memory cell arrays, and random reading is realized. Each of the read data output from the memory cell arrays 1 to n is supplied to the data input / output / sense amplifier control circuit 112 via the sense amplifiers 1 to n and the bus lines 1 to n, respectively.
The data input / output / sense amplifier control circuit 112 time-divisionally selects each output of the data bus lines 1 to n by using the clock φ, and the read data Dm, Dm + 1 corresponding to the order of the read addresses. , Dm + 2, ..., Dm + n are sequentially derived to the output buffer 113. Read data Dm
, Dm + 1, ... Are output buffers 113 and output terminals 11
It is output to the outside as output data Dout via 4.

The waiting time from the input of the read address to the output of the data is the access time TACC of each memory cell array, which is the same as the conventional case for one data, but the read operation of each memory cell array is overlapped. Therefore, the write data is read from the second read data in the time am of the read address. Output data D
The read cycle time dm of m is proportional to the cycle time am of the corresponding read address Am.

Thus, according to the present invention, in the write mode, the write data is simultaneously written to the same address of the plurality of memory cell arrays, and in the read mode, the read addresses are sequentially provided to the plurality of memory cell arrays, and each memory cell array is provided. Are operated in an overlapping manner, the data reading speed is significantly increased. Therefore, the semiconductor device of the present invention is a CPU that requires a high-speed operation such as a cache memory.
It is suitable for use as a peripheral memory.

In the data read mode, access will normally be made in the order of arrangement of the memory cell arrays corresponding to the order of supply of the address signals, but discontinuous arrangement order according to a certain rule. Of course, it is also possible to access each memory cell array in the order of and to select the output data of the memory cell array corresponding to this discontinuous order, and there are a plurality of modes in this order. And the same result can be obtained.

[0018]

As described above, according to the semiconductor memory device of the present invention, the data writing time is the same as that of the conventional device, but the data reading is performed one after another with each memory cell array overlapping. Therefore, the read time interval of the output data is significantly shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram illustrating a write operation mode of the semiconductor memory device according to the embodiment.

FIG. 3 is a signal waveform diagram illustrating a read operation mode of the semiconductor memory device according to the embodiment.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

 101 Address Input Terminal 102 Address Input Buffer 103 Address Transition Detection Circuit 104 / WE (Read / Write Control) Input Terminal 105 / WE Input Buffer 106 Address Latch Control Circuit 107 Address Latch 108 Row Decoder 109 Column Decoder 110 Memory Array 111 Sense Amplifier 112 Data input / output / sense amplifier control circuit 113 Output buffer 114 Data output terminal 115 Data input terminal 116 Input buffer

Claims (1)

[Claims] 1. A plurality of memory cell array units for holding a data signal in a memory location corresponding to an applied address signal, and a write address signal continuously supplied in a write mode for each of the plurality of memory cell array units. An address control unit that sequentially supplies read address signals that are continuously supplied to each of the plurality of memory cell array units in the read mode, and a write that is continuously supplied in the write mode. Data is commonly given to each of the plurality of memory cell array units,
A semiconductor memory device comprising: a data input / output control unit that sequentially selects each data that is continuously read from each of the plurality of memory cell array units in the read mode.