CN113889157A - Storage device and continuous read-write method thereof - Google Patents
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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Abstract
The invention provides a storage device and a continuous reading and writing method thereof. When the memory device starts continuous reading operation or continuous writing operation, the controller provides a plurality of page starting addresses to the virtual static random access memory, and the virtual static random access memory carries out continuous reading operation or continuous writing operation according to the sequence of receiving the plurality of page starting addresses.
Description
Technical Field
The present invention relates to a storage device, and more particularly, to a storage device and a continuous read/write method thereof.
Background
Recently, narrow frequency IOT (NB-IOT), wearable devices, and mobile displays have demanded low pin count memory with high access throughput (throughput). However, existing low pin count storage (e.g., HyperRAM) does not support high speed throughput access. On the other hand, Synchronous Dynamic Random-Access Memory (SDRAM) supports a high-speed throughput function in a page mode and a bank interleave mode.
In the prior art, a Micro Controller Unit (MCU) issues a read transaction and a write transaction to a pseudo Static Random Access Memory (pseudo Static Random Access Memory). With respect to read transactions, read data is output on the DQ bus after a latency period defined in the register space (register space). With respect to write transactions, after a delay time, the write data will be transferred to the pseudo-static random access memory.
However, if the standby mode (standby mode) is not entered, the prior art cannot update the read address and the write address. This is because the DQ bus is occupied by data signals once reading or writing is started, and therefore no other addresses and commands can be input to the sram. This results in lower data transfer efficiency and access throughput.
Disclosure of Invention
The invention is directed to a memory device and a continuous read-write method thereof, which are used for providing a plurality of page starting addresses without entering a standby mode when continuous reading or continuous writing is started so as to improve the continuous access efficiency.
According to an embodiment of the present invention, a storage device includes a virtual static random access memory and a controller. A controller is coupled to the virtual static random access memory. When the memory device starts continuous reading operation or continuous writing operation, the controller provides a plurality of page starting addresses to the virtual static random access memory, and the virtual static random access memory carries out continuous reading operation or continuous writing operation according to the sequence of receiving the plurality of page starting addresses.
According to the embodiment of the invention, the continuous reading and writing method is suitable for the storage device, and the storage device comprises a virtual static random access memory and a controller. The continuous reading and writing method comprises the following steps: when the continuous reading operation or the continuous writing operation is started, a plurality of page starting addresses are provided, and the continuous reading operation or the continuous writing operation is carried out according to the sequence of receiving the plurality of page starting addresses.
Based on the above, in the embodiment of the invention, when the memory device and the continuous read/write method thereof start continuous reading or continuous writing, since the plurality of page start addresses are provided to the virtual static random access memory, the virtual static random access memory can enter the standby mode in a continuous read command cycle or a continuous write command cycle, as in the prior art. Therefore, the data occupancy rate of the DQ bus can be improved, and the continuous access efficiency can be improved.
Drawings
FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention;
FIG. 2 is a block diagram of a pseudo SRAM in accordance with one embodiment of the present invention;
FIG. 3 is a flow chart illustrating the determination of command bits according to an embodiment of the present invention;
FIG. 4 is a block diagram of an address latch decoding circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a page access sequence according to an embodiment of the present invention;
FIG. 6 is a flowchart of a continuous read/write method according to an embodiment of the invention.
Description of the reference numerals
10: storage device
110: virtual static random access memory
120: controller
210: input/output circuit
220: command decoder
230: address latch decoding circuit
240: memory array
410_0, 410_1, 410_ N: input indicator
420_0, 420_1, 420_ N: latch device
430_0, 430_1, 430_ N: output indicator
ECMD: external commands
EADD: external address
ERW: external read-write signal
BRW: continuous read-write signal
BADD: sequential addresses
AS: address space bit
P: page access bit
LIN _0, LIN _1, LIN _ N: latch input control signal
LOUT _0, LOUT _1, LOUT _ N: latch output control signal
ADDL0, ADDL1, ADDL N: latched address
CS: chip select signal
CA: command address
A0, A1, AN: page start address
S310, S320, S330, S340, S350, S610, S620: step (ii) of
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Referring to FIG. 1, the memory device 10 may include a virtual static random access memory 110 and a controller 120, wherein the controller 120 is coupled to the virtual static random access memory 11. The storage device 10 may be, for example, a Flash memory (Flash memory) or other memory.
In one embodiment, the pseudo SRAM 110 is composed of a Dynamic Random Access Memory (DRAM) as a core and a Static Random Access Memory (SRAM) as an interface.
The controller 120 may be, for example, a Central Processing Unit (CPU) or other similar components or combinations thereof, according to design requirements.
In one embodiment, when the memory device 10 starts a continuous read operation (burst read operation) or a continuous write operation (burst write operation), the controller 120 may provide a plurality of page starting addresses (page starting addresses) to the sram 110. The pseudo sram 110 receives a plurality of page start addresses, and the pseudo sram 110 performs a sequential read operation or a sequential write operation according to an order of receiving the plurality of page start addresses. Specifically, the page start address is a start address used to read or write a page consecutive address of the memory array in the vsram 110. The continuous reading operation is used for continuously reading a continuous address range in the memory according to the page starting address, and the continuous writing operation is used for continuously writing the writing data into the continuous address range in the memory according to the page starting address.
For example, when the memory device 10 starts a continuous read operation or a continuous write operation, the controller 120 may provide the page start addresses A0-AN to the pseudo SRAM 110. The PSRAM 110 receives the page start addresses A0 AN in sequence, and the PSRAM 110 performs a sequential read operation or a sequential write operation according to the sequence of receiving the page start addresses A0 AN. That is, a continuous read operation or a continuous write operation is performed on the page start address a0, a continuous read operation or a continuous write operation is performed on the page start address a1, and so on until a continuous read operation or a continuous write operation is performed on the page start address AN. The number of N is determined by design requirements.
Referring to fig. 2, the pseudo sram 110 includes an input/output circuit 210, a command decoder 220, an address latch decoding circuit 230, and a memory array 240. In one embodiment, the pseudo SRAM 110 may further include other circuits, such as a data path circuit (data path circuit).
The input/output circuit 210 may be a conventional input/output circuit (IO circuit) or other interface circuit, and in one embodiment, the input/output circuit 210 is coupled to the controller 120, and the input/output circuit 210 is configured to receive the external command ECMD and the external address EADD from the controller 120, provide the external command ECMD to the command decoder 220, and provide the external address EADD to the address latch decoding circuit 230. The external address EADD includes the page start address A0-AN.
The command decoder 220 is coupled to the input/output circuit 210, and the command decoder 220 is used for receiving the external command ECMD and decoding the external command ECMD to provide the external read/write signal ERW and the continuous read/write signal BRW to the address latch decoding circuit 230. In one embodiment, the command decoder 220 may be an existing command decoder or other decoding circuitry.
The address latch decoding circuit 230 is coupled to the input/output circuit 210 and the command decoder 220, the address latch decoding circuit 230 is configured to receive AN external address EADD from the input/output circuit 210 and AN external read/write signal ERW and a continuous read/write signal BRW from the command decoder 220, and sequentially latch the page start addresses a 0-AN in the external address EADD according to the external read/write signal ERW and the continuous read/write signal BRW to provide the continuous addresses BADD to the memory array 240, and sequentially perform a continuous read operation or a continuous write operation on the memory array 240 according to the page start addresses a 0-AN in the continuous addresses BADD. The number of N is determined by design requirements.
The memory array 240 is coupled to the command decoder 220 and the address latch decoding circuit 230, and the memory array 240 receives the consecutive addresses BADD to sequentially perform a consecutive read operation or a consecutive write operation according to the page start addresses A0-AN in the consecutive addresses BADD. In one embodiment, the memory array 240 may include conventional sense amplifiers, X decoders, Y decoders, and memory cell arrays, but is not limited thereto.
Referring to fig. 1, 2 and 3, the controller 120 is further configured to provide external commands ECMD to the virtual static random access memory 110. The external command ECMD comprises a command address CA comprising address space bits AS and page access bits P. In an embodiment, the command address CA may further include a read or write bit (read or write bit), a burst type bit (burst type bit), and the like, which is not limited thereto.
Referring to fig. 3, in step S310, the memory device 10 starts a continuous read operation or a continuous write operation. Next, in step S320, the memory device 10 determines whether the sequential read operation or the sequential write operation is a register access or a storage array access according to the value of the address space bit AS in the command address CA. When the value of the address space bit AS is 1, the process proceeds to step S330. When the value of the address space bit AS is 0, the process proceeds to step S340. In step S330, the virtual static random access memory 10 performs register access (register access), that is, accesses to a register (not shown) in the storage device 10. In step S340, the vsram 110 further determines whether the memory array access is a page access (page access) according to the page access bit P in the command address CA. When the value of the page access bit P is 1, the SRAM 110 receives the next page start address A1 after receiving the page access address A0, and the step S340 is performed again. This operation is repeated to obtain the required page address and the value of the page access bit P is set to 0 when the last received page address AN is received. When the value of the page access bit P is 0, the process proceeds to step S350. Next, in step S350, the sram 110 performs a memory array access (memory array access), i.e., accesses the memory array 240 in the sram 110.
In other words, when the storage device 10 starts a continuous read operation or a continuous write operation, the storage device 10 determines whether to perform the continuous read operation or the continuous write operation in the storage array of the vsram 110 according to the value of the address space bit AS and the value of the page access bit P.
When the consecutive read operation or the consecutive write operation is determined to be the access of the memory array according to the value of the address space bit AS in the command address CA (i.e., AS in the command address CA of fig. 5 is 0), and the access of the memory array is determined to be the page access according to the value of the page access bit P in the command address CA (i.e., P in the command address CA of fig. 5 is 1), the sram 110 sequentially performs the consecutive read operation or the consecutive write operation according to the page start addresses a 0-AN.
When the consecutive read operation or the consecutive write operation is determined to be a register access according to the value of the address space AS in the command address CA, that is, when the address space AS is equal to 1, the sram 110 performs the register access. When it is determined that the continuous read operation or the continuous write operation is the memory array access according to the value of the address space bit AS in the command address CA, that is, the address space bit AS is equal to 0, the sram 110 determines whether the memory array access is the page access according to the page access bit P in the command address CA. When the memory array access is determined to be a page access according to the value of the page access bit P in the command address CA, i.e., the page access bit P is equal to 1, the sram 110 sequentially receives the page start addresses a 0-AN. When the page start address AN is received, the page access bit P is 0, and the sram 110 performs the memory array access.
Referring to FIG. 4, the address latch decoding circuit 230 includes input indicators 410_0 to 410_ N, latches 420_0 to 420_ N, and output indicators 430_0 to 430_ N.
The input indicators 410_ 0-410 _ N are coupled in series. Specifically, input indicator 410_1 is coupled to input indicator 410_0, and so on until coupled to input indicator 410_ N. The input pointer 410_0 receives the external read and write signal ERW from the command decoder 220.
The latches 420_0 to 420_ N are coupled to the input indicators 430_0 to 430_ N, respectively. Specifically, the latch 420_0 is coupled to the input indicator 410_0, the latch 420_1 is coupled to the input indicator 410_1, and so on, and the latch 420_ N is coupled to the input indicator 410_ N. The latches 420_ 0-420 _ N receive external addresses EADD from the input-output circuit 210, wherein the external addresses EADD include page start addresses A0-AN.
The output indicators 430_ 0-430 _ N are coupled in series. Specifically, output indicator 430_1 is coupled to output indicator 430_0, and so on until coupled to output indicator 430_ N. The output indicators 430_0 to 430_ N are respectively coupled to the latches 420_0 to 420_ N, wherein the output indicator 430_0 is coupled to the latch 420_0, the output indicator 430_1 is coupled to the latch 420_1, and so on, the output indicator 430_ N is coupled to the latch 420_ N. The output indicators 430_ 0-430 _ N receive the continuous read/write signal BRW from the command decoder 220.
In one embodiment, the input indicators 410_ 0-410 _ N generate latch input control signals LIN _ 0-LIN _ N according to the external read/write signal ERW, and the latch input control signals LIN _ 0-LIN _ N are used for sequentially latching (latching) the page start addresses A0-AN in the external address EADD to the latches 420_ 0-420 _ N. The output indicators 430_ 0-430 _ N generate latch output control signals LOUT _ 0-LOUT _ N according to the continuous read/write signal BRW, the latch output control signals LOUT _ 0-LOUT _ N are used for enabling the latches 420_ 0-420 _ N to sequentially output the page start addresses A0-AN in the latched external address EADD as a latched address ADDL0, a latched address ADDL1 … as a latched address ADDLN, and output as a continuous address BADD to sequentially output the page start addresses A0-AN to the memory array 240.
In one embodiment, the latches 420_ 0-420 _ N are used for latching the external address EADD to output the consecutive address BADD according to the latch input control signals LIN _ 0-LIN _ N and the latch output control signals LOUT _ 0-LOUT _ N, wherein the consecutive address BDD is used for sequentially and consecutively providing the page start addresses A0-AN in the external address EADD to the memory array 240 for performing a consecutive read operation or a consecutive write operation.
In detail, referring to fig. 4 and 5, the chip select signal/CS is used to select the chip to be read/written. In this embodiment, when the chip select signal/CS transitions to a low logic level, the memory device 10 begins a continuous read operation or a continuous write operation on the chip selected by the chip select signal/CS. When the consecutive read operation or the consecutive write operation is started, whether the consecutive read operation or the consecutive write operation is performed in the storage array 240 in the vsram 110 is determined according to the value of the address space bit AS and the value of the page access bit P in the command address CA. When the address space bit AS is 0 and the page access bit P is 1, the PSRAM 110 receives the page start addresses A0-AN in the external address EADD. The input indicators 410_ 0-410 _ N generate latch input control signals LIN _ 0-LIN _ N according to the external read/write signal ERW, and the latch input control signals LIN _ 0-LIN _ N are used for sequentially latching the page start addresses A0-AN in the external address EADD to the latches 420_ 0-420 _ N. The output indicators 430_ 0-430 _ N generate latch output control signals LOUT _ 0-LOUT _ N according to the continuous read/write signal BRW, the latch output control signals LOUT _ 0-LOUT _ N are used for enabling the latches 420_ 0-420 _ N to output the page start addresses A0-AN in the latched external address EADD as the latched address ADDL0, the latched address ADDL1 … as the latched address ADDLN, and output the latched address ADDL0, the latched address ADDL1 … as the continuous address BADD to sequentially output the page start addresses A0-AN to the memory array 240. The consecutive address BADD sequentially and consecutively provides the page start addresses A0-AN in the external address EADD to the memory array 240. It should be noted that the plural hatching in fig. 5 indicates an undetermined state (Don't Care).
Referring to FIG. 6, in step S610, when the memory device starts a continuous read operation or a continuous write operation, the controller provides a plurality of page start addresses to the pseudo SRAM. Then, in step S620, the vsram performs a continuous read operation or a continuous write operation according to the sequence of receiving the plurality of page start addresses.
In summary, in the embodiments of the invention, the memory device and the continuous read/write method thereof provide a plurality of page start addresses to the virtual static random access memory when starting continuous read or continuous write, so that the virtual static random access memory can access the plurality of page start addresses in a continuous read command cycle or a continuous write command cycle, thereby improving continuous access efficiency, improving data transmission efficiency and access throughput, and improving system performance.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (14)
1. A memory device, comprising:
a virtual static random access memory; and
a controller coupled to the pseudo SRAM,
when the memory device starts continuous reading operation or continuous writing operation, the controller provides a plurality of page starting addresses to the virtual static random access memory, and the virtual static random access memory carries out the continuous reading operation or the continuous writing operation according to the sequence of receiving the plurality of page starting addresses.
2. The storage device of claim 1, wherein the controller is further configured to provide an external command to the virtual static random access memory, wherein the external command includes a command address,
wherein when the storage device starts the continuous read operation or the continuous write operation, determining whether to perform the continuous read operation or the continuous write operation in a storage array in the pseudo SRAM according to a value of an address space bit in the command address and a value of a page access bit.
3. The memory device according to claim 2, wherein when the consecutive read operation or the consecutive write operation is determined to be the memory array access according to a value of an address space bit in the command address, and the memory array access is determined to be a page access according to a value of a page access bit in the command address, the pseudo sram performs the consecutive read operation or the consecutive write operation according to an order in which the plurality of page start addresses are received.
4. The storage device of claim 2, wherein
When the continuous reading operation or the continuous writing operation is judged to be register access according to the value of the address space bit in the command address, the virtual static random access memory performs the register access;
when the continuous reading operation or the continuous writing operation is judged to be accessed to the memory array according to the value of the address space bit in the command address, the virtual static random access memory judges whether the memory array access is page access or not according to the page access bit in the command address;
when the memory array access is judged to be the page access according to the value of a page access bit in a command address, the virtual static random access memory carries out the page access according to the plurality of page starting addresses in sequence; and
and when the plurality of page starting addresses are all used for the page access, the virtual static random access memory performs the storage array access.
5. The storage device of claim 1, wherein the virtual static random access memory comprises:
an input-output circuit coupled to the controller and configured to receive an external command and an external address from the controller;
a command decoder coupled to the input-output circuit and configured to receive an external command from the input-output circuit, decode the external command to provide an external read-write signal and a continuous read-write signal;
an address latch decoding circuit, coupled to the input/output circuit and the command decoder, configured to receive the external address from the input/output circuit and the external read/write signal and the continuous read/write signal from the command decoder, and latch the plurality of page start addresses in the external address in sequence according to the external read/write signal and the continuous read/write signal to output a continuous address to a memory array, and perform a continuous read operation or a continuous write operation on the memory array in sequence according to the continuous address; and
a memory array coupled to the command decoder and the address latch decoding circuit and configured to receive the consecutive addresses and sequentially perform the consecutive read operations or the consecutive write operations according to the consecutive addresses.
6. The memory device according to claim 5, wherein the address latch decoding circuit comprises:
a plurality of input indicators coupled in series configured to receive the external read and write signals from the command decoder;
a plurality of latches respectively coupled to the plurality of input indicators and configured to receive an external address from the input output circuit, wherein the external address includes the plurality of page start addresses; and
a plurality of output indicators coupled in series, respectively coupled to the plurality of latches, configured to receive the continuous read and write signals from the command decoder,
wherein the plurality of input indicators are configured to generate a plurality of latch input control signals for sequentially latching a plurality of page start addresses among the external addresses to the plurality of latches according to the external read/write signal, and the plurality of output indicators are configured to generate a plurality of latch output control signals for causing the latches to sequentially output a plurality of page start addresses among the latched external addresses as the continuous addresses according to the continuous read/write signal.
7. The memory device according to claim 6, wherein the plurality of latches are configured to latch the external address according to the plurality of latch input control signals and the plurality of latch output control signals to output consecutive addresses, wherein the consecutive addresses are configured to sequentially and consecutively provide a plurality of page start addresses of the external address to the memory array.
8. A continuous read-write method is suitable for a storage device, the storage device comprises a virtual static random access memory and a controller, and the continuous read-write method comprises the following steps:
when a continuous read operation or a continuous write operation is started, a plurality of page start addresses are provided, and the continuous read operation or the continuous write operation is performed according to the sequence of receiving the plurality of page start addresses.
9. The continuous read-write method of claim 8, wherein the controller is further configured to provide an external command to the virtual static random access memory, wherein the external command includes a command address,
wherein when the continuous read operation or the continuous write operation is started, determining whether to perform the continuous read operation or the continuous write operation in a storage array in the pseudo static random access memory according to a value of an address space bit and a value of a page access bit in the command address.
10. The method of claim 9, wherein when the sequential read operation or the sequential write operation is determined to be the memory array access according to a value of an address space bit in the command address, and the memory array access is determined to be a page access according to a value of a page access bit in the command address, the sequential read operation or the sequential write operation is performed according to an order in which the plurality of page start addresses are received.
11. Method for continuous reading and writing according to claim 9, wherein
When the continuous reading operation or the continuous writing operation is judged to be register access according to the value of the address space bit in the command address, the register access is carried out;
when the continuous reading operation or the continuous writing operation is judged to be accessed to the storage array according to the value of the address space bit in the command address, judging whether the access to the storage array is page access or not according to the value of the page access bit in the command address;
receiving the plurality of page starting addresses when the memory array access is judged to be the page access according to the value of a page access bit in the command address; and
and when the plurality of page starting addresses are received, the memory array is accessed.
12. The continuous read-write method of claim 8, wherein the pseudo SRAM comprises an input-output circuit, a command decoder, an address latch decoding circuit, and a memory array, wherein,
receiving an external command and an external address from the controller through the input-output circuit;
receiving an external command from the input-output circuit through the command decoder to decode the external command to provide an external read-write signal and a continuous read-write signal;
receiving the external address from the input/output circuit and the external read-write signal and the continuous read-write signal from the command decoder through the address latch decoding circuit, latching the plurality of page starting addresses in the external address in sequence according to the external read-write signal and the continuous read-write signal to output continuous addresses to a storage array, and performing continuous read operation or continuous write operation on the storage array in sequence according to the continuous addresses; and
receiving the continuous addresses through the storage array, and sequentially performing the continuous reading operation or the continuous writing operation according to the continuous addresses.
13. The continuous read-write method of claim 12, wherein the address latch decoding circuit comprises a plurality of input indicators, a plurality of latches, and a plurality of output indicators coupled in series, wherein
Receiving the external read and write signals from the command decoder through the plurality of input pointers;
receiving an external address from the input-output circuit through the plurality of latches;
receiving the continuous read and write signals from the command decoder through the plurality of output indicators;
generating a latch control signal for sequentially latching a plurality of addresses in the external addresses to the latch according to the external read-write signals through the plurality of input indicators; and
generating, by the plurality of output indicators, an output control signal for causing the latch to sequentially output a plurality of the latched external addresses as the consecutive external addresses according to the consecutive read and write signals.
14. The continuous read-write method of claim 13, wherein the external addresses are latched by the latches according to the latch input control signals and the latch output control signals to output continuous addresses, wherein the continuous addresses are configured to sequentially and continuously provide a plurality of addresses of the external addresses.
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