JP4819325B2 - Integrated circuit device and operation method thereof - Google Patents

Description

  The present invention relates to an integrated circuit device and an operation method thereof, for example, a write data path of an integrated circuit memory device and an operation method thereof.

  Integrated circuit memory devices are widely used in many consumer and commercial applications. As the degree of integration of an integrated circuit memory device increases, the number of memory cells in the integrated circuit memory device also increases. In addition, the prefetch scheme of integrated circuit memory devices is further increased. As is well known to those skilled in the art, prefetch means how many bits can be written or read simultaneously in an integrated circuit memory device. The prefetch scheme is also expressed in burst length, which means the number of bits output or input serially to / from an external terminal at a time. Many integrated circuit devices use a 4-bit prefetch scheme, for example, a 4-bit burst length. However, increasing to an 8-bit burst length or 8-bit prefetch scheme is required for high data rates. In the future, higher prefetch schemes and burst lengths will be used.

  As the number of high prefetch schemes increases, the size and complexity of the write data path of an integrated circuit memory device increases. As is well known to those skilled in the art, a write data path is provided for receiving multiple data bits in series from an external terminal and writing multiple data bits to the memory cell array in parallel. As a result, the data write path occupies a considerable portion of the chip area.

  FIG. 1 is a block diagram of a typical DRAM. The DRAM of FIG. 1 is also referred to as a fast cycle DRAM (FCDRAM). Referring to this, the FCRAM 100 receives a clock signal to generate an internal clock signal, a command decoder 104 to generate an instruction according to an external input, address data A0 to A14, and bank selection signals BA0 and BA1. Therefore, an address buffer 106 for generating an address signal and a refresh counter 108 are included. The control signal generator 110 generates a control signal according to the signal provided from the command decoder 104. The mode register MRS 112 generates an appropriate mode signal. The upper address latch 114 and the lower address latch 116 generate address signals provided to the row decoder and the column decoder, respectively. The burst counter 118 is used to control the burst length of read and write data. The write address latch / comparator 120 is used to compare the previous write address with the current write address.

  As the memory cell array, for example, four banks 122 to 128 are provided. However, fewer or more banks may be provided. The input / output data path 200 includes a data control and latch circuit 130, a read data buffer 132, a write data buffer 134, and an input / output DQ buffer 136. The DQ buffer 136 is responsive to a data mask signal DM that masks a predetermined input. Since the FCDRAM described in FIG. 1 is a technique well known to those skilled in the art, further description is omitted.

  FIG. 2 is a more specific block diagram of the data input / output path 200 of FIG. As shown in FIG. 2, when the mode register 112 of FIG. 1 selects the burst length 4, each of the input / output terminals DQ0 to DQ15 sequentially receives 4 data bits transmitted from the external terminal. Thereafter, each input data bit is transmitted to the serial-parallel (SP) conversion unit 30 by the data input buffer 38 in the DQ buffer 136. Input data on the write data bus DBW converted from serial to parallel by the serial-parallel SP converter 30 is sent to the appropriate write data paths 31, 32, 33, 34 selected by the bank address bits BA0, BA1. Reportedly.

  Referring to FIG. 2, the reading of data will be described. Data is output from any one of a number of banks BANK0 to BANK3, and read data paths 41, 42, 43, and 44 selected by bank address bits BA0 and BA1. To the read data bus line DBR. The parallel data on the read data bus line DBR is converted into serial data by the parallel-serial converter 40. Thereafter, the serial data is output to the outside through the data output buffer 48 and the data input / output terminals DQ0 to DQ15. Therefore, 64 (4 × 16) bits of input data are simultaneously written into the memory cell array of the selected bank through data input / output terminals DQ0 to DQ15, and a 64-bit date is simultaneously read.

  FIG. 3 is a block diagram illustrating a 4-bit prefetch scheme in a conventional FCDRAM connected to FIGS. Referring to FIG. 3, when the burst length 4 is selected by the MRS 112 of FIG. 1, the first input data bit buffered through the input buffer 38 is responsive to the rising edge of the first internal data strobe signal PDS. The data is stored in the first latch 311 of the input data latch 301 of the serial-parallel converter 30. The second input data bits received in series are stored in the second latch 312 of the input data latch 301 of the serial-parallel converter 30 in response to the falling edge of the first internal data strobe signal PDS.

  At this time, the first input data bit stored in the first latch 311 and the second input data bit stored in the second latch 312 are the first of the parallel conversion unit 302 in response to the second internal data strobe signal PDSP. This is transmitted to the register 313 and the second register 314, respectively. The third input data bit is stored in the first latch 311 in response to the next rising edge of the first internal data strobe signal PDS, and the fourth input data bit is the next falling edge of the first internal data strobe signal PDS. Stored in the second latch 312 in response to the edge.

  The third input data bit and the fourth input data bit are respectively sent to the third register 315 and the fourth register 316 of the parallel conversion unit 302 in response to the rising and falling edges of the first internal data strobe signal PDS. Reportedly. Therefore, as shown in FIG. 3, the odd input data DIN-O such as the first and third input data bits is continuously transmitted to the first and third registers 313 and 315, and the second and second inputs. Even input data DIN-E such as 4 input data bits is transmitted to the second and fourth registers 314 and 316. After all input dates D0, D1, D2, and D3 are transmitted to the parallel conversion unit 302, all input data is transmitted to the parallel data output circuit 303 in parallel in response to the third internal data strobe signal PDSEN. Saved.

  FIG. 4 is a timing diagram illustrating the above-described operation including serial input of four data bits D0-D3 on the input DQ pad and parallel output of four data bits on data lines DBW_0-DBW_3.

  Referring to FIG. 3, the input data stored in the serial-parallel converter 30 is written data buffers 330, 331, 332, which form portions of the write data paths 31, 32, 33, 34 of FIG. 333 is stored. Input data is transmitted from the write data buffers 330, 331, 332, and 333 to the column selection lines CSL and 350 in response to a control signal PS4 applied to the parallel bit switches PSW and 340 to 343. The 4-bit input date is written into the memory cell block 360 at the same time. 3 and 4, since 4-bit data is simultaneously written into the memory cell block, a 4-bit prefetch scheme will be described. In FIG. 3, lines connecting the write data buffers 330 to 333 and the parallel bit switches PSWs 340 to 343 are referred to as global data lines GDL_0 to GDL_3. Lines connecting the parallel bit switch PSW and the column selection line CSL are referred to as local data lines LDL_0 to LDL_3. Finally, the bit lines of the memory cell array are denoted as BL_0-BL_511 in FIG.

  FIG. 5 is a block diagram of a conventional FCDRAM including an 8-bit prefetch scheme. As is well known to those skilled in the art, in an 8-bit prefetch scheme, the FCDRAM operates at a higher data rate. In FIG. 5, the same reference numerals as those in FIG. 3 indicate the same components. In order to conform to the 8-bit prefetch scheme, the number of components in FIG. 3 is doubled in FIG. Accordingly, the second set of registers 313 ′ to 316 ′ is provided to the parallel converter 302, and the second set of registers 317 ′ to 320 ′ is provided to the parallel data output circuit 303. A second set of write data buffers 334-337 and parallel bit switches 344-347 are also provided.

  As shown in FIG. 5, the local data line LDL and the global data line GDL are doubled as compared with FIG. In other words, in the 8-bit prefetch scheme of FIG. 5, the number of global data lines GDL and local data lines LDL increases twice as compared with the 4-bit prefetch scheme of FIG. More specifically, in FIG. 5, eight global data lines GDL_0 to GDL_7 are used to connect the respective write data buffers 330 to 337 to the respective parallel bit switches 340 to 347. The eight local data lines LDL_0 to LDL_7 are used to connect the respective parallel bit switches 340 to 347 to the column selection line 350. As a result, a large number of local and / or global data lines occupy too much area of the integrated circuit memory device.

Read and / or write data paths in other high-speed memory devices are disclosed in Patent Document 1 (“Semiconductor Memory Device” by Suzuki et al.) And Patent Document 2 (“Seigo et al.” “Clock data for high-speed data read and data write operations”. Semiconductor memory devices that operate in synchronism ”) and in US Pat. No. 6,057,059 (“ Fast cycle RAM with improved data write operation ”by Ochuma et al.).
US Pat. No. 6,144,616 US Pat. No. 6,427,197 US Patent Application No. 2001/0005012

  An object of the present invention is to provide a memory device that implements a 2n-bit prefetch scheme using an n-bit prefetch structure.

  Another object of the present invention is to provide a memory device that adjusts an automatic precharge time according to a change in burst length.

  It is still another object of the present invention to provide a method for implementing a 2n-bit prefetch scheme using a memory device having an n-bit prefetch structure.

  Still another object of the present invention is to provide an automatic precharge control method by changing a burst length.

  An integrated circuit memory device according to one aspect of the present invention includes a memory cell array that writes N data bits in parallel and a write data path that receives 2N data bits in series from an external terminal. The write data path includes 2N write data buffers storing 2N data bits, 2N switches, and at least N of 2N switches for writing N data bits to the memory cell array in parallel. And N data lines connecting the memory cell arrays. This reduces the number of local data lines and global data lines.

  In an embodiment of the present invention, the write data path includes first and second serial-parallel converters connected to an external terminal, N first global data lines and N second global data lines. including. In an embodiment of the present invention, the first serial-parallel converter is responsive to the first internal data strobe signal, and the second serial-parallel converter is responsive to the second internal data strobe signal. In other embodiments, the first and second serial-to-parallel converters are responsive to the same internal data strobe signal. The 2N write data buffers are composed of N first write data buffers and N second write data buffers, and 2N switches include N first switches and N second switches. Composed. In these embodiments, the N first write data buffers are coupled to the first serial-parallel converter, and each of the N first global data lines includes each of the N first switches and the N number of first switches. Each of the first write data buffers is connected to each other. In these embodiments, the N second write data buffers are coupled to the second serial-parallel converter, and each of the N second global data lines includes each of the N second switches and the N number of the second switches. It is connected between each of the second write data buffers. In these embodiments, the N data lines are N local data lines, and each of the N local data lines includes N first switches and N second switches and a memory cell array. Each is connected in between.

  In these embodiments, the write data path is any one of the first and second serial-parallel converters and any one of the N first write data buffers and the N second write data buffers. First and second data ordering circuits connected between the first and second data ordering circuits, respectively. Further, in these embodiments, the N first switches are responsive to a first control signal, and the N second switches are responsive to a second control signal delayed from the first control signal. The first and second control signals may be generated with a different delay time from the write activation signal.

  The embodiments further include a command decoder that generates a write activation signal in response to a chip selection command and a function command, and a control signal generator that generates first and second control signals in response to the write activation signal. Including. The instruction decoder further generates an active instruction and a read instruction in response to the chip selection instruction and the function instruction, and the instruction decoder further receives a read instruction, a refresh instruction, and a mode register instruction in response to the chip selection instruction and the function instruction. Can be generated.

  These embodiments further include N third switches and N fourth switches. Each of the N third switches is connected between the first serial-parallel converter and each of the N first write data buffers, and each of the N fourth switches includes a second serial-parallel converter. And each of the N second write data buffers. In an embodiment, the N third switches are responsive to a third control signal, and the N fourth switches are responsive to a fourth control signal delayed from the third control signal. The third and fourth control signals are generated in response to the offset falling edge of the data strobe signal. Finally, the data strobe counter may count the falling edge of the data strobe signal in response to the data strobe signal and generate the third and fourth control signals from the offset falling edge of the data strobe signal.

  In another embodiment of the present invention, the write data path includes a serial-parallel converter connected to an external terminal and N global data lines. In these embodiments, the 2N write data buffers are composed of N first write data buffers and N second data buffers, and the 2N switches include N first switches and N second data buffers. The second switch. The N first write data buffers are connected to the first serial-parallel converter, and each of the N first write data buffers is connected to the N first switches. Each of the N second write data buffers is connected to each of the N first switches, and each of the N global data lines is connected to each of the N second switches and the N second write. It is connected between each of the data buffers. Finally, each of the N local data lines is connected between the N second switches and the memory cell array.

  In these other embodiments, the write data path further includes a data ordering circuit coupled between the serial-parallel converter and the N first write data buffers. In addition, these embodiments further include N third switches connected between the serial-parallel converter and each of the N first write data buffers. Further, the N third switches are responsive to a first control signal, and the N first switches are responsive to a second control signal delayed from the first control signal. The first and second control signals may be generated in response to the offset falling edge of the data strobe signal.

  Yet another embodiment of the present invention includes a precharge control circuit that enables a word line of a memory cell array at a time sufficient to store 2N data bits, which are two groups of N parallel bits, in the memory cell array. In these embodiments, the precharge control circuit has a sufficient time to store 2N data bits, which are two groups of N parallel bits, in the memory cell array during the first precharge mode of the integrated circuit device. Enable the word line of the memory cell array. The precharge control circuit sets the word line of the memory cell array for a time sufficient to write N data bits, which are a group of N parallel bits, to the memory cell array during the second precharge mode of the integrated circuit device. Activate. The mode register is set to select the first or second precharge mode, and the precharge control circuit responds to the mode register.

  In these embodiments, the precharge control circuit includes first and second delay units. The first delay unit activates the word line of the memory cell array in response to the first precharge mode for a time sufficient to store 2N data bits, which are two groups of N parallel bits, in the memory cell array. Let The second delay unit is responsive to the second precharge mode and activates the word line of the memory cell array for a time sufficient to write N data bits of the N parallel bits of the first group to the memory cell array. .

  According to another embodiment of the present invention, at least one of the write data buffers includes an address latch that latches a write address, an address comparison unit that compares the write address latched in the address latch with a current address, A data latch for latching write data corresponding to the write address is included. In these embodiments, when the current address is a read address and the address comparison unit determines that the read address and the write address latched in the address latch match, the external address is not from the memory cell array but from the data latch. Outputs read data to the terminal. In another embodiment, the integrated circuit memory device provides a memory cell array when the current address is a read address and the address comparator determines that the read address and the write address latched in the address latch do not match. Read data to the external terminal.

  Accordingly, an integrated circuit memory device according to various embodiments of the present invention includes a memory cell array that writes a number of data bits in parallel. The write data path receives a number of data bits from the external terminal twice in series, writes the first half of the data bits to the memory cell array in parallel, and writes the last second half of the data bits to the memory cell array in parallel.

  An integrated circuit device having a memory cell array for storing a large number of data bits in parallel according to an embodiment of the present invention operates while receiving a plurality of data bits from an external terminal twice in series. The received data bits are stored in a plurality of write data buffers. The first half (first half) of the plurality of data bits is written in parallel from the write data buffer to the memory cell array. Thereafter, the remaining half (second half) of the plurality of data bits is written in parallel from the write data buffer to the memory cell array.

  In these embodiments, in receiving data bits twice, the first half (first half) of the plurality of data bits is received in series and then the remaining half (second half) of the plurality of data bits. Are received in series. After the first half (first half) of the plurality of data bits is stored in the first set of write data buffers, the remaining half (second half) of the plurality of data bits is the second of the write data buffer. Saved in a set. Finally, the first half (first half) and the remaining half (second half) of each of the plurality of data bits from each of the first and second sets of write data buffers are shared through the local data line. Is written to.

  According to another embodiment of the present invention, a first half (first half) of the plurality of data bits is received in series, and then the remaining half (second half) of the plurality of data bits is serially received. Received. The first half (first half) of the plurality of data bits is stored in the first write data buffer, and the first half (first half) of the plurality of data bits of the first write data buffer is the second write data. Shifted to the buffer, the remaining half (second half) of the plurality of data bits is stored in the first write data buffer. The first half (first half) of the plurality of bit data is written from the second write data buffer to the memory cell array. The remaining half (second half) of the plurality of data bits of the first write data buffer is shifted to the second write data buffer, and the remaining half of the plurality of data bits (second half) from the second write data buffer. Are written into the memory cell array.

  In addition, according to the embodiment of the present invention, without increasing the number of global data lines and local data lines, for example, by implementing an 8-bit prefetch scheme with a 4-bit prefetch structure, without increasing the chip size. An integrated circuit memory device capable of ultra-high speed operation can be provided.

  Also, according to the embodiment of the present invention, for example, in a memory device having a 4-bit prefetch structure, the bit line automatic precharge time is adjusted according to the burst length, and for example, data corresponding to a burst length of 8 Therefore, an integrated circuit memory device with an extended word line enable time can be provided.

  According to the present invention, a 2n-bit prefetch scheme can be implemented using an n-bit prefetch structure.

  Alternatively, according to the present invention, the automatic precharge time can be adjusted by changing the burst length.

  Alternatively, according to the present invention, a 2n-bit prefetch scheme can be implemented using a memory device having an n-bit prefetch structure.

  Alternatively, according to the present invention, it is possible to provide an automatic precharge control method by changing the burst length.

  For a full understanding of the invention and its operational advantages and objects achieved by the practice of the invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the invention and the contents described in the accompanying drawings. is there.

  Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the drawings. The same reference numbers provided in each drawing indicate similar components.

  FIG. 6 is a block diagram of an integrated circuit memory device according to one embodiment of the present invention. As shown in FIG. 6, the integrated circuit memory device 400 includes a memory cell array 410 into which N data bits are written in parallel. Write data path 420 receives 2N data bits in series on serial line 428 from external terminal 426. As shown in FIG. 6, the write data path 420 is comprised of 2N write data buffers 422 and 2N switches 424 for storing 2N data bits received on the serial line 428. The N data lines 412 also connect at least N of the 2N switches 424 to the memory cell array 410 to write N data bits in parallel to the memory cell array 410.

  FIG. 6 illustrates one embodiment of the present invention embodied as an integrated circuit memory device 400 that includes a memory cell array 410 for storing multiple data bits in parallel. The write data path 420 receives 2N data bits from the external terminal 426 in parallel, and the first group (the first half or the first half) of one of the 2N data bits divided into two. Half of 1) is stored in parallel in the memory cell array 410, and the remaining second group (the remaining half or the second half) of the 2N data bits divided into two is divided into two. The data is stored in the memory cell array 410 in parallel. FIG. 6 illustrates a method of operating the integrated circuit memory device 400 of one embodiment of the present invention. This method of operation receives 2N data bits from the external terminal 426 in series, stores them in 2N write data buffers 422, and divides 2N data bits from the write data buffer 422 into N pieces each. The first group is stored in the memory cell array 410 in parallel, and then the remaining second group of the two data bits divided into two from the write data buffer 422 is stored in the memory cell array 410 in parallel. save.

  7 and 8 are block diagrams of the write data path of the embodiment of the present invention. The embodiment shown in FIG. 7 is a first embodiment of the present invention, and will be specifically described in conjunction with FIGS. 9 to 12. The embodiment shown in FIG. 8 is a second embodiment of the present invention and will be specifically described in connection with FIGS.

  Referring to FIG. 7, the write data path 420 ′ includes first and second serial-parallel converters 430 a and 430 b connected to the external terminal 426 through a serial line 428. The write data path 420 'is further provided with N first global data lines 434a and N second global data lines 434b. The 2N write data buffers 422 in FIG. 6 are configured by N first write data buffers 432a and N second write data buffers 432b. Further, the 2N switches 424 in FIG. 6 are configured by N first switches 436a and N second switches 436b. As shown in FIG. 7, the N first write data buffers 432a are connected to the first serial-parallel converter 430a, and each of the N first global data lines includes N first One switch 436a is connected to each of the N first write data buffers 432a. Similarly, as shown in FIG. 7, N write data buffers 432b are connected to the second serial-parallel converter 430b, and each of the N second global data lines is N The second switches 436b are connected to the N second write data buffers 432b. Finally, in FIG. 7, the N data lines in FIG. 6 are N local data lines 438. Each of the N local data lines 438 is coupled between each of the N first switches 436a and N second switches 436b and the array 410 of memory cells.

  Of the 2N data bits received in series through the external terminal 426, a first group of N divided into two is stored in the first serial-parallel conversion unit 430a, and 2N received in series through the external terminal 426. The remaining second group of the N data bits divided into two is received by the second serial-parallel converter 430b. N first groups of 2N data bits are stored in the first write data buffer 432a, and the remaining N second groups of 2N data bits are stored in the second write data buffer 432b. Saved in. N first groups of the 2N data bits are transferred from the first write data buffer 432a to the memory cell array 410, and the remaining N second groups of the 2N data bits are the second ones. Data is written from the write data buffer 432b to the memory cell array 410 through the local data line 438.

  FIG. 8 is a block diagram of the write data path of the second embodiment of the present invention. As shown in FIG. 8, the write data path 420 ″ includes a serial-parallel converter 440 connected to the external terminal 426. The write data path 420 '' is also provided with N first write data buffers 442a, N second write data buffers 442b, and N first switches 446a and N second switches 446b. . The N first write data buffers 442a are connected to the serial-parallel converter 440, and each of the N write data buffers 442a is connected to each of the N first switches 446a. Further, the N second write data buffers 442b are connected to the N second switches 446b, respectively. Each of the N global data lines 444 is connected between each of the N second switches 446b and each of the N second write data buffers 442b. Finally, each of the N local data lines 448 is connected between each of the N second switches 446 b and the memory cell array 410.

  FIG. 8 shows an operation method according to the second embodiment of the present invention. In this operation method, after N first groups of 2N data bits divided into 2 parts are received in series from the external terminal 426, 2N data bits are divided into 2 parts each. The remaining N second groups are received from the external terminal 426 in series. After the N first groups of 2N data bits are stored in the first write data buffer 442a, the remaining N second groups of 2N data bits are stored in the first write data buffer. When the data is stored in 442a, the data is shifted from the first write data buffer 442a to the second write data buffer 442b through the N first switches 446a. Of the 2N data bits, N first groups are written from the second write data buffer 442b to the memory cell array 410 through the N second switches 446b. The remaining N second groups of the 2N data bits are shifted from the first write data buffer 442a to the second write data buffer 442b through the N first switches 446a and then through the second switch 446b. Data is written in the memory cell array 410. That is, FIG. 8 shows a write data pipeline system in which 2N data bits are stored in the write data path 420 ″, and N data bits are written in the memory cell array 410 in parallel.

  9A and 9B are specific block diagrams of the integrated circuit memory device of the first embodiment shown in FIG. In the embodiment shown in FIGS. 9A and 9B, an 8-bit prefetch operation is performed in a scheme with a burst length of 4 (BL = 4). However, it will be apparent to those skilled in the art that in other embodiments, it can be used as a smaller or larger prefetch scheme. As shown in FIGS. 9A and 9B, despite the 8-bit prefetch operation, only eight local data lines LDL_0 to LDL_3 are used while eight global data lines GDL_0 to GDL_7 are used. Therefore, the layout area of the memory device is reduced as compared with the memory device of FIG. 5 even when the 8-bit prefetch operation is performed.

  Referring to FIG. 9A, burst length = 8 (BL = 8) is selected by the mode register MRS, and an 8-bit input date corresponding to BL = 8 is received by the buffer 502 in series. The first input data bit output from the buffer 502 is stored in the first latch 511 of the first input data latch circuit 512 in response to the rising edge of the first internal data strobe signal PDS. The second input data bit is stored in the second latch 513 of the first input data latch circuit 512 in response to the falling edge of the first internal data strobe signal PDS. After the two input data bits are stored in the first input data latch circuit 512, the first input data bit of the first latch 511 and the second input data bit of the second latch 513 are the first falling edge of the PDS signal. Are simultaneously transmitted to the third latch 515 and the fourth latch 517 of the parallel conversion unit 514 in response to the second internal data strobe signal PDSP generated at the same time.

  Next, in FIG. 9A, the third input data bit is stored in the first latch 511 of the first input data latch circuit 512 in response to the second rising edge of the first internal data strobe signal PDS, and the fourth input data The bit is stored in the second latch 513 of the first input data latch circuit 512 in response to the second falling edge of the first internal data strobe signal PDS. At the same time, the third and fourth input data bits are transmitted to the P1 and P4 nodes of the parallel conversion unit 514 in response to the second rising edge and falling edge of the PDS signal, respectively. As a result, 4 bits of the serial input data are converted into 4-bit parallel input data as indicated by P1 to P4 in the parallel conversion unit 514. The parallel data output 516 outputs 4-bit input data to the data ordering circuit 520. The data ordering circuit 520 determines the output order of 4-bit parallel input data. However, in other embodiments of the present invention, the data ordering circuit 520 may not be used. The 4-bit parallel data P1 to P4 are stored in the respective write data buffers 532, 534, 536, and 538 in response to the first write control signal WDBICS provided to the plurality of write switches (WSW) 522 to 528. The first write control signal WDBICS is generated from the data strobe counter described with reference to FIG.

  Further, the fifth input data bit output from the buffer 502 is stored in the fifth latch 611 of the second input data latch circuit 612 in response to the rising edge of the fourth internal data strobe signal PDS ′. The sixth input data bit is stored in the sixth latch 613 of the second input data latch circuit 612 in response to the falling edge of the fourth internal data strobe signal PDS ′. After the fifth and sixth input data bits are stored in the second input data latch circuit 610, the fifth and sixth input data bits in the fifth and sixth latches 611 and 613 are the first rising edge of the PDS ′ signal. In response to the fifth internal data strobe signal PDSP ′ generated from the falling edge, the signals are simultaneously transmitted to the seventh and eighth latches 615 and 617 of the parallel conversion unit 614, respectively.

  Thereafter, the seventh input data bit is stored in the fifth latch 611 in response to the second rising edge of the fourth internal data strobe signal PDS ′, and the eighth input data bit is stored in the fourth internal data strobe signal PDS ′. In the sixth latch 613 in response to the second falling edge. At the same time, the seventh and eighth input data bits are transmitted to the nodes P1 'and P4' of the parallel conversion unit 614 in response to the second rising edge and falling edge of the PDS 'signal, respectively. As a result, the fifth to eighth input data bits received in series are converted into the fifth to eighth parallel data bits P1 'to P4'. The parallel data output 616 outputs the 4-bit parallel input data to the data ordering circuit 620 that determines the order of the 4-bit parallel input data. As described above, in other embodiments, the data ordering circuit 620 may not be used.

  Then, the 4-bit parallel data is stored in the plurality of write data buffers 632 to 638 in response to the second write control signal WDICS '. The second write control signal WDBICS 'is generated by the data strobe counter described with reference to FIG. Therefore, 8 bits of serially received data are converted into 8-bit parallel data and stored in the eight write data buffers 532-538 and 632-638.

  Therefore, in the embodiment of the present invention described in FIG. 9A, the first serial-parallel converter 510 responds to the first internal data strobe signals, eg, PDS, PDSP and PDSEN, and the second serial-parallel converter 610. Responds to a second internal data strobe signal, eg PDS ′, PDSP ′ and PDSEN ′. Meanwhile, referring to FIG. 9B, both the first serial-parallel converter 510 'and the second serial-parallel converter 610' respond to internal data strobe signals, eg, PDS, PDSP, and PDSEN at the same time.

  Next, the operation of the integrated circuit memory device shown in FIGS. 9A and 9B will be described. In this integrated circuit memory device, after the 8-bit serial input data is stored in the eight write data buffers, the first group of 4 bits, which are the parallel input data stored in the first write data buffers 532 to 538, are stored in the integrated circuit memory device. In response to the first switching signal CICS provided to the plurality of control switches (CSWs) 542 to 548, the data is transmitted to the local data lines LDL_ 0 to LDL_ 3 and supplied to the column selection line unit 550. The selected memory cell of the memory cell array 560 is written through the bit line BL selected in response. Next, the second group of 4-bit parallel input data stored in the second write data buffers 632 to 638 is respectively responsive to the second switching signal CICS ′ provided to the second control switches (CSW) 642 to 648. Local data lines LDL_0 to LDL_3.

  Here, the CSWs 542 to 548 are called first control switches, and the CSWs 642 to 648 are called second control switches. Further, the WSWs 522 to 528 are referred to as third switches, and the WSWs 622 to 628 are referred to as fourth switches.

  Therefore, as shown in FIGS. 9A and 9B, in the embodiment of the present invention, only four local data lines LDL_0 to LDL_3 are used together with eight global data lines GDL_0 to GDL_7. Therefore, the integrated circuit layout area is reduced as compared with the conventional write data path in which 8-bit prefetch is performed with 8 global data lines and 8 local data lines.

  FIG. 10 is a block diagram illustrating a circuit for generating the first write control signal WDBICS and the second write control signal WDBICS ′ according to an embodiment of the present invention. As shown in FIG. 10, the write control signal counts the buffer 710 responding to the first data strobe signal PDS and the rising and falling edges of the first data strobe signal PDS in response to the output of the buffer 710. Generated by the data strobe counter 720. The first write control signal WDBICS is generated in response to the second falling edge of the data strobe signal PDS, and the second write control signal WDBICS ′ is in response to the fourth falling edge of the data strobe signal PDS. appear. This embodiment may also generate PDSEN and PDSEN 'signals.

  FIG. 11 is a block diagram illustrating an embodiment of a switching signal generation circuit for the embodiment described in FIG. As shown in FIG. 11, the switching signal is generated using the commander decoder 104 which generates the active command signal ACT, the read command signal RDA, and the write command signal WRA in response to the chip selection signal / CS and the function signal FN. appear. The control signal generation circuit 1110 generates the first and second switching signals CICS and CICS ′ at a predetermined time interval in response to the write command signal WRA.

  Next, in another embodiment of the present invention, the instruction decoder 1104 of FIG. 11 is shown as 1104 ′, and a mode reset instruction in response to the chip select signal / CS, function signal, and FN provided to the instruction decoder 1104. A refresh instruction REF is also generated.

  12A and 12B are timing diagrams for performing an 8-bit prefetch operation according to the embodiment of the present invention described in FIGS. 7 and 9A to 11. More specifically, FIG. 12A is the timing diagram of FIG. 9A, and FIG. 12B is the timing diagram of FIG. 9B. These timing diagrams illustrate various control signals as well as the operation of the write data buffers 532-538, 632-638 described above. For comparison, FIGS. 13 and 14 are timing diagrams illustrating the 4-bit prefetch operation of the FCRAM and the 4-bit prefetch operation of the DDR SDRAM described above with reference to FIG.

  In FIG. 13, the 4-bit input data for writing to the address “0000” is not written in response to the previous write command WR0, but is written after receiving the next write command WR1. Therefore, the input data is stored in the write data buffer in the previous cycle CYC # 1, and then written in the memory cell in response to the next write command WR1 in the cycle CYC # 2.

  In FIG. 14, in the DDR SDRAM, the 4-bit input data for writing to the address “0000” is not in response to the next write command WR1, but in response to the write command WR0, as shown in FIG. Data is written in the corresponding memory cell. The DDR SDRAM does not include a write data buffer because input data is immediately written to a memory cell without being stored in the write data buffer.

  FIG. 15 is a more specific block diagram of the second embodiment of the present invention described in FIG. As shown in FIG. 8, a pipeline configuration is used for the write data path to simply use N global data lines and N local data lines for 2N write data paths. This reduces the number of global data lines and local data lines compared to the conventional write data path.

  More specifically, referring to FIG. 15, the write data path 700 includes, for example, a serial-parallel converter 510, an optional data ordering circuit 520, and first switches 722 to 728 as already described in FIG. The first write data buffers 732 to 738, the second switches 742 to 748, the second write data buffers 752 to 758, and the third switches 762 to 768 are included. As shown in FIG. 15, such an embodiment has fewer data lines than the embodiment of FIG. 9, for example. This is because the number of global data lines GDL_0 to GDL_3 is the same as that of the 4-bit prefetch scheme and the number of local data lines LDL_0 to LDL_3 is the same as that of the 4-bit prefetch scheme. Therefore, the layout area of the memory device is reduced.

  Next, in FIG. 15, 8-bit input data corresponding to BL = 8 is received serially through the buffer 502. The first 4 bits of the serial input data are converted to 4-bit parallel input data in the parallel output data circuit 510, and the first 4 bits of the parallel input data are provided to the optional data ordering circuit 520. The data ordering circuit 520 determines the output order of 4-bit parallel input data. Thereafter, the first 4 bits of the parallel input data are stored in the first write data buffers 732 to 738 in response to the first write control signal WDBICS provided to the write switches (WSW) 722 to 728. At the same time, the second 4 bits of the serial input data are converted from the parallel data output circuit 510 to 4 bits of parallel input data and provided to the data ordering circuit 520 if present.

  Then, the first four bits of the parallel input data stored in the first write data buffers 732 to 738 are second written in response to the second write control signal WDBICS ′ provided to the write switches WSW and 742 to 748. It is stored in the data buffers 752 to 758. At the same time, the second four bits of parallel bit data from the data ordering circuit 520 are also stored in the first write data buffers 732 to 738 in response to the second activation of the first write control signal WDBICS. As a result, the first 4 bits and the second 4 bits of the parallel input data are sequentially transmitted to the memory cell array 560 and selected in response to a number of WDBICS, WDBICS ′, CICS, and CSL signals. Is written to. As shown in FIG. 15, these WDBICS, WDBICS ', CICS, and CSL signals are enabled twice for the first 4 bits for pipeline operation and for the second 4 bits. Is done.

  Next, a precharge control circuit according to an embodiment of the present invention will be described. This precharge control circuit groups each of the N parallel bits into two groups, and activates the word lines of the memory cell array for a time sufficient to write 2N data bits to the memory cell array. And in connection with the embodiment of FIG. In order to describe the precharge control circuit according to the embodiment of the present invention, a conventional precharge control circuit will be described with reference to FIG.

  FIG. 16 is a timing diagram for a conventional precharge control circuit used in conjunction with FIG. In order to activate the word line to write any input data D0, D1, D2, D3 to the corresponding memory cell using a 4-bit prefetch scheme as shown in FIG. Enabled.

  FIG. 17 shows a conventional technique for enabling a word line in the 8-bit prefetch scheme described with reference to FIG. In FIG. 17, in the 8-bit prefetch scheme shown in FIG. 5, 8 bits are written in parallel, and therefore, T0 time used in the 4-bit prefetch scheme shown in FIG. 16 writes 8-bit input data to the memory cell. It is enough time. This is because an 8-bit input date in FIG. 5 is written into the corresponding memory cell at the same time after being converted into parallel input data.

  FIG. 18 explains why the precharge scheme shown in FIGS. 16 and 17 is not applied to the embodiment of the present invention. In particular, as shown in FIG. 18, if the same prefetch time T0 is used in the embodiment of the present invention, the N second groups of the 2N data bits divided into two are divided into memory. Cannot write to the cell array. In other words, the input data D4 to D7 are lost. According to an embodiment of the present invention, the precharge control circuit activates the word line of the memory cell for a time sufficient to write 2N data bits, which are two groups of N parallel data, to the memory cell array. Let

  More specifically, as shown in FIG. 18, the T0 time used for the 4-bit prefetch scheme is not sufficient to write 8-bit input data to the memory cell array according to an embodiment of the present invention. This is because, as described above, according to the embodiment of the present invention, the 8-bit input date is not simultaneously written into the memory cell. In other words, 8-bit serial input data is divided into first and second groups. A first group of 4-bit serial input data is converted to 4-bit parallel data. Thereafter, the second group of 4-bit serial input data is converted to 4-bit parallel input data. Thereby, after the first 4-bit input data is written in parallel to the memory cell, the second 4-bit input data is written in parallel to the memory cell. Therefore, in the embodiment of the present invention, the word line enable time must be adjusted by burst length (BL) = 4, BL = 8.

  FIG. 19 illustrates the word line of the memory cell array for a time sufficient to write 2N data bits, which are two groups of N parallel bits, into the memory cell array during the first precharge mode of the integrated circuit memory device. 2 is a circuit diagram of a precharge control circuit for enabling The precharge control circuit 1900 provides a word of the memory cell array for a time sufficient to write a group of N data bits, one form of N parallel bits, to the memory cell array during a second precharge mode of the integrated circuit memory device. Activate the line.

  More specifically, as shown in FIG. 19, the precharge control circuit 1900 receives the burst length signals BL-1 and BL-2 and the precharge command signal AP_CMD generated by the command decoder 1904, and then precharges the signal. The charge control signal AP is output. Command decoder 1904 can respond to external command signals / CS, FN and external clock signals CLK, / CLK. For example, when the memory device operates with 4-bit prefetch (when BL = 4 is selected), BL-1 is enabled. In the embodiment of the present invention, BL-2 is enabled when the memory device operates with 8-bit prefetch (when BL = 8 is selected).

  As shown in FIG. 19, the delay time DT1 for BL = 4 is shorter than the delay time DT2 for BL = 8. Accordingly, the first delay circuit 1910 provides a relatively short first delay time DT1, and the second delay circuit 1920 provides a relatively long second delay time DT2. In one embodiment, DT1 is 3.5 clock cycles, while DT2 is 5.5 clock cycles. The coupling circuit 1930 provides a precharge control signal AP from the first delay circuit 1910 and the second delay circuit 1920. Therefore, the precharge control signal AP for BL = 4 is activated faster than the precharge control signal AP for BL = 8 to deactivate the word line. Therefore, the word line enable time for BL = 8 is longer than the T0 time shown in FIG.

  As shown in FIG. 13, the word line enable time for BL = 4 is approximately 3.5 clock cycles. On the other hand, as shown in FIG. 12, the word line enable time for BL = 8 is approximately 5.5 clock cycles. In one embodiment, the mode register is set to select the first and second precharge modes, and the precharge control circuit 1910 is responsive to the mode resist.

  Next, additional items of the write data buffer according to the embodiment of the present invention will be described. FIG. 20 exemplarily shows one of the write data buffers of FIGS. 6 to 9 and FIG. The write data buffer 2010 includes an address latch 2012 that latches a write address. The address comparison unit 2014 compares the write address latched by the address latch 2012 with the current write address. The data latch 2016 latches write data corresponding to the write address. In one embodiment, if the current address is a read address and the address comparator 2014 determines that the read address and the write address latched in the address latch 2012 match, the integrated circuit memory device is not from the memory cell array. Instead, read data is output from the data latch 2016 to the external terminal. In another embodiment, if the current address is a read address and the address comparator 2014 determines that the read address and the write address latched in the address latch 2012 do not match, the integrated circuit memory device Read data is output from the cell array to the external terminal.

  FIG. 20 shows not only the data write structure and process of the embodiment of the present invention, but also the data read structure and process. The write data buffer 2010 includes an address latch 2012, an address comparison unit 2014, and a data latch 2016. The address latch 2012 is controlled by a write command signal WR provided from an instruction decoder such as the instruction decoder 104 and stores an input address received from the address buffer 106. At the same time, input data corresponding to the input address is stored in the data latch 2016. The address comparison unit 2014 compares the input address stored in the address latch 2012 with the current input address and outputs an address comparison signal ADCMP to the DQ buffer 2020. If the current input address matches the stored input address, the ADCMP signal is activated to a high level, for example. As a result, the read data stored in the data latch 2016 is output to the DQ pad through the first transmission gate 2022. However, if the current input address is different from the stored input address, the ADCMP signal is deactivated. Under such circumstances, read data stored in the memory cell array is output to the DQ pad through the second transmission gate 2024.

  FIG. 21 is a timing diagram illustrating a data read / write process according to an embodiment of the present invention in conjunction with FIGS. 15 and 18 to 20. As shown in FIG. 21, pipeline writing of data bits occurs between two cycles CYC # 1, CYC # 2 that include an extended wordline enable signal. Furthermore, as shown in FIG. 21, when the memory device receives a read command RD from the command decoder 104, the address comparison unit 2014 in FIG. 20 receives the current input address (0001; RD command input) and an address latch. Is compared with the input address (0001; WR1 command input) stored in the. Here, since both have the same address, read data is immediately output from the write data buffers 532 to 538 instead of the memory cell array.

  Although the present invention has been described through the embodiments, this is merely an example, and it is understood by those skilled in the art that various modifications and other equivalent embodiments are possible. It will be possible. Accordingly, the true technical protection scope of the present invention must be determined by the technical ideas of the claims.

  Integrated circuit memory devices according to the present invention are widely used in consumer and commercial applications.

2 is a block diagram of a conventional DRAM. 2 is a specific block diagram of the data input / output path of FIG. 2 is a block diagram illustrating a 4-bit prefetch scheme in a conventional fast cycle DRAM. 4 is a timing diagram illustrating the operation of the apparatus of FIG. 1 is a block diagram of a conventional fast cycle DRAM including an 8-bit prefetch scheme. 1 is a block diagram of an integrated circuit memory device according to an embodiment of the present invention. 3 is a block diagram of a write data path of an embodiment of the present invention. 3 is a block diagram of a write data path of an embodiment of the present invention. 8 is a specific block diagram of the integrated circuit memory device generally described in FIG. 8 is a specific block diagram of the integrated circuit memory device generally described in FIG. 3 is a block diagram illustrating generation of a write control signal according to an embodiment of the present invention. 10 is a block diagram illustrating generation of a switching signal according to the embodiment of the present invention described in FIG. 12 is a timing diagram illustrating an 8-bit prefetch operation according to an embodiment of the present invention described in FIGS. 7 and 9A to 11. 12 is a timing diagram illustrating an 8-bit prefetch operation according to an embodiment of the present invention described in FIGS. 7 and 9A to 11. 6 is a timing diagram illustrating a conventional 4-bit prefetch operation in a fast cycle DRAM and a dual data rate DRAM. 6 is a timing diagram illustrating a conventional 4-bit prefetch operation in a fast cycle DRAM and a dual data rate DRAM. FIG. 9 is a specific block diagram of an embodiment of the invention generally described in FIG. It is a timing diagram of the conventional precharge control circuit. It is a figure explaining the prior art which enables a word line by an 8-bit prefetch scheme. A free charging timing diagram of an embodiment of the present invention will be described. It is a circuit diagram of the precharge control circuit of the embodiment of the present invention. 3 is a block diagram of a read / write data buffer according to an embodiment of the present invention. 3 is a timing diagram illustrating a data read / write process according to an embodiment of the present invention.

Explanation of symbols

510 1st serial-parallel conversion part 511 BL_0-BL_
512 First input data latch circuit 513 Second latch 514 Parallel converter 515 Third latch 516 Parallel data output 517 Fourth latch 520 Data ordering circuit 522, 524, 526, 528 Write switch 532, 534, 536, 538 Write data buffer 542, 544, 546, 548 Control switch 550 Column selection line unit 560 Memory cell array 610 Second input data latch circuit 611 Fifth latch 612 Second input data latch circuit 613 Sixth latch 614 Parallel conversion units 615, 617 8 Latch 616 Parallel data output 620 Data ordering circuit 622, 624, 626, 628 Write switch 632, 634, 636, 638 Write data buffer 642, 644, 646, 648 Second control switch

Claims (8)

A memory cell array including a plurality of memory cells;
A write data path for receiving in serial 2N data bits from an external terminal,
The write data path is:
2N write data buffers;
2N switches,
N data lines connected to at least N of the 2N switches to write N data bits to the memory cell array in parallel,
The write data path is:
First and second series-parallel converters connected to the external terminal;
Comprising N first global data lines and N second global data lines;
The 2N write data buffers include N first write data buffers and N second write data buffers.
The 2N switches are configured to include N first switches and N second switches,
The N first write data buffers are connected to a first serial-parallel converter, and each of the N first global data lines includes each of the N first switches and the N first switches. 1 write data buffer connected to each
The N second write data buffers are connected to a second serial-to-parallel converter, and each of the N second global data lines includes each of the N second switches and the N second switches. Connected to each of the two write data buffers,
The N data lines are N local data lines;
Each of the N local data lines is connected between the N first switches, the N second switches, and the memory cell array, respectively.
The write data path is:
The first and second serial-to-parallel converters may be connected between one of the first and second serial-parallel converters and one of the N first write data buffers and the N second write data buffers, respectively. 1 and a second data ordering circuit,
The N first switches are responsive to a first control signal;
The N second switches are responsive to a second control signal delayed from the first control signal;
The first and second control signals are:
An integrated circuit device produced by being delayed from a write activation signal with different delay times. The integrated circuit device includes:
An instruction decoder for generating the write activation signal in response to a chip selection instruction and a function instruction;
2. The integrated circuit device according to claim 1, further comprising: a control signal generation unit that generates the first and second control signals in response to the write activation signal. The instruction decoder
The integrated circuit device according to claim 2, further generating an active command and a read command in response to the chip selection command and the function command. The instruction decoder
The integrated circuit memory device according to claim 2, further comprising a read command, a refresh command, and a mode register command in response to the chip selection command and the function command. A memory cell array including a plurality of memory cells;
A write data path for receiving in serial 2N data bits from an external terminal,
The write data path is:
2N write data buffers;
2N switches,
N data lines connected to at least N of the 2N switches to write N data bits to the memory cell array in parallel,
The write data path is:
First and second series-parallel converters connected to the external terminal;
Comprising N first global data lines and N second global data lines;
The 2N write data buffers include N first write data buffers and N second write data buffers.
The 2N switches are configured to include N first switches and N second switches,
The N first write data buffers are connected to a first serial-parallel converter, and each of the N first global data lines includes each of the N first switches and the N first switches. 1 write data buffer connected to each
The N second write data buffers are connected to a second serial-to-parallel converter, and each of the N second global data lines includes each of the N second switches and the N second switches. Connected to each of the two write data buffers,
The N data lines are N local data lines;
Each of the N local data lines is connected between the N first switches, the N second switches, and the memory cell array, respectively.
The write data path is:
The first and second serial-to-parallel converters may be connected between one of the first and second serial-parallel converters and one of the N first write data buffers and the N second write data buffers, respectively. 1 and a second data ordering circuit,
The N first switches are responsive to a first control signal;
The N second switches are responsive to a second control signal delayed from the first control signal;
The integrated circuit device includes:
Further comprising N third switches and N fourth switches;
Each of the N third switches is connected between the first serial-parallel converter and each of the N first write data buffers.
The integrated circuit device, wherein the N fourth switches are connected between the second serial-parallel converter and each of the N second write data buffers. The N third switches are responsive to a third control signal;
The integrated circuit device according to claim 5, wherein the N fourth switches are responsive to a fourth control signal delayed from the third control signal. The third and fourth control signals are:
The integrated circuit device according to claim 6, wherein the integrated circuit device is generated in response to an offset falling edge of the data strobe signal. The integrated circuit device includes:
A data strobe counter for counting the falling edge of the data strobe signal in response to the data strobe signal and generating the third and fourth control signals according to the offset falling edge of the data strobe signal; The integrated circuit device according to claim 7.

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