JP4940894B2 - 同期型メモリ回路 - Google Patents
同期型メモリ回路 Download PDFInfo
- Publication number
- JP4940894B2 JP4940894B2 JP2006293486A JP2006293486A JP4940894B2 JP 4940894 B2 JP4940894 B2 JP 4940894B2 JP 2006293486 A JP2006293486 A JP 2006293486A JP 2006293486 A JP2006293486 A JP 2006293486A JP 4940894 B2 JP4940894 B2 JP 4940894B2
- Authority
- JP
- Japan
- Prior art keywords
- write
- read
- burst length
- data
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Description
Claims (4)
- 読み出し命令により読み出しデータのバースト長が変更される第1の制御回路と、
第1の書き込み命令の直前のサイクルにて第2の書き込み命令が与えられているか否かに応じて、書き込みデータのバースト長が変更される第2の制御回路と、を有し、
ラッチされているライトデータを上記バースト長で書き込み、
上記読み出し命令と同じサイクルで上記第2書き込み命令を与えることが可能なことを特徴とする同期型メモリ回路。 - 請求項1において、
上記第2の書き込み命令が与えられた場合の上記第1の書き込み命令による書き込みデータのバースト長は、上記第2の書き込み命令が与えられなかった場合の上記第1の書き込み命令による書き込みデータのバースト長よりも短いことを特徴とする同期型メモリ回路。 - 請求項1において、
上記第1の書き込み命令または上記第2の書き込み命令と同じサイクルで読み出し命令を与えることが可能なことを特徴とする同期型メモリ回路。 - 請求項3において、
複数のバンクを有し、上記第1の書き込み命令、上記第2の書き込み命令及び上記読み出し命令は、それぞれ異なるバンクに作用することを特徴とする同期型メモリ回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006293486A JP4940894B2 (ja) | 2006-10-30 | 2006-10-30 | 同期型メモリ回路 |
US11/926,756 US7729198B2 (en) | 2006-10-30 | 2007-10-29 | Synchronous memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006293486A JP4940894B2 (ja) | 2006-10-30 | 2006-10-30 | 同期型メモリ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008112485A JP2008112485A (ja) | 2008-05-15 |
JP4940894B2 true JP4940894B2 (ja) | 2012-05-30 |
Family
ID=39444926
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006293486A Expired - Fee Related JP4940894B2 (ja) | 2006-10-30 | 2006-10-30 | 同期型メモリ回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7729198B2 (ja) |
JP (1) | JP4940894B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101115452B1 (ko) * | 2010-10-29 | 2012-02-24 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 링백 회로 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10208468A (ja) * | 1997-01-28 | 1998-08-07 | Hitachi Ltd | 半導体記憶装置並びに同期型半導体記憶装置 |
GB2332539B (en) * | 1997-12-17 | 2003-04-23 | Fujitsu Ltd | Memory access methods and devices for use with random access memories |
JP3251237B2 (ja) * | 1998-05-29 | 2002-01-28 | 日本電気株式会社 | Sdramにおける再プログラミング方法 |
KR100306965B1 (ko) | 1998-08-07 | 2001-11-30 | 윤종용 | 동기형반도체메모리장치의데이터전송회로 |
JP4439033B2 (ja) | 1999-04-16 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP4108237B2 (ja) * | 1999-11-04 | 2008-06-25 | 株式会社リコー | メモリ制御装置 |
US6580659B1 (en) * | 2000-08-25 | 2003-06-17 | Micron Technology, Inc. | Burst read addressing in a non-volatile memory device |
KR100415192B1 (ko) * | 2001-04-18 | 2004-01-16 | 삼성전자주식회사 | 반도체 메모리 장치에서 읽기와 쓰기 방법 및 장치 |
-
2006
- 2006-10-30 JP JP2006293486A patent/JP4940894B2/ja not_active Expired - Fee Related
-
2007
- 2007-10-29 US US11/926,756 patent/US7729198B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7729198B2 (en) | 2010-06-01 |
US20080175091A1 (en) | 2008-07-24 |
JP2008112485A (ja) | 2008-05-15 |
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