JP2000227897A - Device and system for dma transfer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a useful DMA transfer device which is compatible with a memory which capable of quick page access and actualizes high-speed DMA transfer without sacrificing performances. SOLUTION: A partial area discriminating parts 211 (or 311) discriminates plural transfer source (or transfer destination) partial areas which constitute a memory area at a transfer source (or transfer destination), i.e., plural transfer source (or transfer destination) partial areas which are sectioned between the head of the memory area, a page boundary or the end of the memory area and a page boundary. An access means 120 reads data by quick page access out of the discriminated transfer source partial areas and writes the read data to the transfer destination partial area by quick page access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION D which guarantees continuous access in units of pages to a memory which can be accessed at high speed pages
MA data transfer device

[0002]

2. Description of the Related Art A conventional DMA data transfer device performs high-speed data transfer between a memory and a memory or between a memory and an input / output device. In a transfer between memories connected to the same bus and a transfer between different storage areas of the same memory, the DMA data transfer apparatus temporarily holds data read from the transfer source storage area in a buffer in the DMA data transfer apparatus. Then, DMA data transfer is performed by writing data from the buffer to the storage area of the transfer destination. This buffer is
It has a capacity equal to or larger than the size of one access to the memory. In a typical conventional DMA data transfer, data is read from a transfer source, stored in a buffer, and written from a buffer to a transfer destination storage area for each data of one access size. This enables DMA data transfer with a minimum necessary buffer size.

If the buffer size is a multiple of the access size, the DMA transfer device reads data from the transfer source until the buffer size is reached and stores the data in the buffer. Write data to the destination storage area. In this case, reading and writing are performed in units of a buffer size.

[0004]

In recent years, an SDRAM capable of high-speed page access has been used as a main memory.
There is a problem that the high speed performance of the DRAM is sacrificed and its usefulness cannot be fully utilized. Because the traditional DM
This is because the A transfer device accesses the buffer from the transfer source to the buffer and writes from the buffer to the transfer destination irrespective of the page boundary.

SUMMARY OF THE INVENTION An object of the present invention is to provide a useful DMA transfer device which is compatible with high-speed page accessible memories and realizes high-speed DMA transfer without sacrificing its performance.

[0006]

A DMA transfer device according to the present invention is a DMA transfer device for a memory corresponding to a high-speed page access, and includes a plurality of partial areas constituting a memory area to be transferred. Determining means for determining each partial area between the beginning of the memory area and the page boundary, between page boundaries, and between the page boundary and the end of the memory area; and a high-speed page access for each determined partial area. And access means for performing the following.

Further, the DMA transfer device of the present invention is a plurality of transfer source partial areas constituting a first memory area serving as a transfer source, wherein a plurality of transfer source partial areas are provided between a head of the first memory area and a page boundary. A first discriminating means for discriminating each transfer-source partial area between the end of the first memory area and a page boundary, and a plurality of transfer-destination partial areas constituting a second memory area serving as a transfer destination. Second determining means for determining each transfer destination partial area between the beginning of the second memory area and the page boundary, between the page boundaries, and between the page boundary and the end of the second memory area; The data is read out from the transfer source partial area determined by the means by high-speed page access and stored in the buffer means, and the data stored in the buffer means is read into the transfer destination partial area determined by the second determination means at the high speed page access. And an access means for writing by.

A DMA transfer system according to the present invention is a DMA transfer system having a plurality of DMA channels having different priorities. The DMA transfer system is provided for each DMA channel and receives a DMA transfer request of a corresponding DMA channel.
A plurality of receiving means for holding a DMA transfer request until the completion of the transfer; and a plurality of receiving means provided for each DMA channel and constituting a memory area to be transferred specified in the DMA transfer request of the corresponding DMA channel. A plurality of discriminating means for discriminating each partial area between the beginning of the memory area and the page boundary, between the page boundaries and between the page boundary and the end of the memory area;
A plurality of access request generation means provided for each MA channel for generating an access request for instructing high-speed page access for each partial area determined by the corresponding DMA channel determination means; Buffer means for temporarily holding data to be transmitted, and arbitration means. Here, if the plurality of accepting units hold a DMA transfer request for only one DMA channel, the arbitrating unit performs access according to the access request corresponding to the DMA channel, and
A transfer request is held and DM with high priority
When the DMA transfer request for the A channel is accepted, the discriminating means and the access request generating means corresponding to the DMA channel of the preceding DMA transfer request are instructed to empty the buffer means and then suspend the processing. Becomes empty, access is made in accordance with the access request of the high-priority DMA channel, and the high-priority DM
After the completion of the A transfer, an instruction is issued to the determining means and the access request generating means corresponding to the DMA channel of the preceding DMA transfer request to restart the DMA transfer.

A DMA transfer system according to the present invention is a DMA transfer system having a plurality of DMA channels. The DMA transfer system is provided for each DMA channel, receives a DMA transfer request of a corresponding DMA channel, and waits until the DMA transfer is completed. A plurality of receiving means for holding transfer requests;
For the transfer target memory area specified in the transfer request,
A plurality of partial areas constituting the memory area, each of which identifies a respective partial area between the beginning of the memory area and a page boundary, between page boundaries, and between a page boundary and the end of the memory area. Determining means, and a plurality of access request generating means provided for each DMA channel and generating an access request for instructing high-speed page access for each partial area determined by the corresponding DMA channel determining means;
It comprises a buffer means, which is a two-port memory shared by each DMA channel and connected to two buses, and an arbitration means. Here, if the plurality of accepting units hold a DMA transfer request for only one DMA channel, the arbitrating unit performs access in accordance with the access request corresponding to the DMA channel,
When a transfer request is held, a DMA transfer request for another DMA channel is accepted, and a transfer destination of a preceding DMA transfer and a transfer source of a new DMA transfer are memories on different buses. Has been read from the transfer source for all transfer data being transferred, and
When the buffer unit has a free area corresponding to the read size of the first partial area of another DMA channel, the reading of the first partial area of the other DMA channel is started.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment><OverallConfiguration> FIG. 1 shows a main part of an information processing apparatus having a DMA (Direct Memory Access) transfer device according to a first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration. The information processing apparatus shown in FIG. 1 is, for example, a digital satellite broadcast receiver (hereinafter referred to as an STB (Set Top Box)) or a DVD (Digita
l Video / Versatile Disk), used for controlling the entire device such as an optical disk recording / reproducing device such as a DVD-RAM.
/ O unit 5, SDRAM4, SDRAM I / F3, CP
U2, a DMA transfer device 1 is provided.

The I / O section 5 inputs and outputs an MPEG stream and inputs key data from a remote controller (not shown). The SDRAM 4 is a memory corresponding to high-speed page access. High-speed page access refers to high-speed access to a continuous storage area called a predetermined page. In this embodiment, the SDRAM
4 is 32 bits (hereinafter, 32 bits are defined as 1 word)
Data width of one page is 4 words (16 bytes)
It is a continuous storage area for each. Here, the size of one page can be set to another size such as 2 words or 8 words, but is preferably set to be the same as the cache fill size of the CPU 2 (unit for updating the cache memory). This is because the configuration of the SDRAM I / F 3 can be shared between the CPU 2 and the DMA transfer device 1 and can be simplified. In this embodiment, the cache fill size is also assumed to be 16 bytes.

The SDRAM I / F 3 transfers an access signal group (address, data, various control signals) sent from the DMA transfer device 1 and the CPU 2 onto the bus to the SDRAM 4.
, And accesses the SDRAM 4.
The CPU 2 has a cache memory therein, controls the entire information processing apparatus, and sets a DMA transfer request to the DMA transfer apparatus 1. The DMA transfer in FIG.
Transfer from the AM 4 to the SDRAM 4 (that is, between different storage areas in the SDRAM 4), the SDRAM 4 and the I / O unit 5
And the transfer between the SDRAM 4 and the MPEG decoder (not shown).

The DMA transfer device 1 performs DMA transfer between different storage areas of the SDRAM 4, between the SDRAM 4 and the I / O unit 5, and the like.
Perform a transfer. At this time, when the transfer source or the transfer destination is the SDRAM 4, the DMA transfer device 1
A partial area demarcated from a page boundary existing in the area to be transferred is determined, and continuous access is made to each partial area by high-speed page access. <Configuration of DMA Transfer Apparatus 1> FIG.
FIG. 3 is a block diagram showing the configuration of FIG. As shown in the figure, the DMA transfer device 1 includes a mode setting unit 100, a read management unit 20
0, a read determination unit 210, a write management unit 300, a write determination unit 310, an access determination unit 110, an access control unit 120, and a buffer 130. The parentheses () attached to the arrows in the figure mean that the contents of the registers with the corresponding codes are input / output.

The mode setting unit 100 includes registers 101 to 10 for holding a DMA transfer request set by the CPU 2.
5 is provided. Here, the DMA transfer request is sent to the SDRAM 4
Between the SDRAM 4 and the I / O unit 5
It includes various parameters for requesting a DMA transfer not via U2. The various parameters include (1) DMA transfer size, (2) read start address, (3) write start address, (4) addressing mode, (5) access size, and the like. Here, (1) “transfer size” indicates the total data length (the number of bytes) to be DMA-transferred. (2) The “read start address” indicates a start address of data to be transferred stored in the transfer source (the SDRAM 4, the I / O unit 5, or the like). (3) The “write start address” is the transfer destination (SDRAM4 or I / O
Part 5). (4) The "addressing mode" indicates whether to access the transfer source and the transfer destination in ascending address or fixed address. (5) “Access size” indicates the data size to be read or written by one access for each of the transfer source and the transfer destination. In the present embodiment, it is assumed that the access size is 32 bits.

The registers 101 to 105 hold a transfer size, a read start address, a write start address, an addressing mode, and an access size in order.
It is cleared after the end of the DMA transfer by the transfer request. Hereinafter, the contents held in the registers 101 to 103 will be referred to as TRANSFER.
_SIZE_101, SRC_A_102, DST_A_103. The read management unit 200 determines the start address of unread data (hereinafter abbreviated as REMAIN_R_A_201) in the transfer source recording area specified by TRANSFER_SIZE_101 and SRC_A_10,
It manages the unread data size (hereinafter abbreviated as REMAIN_R_SIZE_202). Therefore, the read management unit 200
Has an address counter 201 and a data counter 202.

The address counter 201 holds the SRC_A_102 input from the register 102 as the initial value of the REMAIN_R_A_201 when the DMA transfer request is issued to the mode setting unit 100. Further, when the addressing mode is in the ascending address order, By adding the notified number of bytes to REMAIN_R_A_201 each time a notification about the number of bytes of the partial area that has been read is received from the read determination unit 210, the REMAIN_R_A_201 points to the start address of the next partial area. Update. The number of bytes of the partial area for which the reading has been completed is determined by the access control unit 120.
When the data of the transfer source partial area is read and stored in the buffer 130, the read determination unit 210 notifies. On the other hand, when the addressing mode is the fixed address, the address counter 201 stores the SRC_A_102 input from the register 102,
Do not update during MA transfer.

When a DMA transfer request is issued to the mode setting unit 100, the data counter 202
IZE_101 is held as the initial value of REMAIN_R_SIZE_202, and every time the read determination unit 210 notifies the number of bytes of the read-completed partial area, REMAIN_R_SIZE_20
Update by subtracting the number of bytes from 2. As a result, REMAIN_R_SIZE_202 indicates the unread data size in TRANSFER_SIZE_101.

The read determining section 210 includes a partial area determining section 211, an address register 212, and a size register 21.
After a DMA transfer request is issued to the mode setting unit 100, a partial area delimited by a page boundary in a storage area of unread data specified by REMAIN_R_A_201 and REMAIN_R_SIZE_202 is determined, and the determined partial area is determined. Start address of each (hereinafter PARTIAL_R_A_21
Abbreviated as 2. ) Is set in the address register 212, and the size of the determined partial area (PARTIAL_R_SIZE_213) is set in the size register 213. After the setting, the read determination unit 210
Upon receiving notification from the access control unit 120 that the reading of the partial area and the storage in the buffer 130 have been completed, the PARTIAL_R_SIZE_213 of the size register 213
Is notified to the read management unit 200 as the size of the partial area for which reading has been completed, and the next partial area is determined again and set in the address register 212 and the size register 213 as described above.

FIG. 3 shows an example of a partial area determined by the read determination unit 210. The figure shows SDRAM4
The storage area of the transfer source in FIG. The storage area of this transfer source is a storage area of 28 bytes starting from the address 500C (hexadecimal), that is, the SRC_A_102 has the address 500C and the TRA
NSFER_SIZE_101 is 28 bytes (7 words: ~ in the figure)
). Since the page size of the SDRAM 4 is 16 bytes (4 words), the data to be transferred (7 words in the figure) is stored over three pages.

In this case, the read determination unit 210 determines the next first to third partial areas in order. The first partial area is (PARTIAL_R_A_212, PARTIAL_R_SIZE_213) = (500C,
This is the storage area for the word represented by 4). The second partial area is a storage area of a word or more represented by (5010, 16). The third partial area is a storage area for the word represented by (5020,8). Since each partial area does not include a page boundary, it is suitable for high-speed page access.

The write management unit 300 transfers
In the transfer destination recording area specified by 101 and DST_A_103, the start address of the unwritten area (abbreviated as REMAIN_W_A_301) and the unwritten data size (REMAIN_W_SIZE_30)
2). Therefore, the write management unit 3
00 is an address counter 301 and a data counter 302
And

The address counter 301 holds DST_A_103 input from the register 103 as an initial value when a DMA transfer request is issued to the mode setting unit 100. Further, when the addressing mode is in the ascending address order, Each time a notification about the number of bytes of the partial area for which writing has been completed is received from the writing determination unit 310,
By adding the notified number of bytes to REMAIN_W_A_301, REMAIN_W_A_301 is updated so as to point to the start address of the next partial area. The write determining unit 310 notifies the number of bytes of the partial area for which the writing has been completed when the access control unit 120 writes data in the partial area of the transfer destination. On the other hand, if the addressing mode is fixed, the address counter 3
01 is not updated during DMA transfer while DST_A_103 input from the register 103 is stored.

When a DMA transfer request is issued to the mode setting unit 100, the data counter 302
IZE_101 is held as the initial value of REMAIN_W_SIZE_302, and each time the number of bytes of the partial area for which writing has been completed is notified from the writing determination unit 310, REMAIN_W_SIZE_30
Update by subtracting the number of bytes from 2. As a result, REMAIN_R_SIZE_202 indicates the unread data size in TRANSFER_SIZE_101.

The write determining section 310 includes a partial area determining section 311, an address register 312, and a size register 31.
After the DMA transfer request is issued to the mode setting unit 100, a partial area delimited by a page boundary in the unwritten storage area specified by REMAIN_W_A_301 and REMAIN_W_SIZE_302 is determined, and for each of the determined partial areas, Start address (hereinafter abbreviated as PARTIAL_W_A_312)
Is set in the address register 312 and the size of the determined partial area (hereinafter abbreviated as PARTIAL_W_SIZE_313) is set in the size register 313. After the setting, when a notification that the writing to the partial area is completed is received from the access control unit 120, the PARTIAL_W_SIZE_313 of the size register 313 is notified to the write management unit 300 as the size of the completed writing, and the same as above Then, the next partial area is set in the address register 312 and the size register 313 by determining the next partial area.

FIG. 4 shows an example of a partial area determined by the write decision unit 310. The figure shows SDRAM4
3 shows a part of the storage area of the transfer destination in FIG. This transfer destination storage area is a storage area of 28 bytes starting from address 6008, that is, DST_A_103 is located at address 6008 (hexadecimal),
FER_SIZE_101 is 28 bytes (7 words: ~ in the figure)
It is assumed that The page size of SDRAM4 is 16
Since it is a byte (4 words), the storage area (-in the figure) of the transfer destination is stored over three pages.

In this case, the write determining section 310 sequentially determines the next fourth to sixth partial areas. The fourth partial area is (PARTIAL_W_A_302, PARTIAL_W_SIZE_303) = (6008,
This is the storage area for the word represented by 8). The fifth partial area is a storage area of a word or more represented by (6010, 16). The sixth partial area is a storage area for the word represented by (6020,4). Since each partial area does not include a page boundary, it is suitable for high-speed page access.

The access determination unit 110 includes a buffer management unit 111 and a read / write determination unit 112. The access determination unit 110 reads from the transfer source partial area determined by the read determination unit 210 and stores it in the buffer 130 (hereinafter abbreviated as read). ) And writing (hereinafter abbreviated as “write”) of the data stored in the buffer 130 to the transfer destination partial area determined by the write determining unit 310. 130 is determined according to the data amount.

The buffer management unit 111 has a REMAIN_R_SIZE_
202 and REMAIN_W_SIZE_302 are entered, and REMAIN_R_SIZE_
By subtracting REMAIN_W_SIZE_302 from 202, the amount of data temporarily held in the buffer 130 is calculated. The read / write determination unit 112 is a buffer management unit 1
If the data amount calculated in 11 is smaller than PARTIAL_W_SIZE_313, it is determined that the access control unit 120 performs reading, and if not, it is determined that the access control unit 120 performs writing.

The access control unit 120 reads data from the partial area of the transfer source by the read determination unit 210 and stores it in the buffer 130 according to the determination by the read / write determination unit 112, and also stores the data stored in the buffer 130. Is read and written in the partial area of the transfer destination determined by the write determination unit 310. The buffer 130 temporarily holds data read from the transfer source, and is erased when the data is further written to the transfer destination. The size of the buffer 130 is 32 bytes (for two pages). <Example of Configuration of Partial Region Determining Unit 211> FIG. 5 is a block diagram showing a detailed example of the configuration of the partial region determining unit 211. As shown in the figure, the partial area determination unit 211 includes a subtractor 211a,
It comprises a comparator 211b and a selector 211c.

The subtractor 211a subtracts the lower 4 bits of REMAIN_R_A_201 from a constant (10H) corresponding to the page size. This subtraction result indicates the number of bytes from REMAIN_R_A_201 to the nearest page boundary, and in this embodiment, is one of four types of values as shown in FIG. The comparator 211b calculates the number of bytes of the subtraction result (A in the figure) and the REMA
Compare the magnitude relation with IN_R_SIZE_202 (B in the figure).

The selector 211c operates as follows: REMAIN_R_SIZE_202
Is larger than the subtraction result, select the subtraction result. Otherwise (that is, if unread data exists only before the nearest page boundary), select RE.
MAIN_R_SIZE_202 is selected, and the selection result is output to the size register 213 as the data size PARTIAL_R_SIZE_213 of the partial area to be read next.

Thus, the data size of one partial area is determined. The start address of the partial area is RE
MAIN_R_A_201 (updated by the address counter 201) is itself. REMAIN_R_A_201 sets the address register 2 as PARTIAL_R_A_212 at the same time that the output of the selector 211c is set in the size register 213.
It is set to 12. <Partial area determination section 311> The partial area determination section 311 also sequentially determines the partial area of the transfer destination by the configuration as shown in FIGS. FIGS. 7 and 8 have substantially the same configuration as the partial area determination unit 211 shown in FIGS. <Description of Operation> The operation of the DMA transfer device 1 according to the first embodiment of the present invention configured as described above will be described.

FIG. 9 is an explanatory diagram showing a state in which DMA transfer is performed between the transfer source and transfer destination storage areas shown in FIGS. In this case, the CPU 2
TRANSFER_SIZE_101 = 28 as a TDMA transfer request
(Byte, decimal), SRC_A_102 = 500C (16
Hexadecimal), DST_A_103 = 6008 (hexadecimal), the addressing mode is set in the register 104 for both the transfer source and the transfer destination in ascending order, and the register 105 is set to 4 bytes as the access size.

In response to this setting, the DMA transfer device 1
Reading from the storage area of the transfer source (SDRAM 4 → buffer 130) is performed for each partial area of (1), (2) and (4) in FIG.
SDRAM 4) is performed in the numerical order for each of the partial areas (3), (5), and (6) in FIG. FIG. 10 is a time chart showing the timing of the DMA transfer of FIG. In the figure, XBRD is a read signal (negative logic), XBWT is a write signal (negative logic), ADR is address, SIZE is access size, D
ATA indicates read / write data, and XACK indicates an acknowledge signal. These signals are input and output between the access control unit 120 and the SDRAM I / F3. Hereinafter, description will be made in order.

(1) In response to the setting of the DMA transfer request, the read management unit 200 sets REMAIN_R_A_201 = 500C (16
), REMAIN_R_SIZE_202 = 28 (decimal) are held as initial values. In addition, the write management unit 300
_W_A_301 = 6008 and REMAIN_W_SIZE_302 = 28 are held as initial values. The read determination unit 210 determines the size of the first partial area based on REMAIN_R_A_201, REMAIN_R_SIZE_202, the addressing mode (in ascending order of address), and the access size of the read management unit 200.
The first partial area is determined to be an area for storing the source word in FIG. 5, and as a result, the address register 212,
The size register 213 has PARTIAL_R_A_212 = 500C
(Hexadecimal), PARTIAL_R_SIZE_213 = 4 (decimal).

In parallel with this, the write decision unit 310
Similarly determines the storage area of the transfer destination word as the first partial area, and stores the PARTIAL_W_
A_312 = 6008 is stored in the size register 313 as PARTIAL_W
_SIZE_313 = 8 is set. After the transfer source partial area and the transfer destination partial area are set in this manner, the access determining unit 110 determines that the data amount of the buffer 130 managed by the buffer managing unit 111 is 0, and thus the read determining unit 210 The access control unit 120 is instructed to read the partial area of the transfer source set by (1).

In response to this instruction, access control unit 120
Reads data from the first partial area of the transfer source (area storing words in the figure) and writes it to the buffer 130 ((1) in FIGS. 9 and 10). (2) After reading of the first partial area (word) of the transfer source is completed, the access control unit 120 reads the read determination unit 2
10, the read determination unit 210 notifies the read management unit 200 of PARTIAL_R_SIZE_213 as the read completed size.

In response to this notification, the read management unit 200
Sets REMAIN_R_A_201 and REMAIN_R_SIZE_202 to 5010
h, updated to 24 (bytes). On the other hand, write decision unit 3
10 does not receive a notification from the access control unit 120 that the writing has been completed, and
L_W_A_312 = 6008 and PARTIAL_W_SIZE_313 = 8 remain.

At this point, since only one word is stored in the buffer 130, the access determining unit 110 determines to read the partial area of the transfer source set by the reading determining unit 210, and instructs the access control unit 110 to that effect. 12
Indicate 0. Upon receiving this instruction, the access control unit 120
Reads data from the second partial area (words) of the transfer source by high-speed page access, and
30 ((2) in FIGS. 9 and 10).

(3) After the reading of the second partial area of the transfer source is completed, the reading management unit 200 and the reading determining unit 21
0 is REMAIN_R_A_201 = 5020 (hexadecimal), REMAIN_R
_SIZE_202 = 8 (decimal), PARTIAL_R_A_212 = 5020
(Hex), PARTIAL_R_SIZE_213 size register 21
Update to 3 = 8. At this point, the access determination unit 110
Is stored in the buffer 130 as 5 words.
The write decision unit 310 decides to read the first partial area of the transfer destination, and instructs the access control unit 120 to that effect.

In response to this instruction, the access control unit 120
Reads data from the buffer 130 and writes the data in the first partial area (word) of the transfer destination by continuous access ((3) in FIGS. 9 and 10). (4) to (6) Hereinafter, similarly, the DMA transfer device 1 sequentially reads the partial area (4), writes the partial area (5), and writes the partial area (6) in FIGS. Do.

As described above, the DMA transfer device 1 performs high-speed page access in (2) reading, (3) writing (4) reading, and (5) writing in FIG. That is, for the transfer source and the transfer destination of the DMA transfer apparatus 1, high-speed page access is performed in units of one page for partial areas other than the first and last partial areas,
In addition, high-speed page access is performed when there are two or more words in the first and last partial areas. Thereby, the DMA transfer device 1 can complete the DMA transfer at a high speed. The storage capacity of the buffer 130 is at least two pages (more precisely, (size of two pages)-(one word)).
Just need.

In the above embodiment, the case where both the transfer source and the transfer destination are the SDRAMs 4 has been described.
4 may be accessed for each partial area. <Second Embodiment> A DMA transfer system according to the present embodiment has a plurality of DMA channels sharing a buffer 130, and when DMA transfer requests of different DMA channels do not conflict, each DMA channel In both cases, access is made for each partial area as in the first embodiment, and when DMA transfer requests conflict (when a DMA transfer request of another DMA channel with higher priority is issued during DMA transfer), DMA transfer is interrupted, and DMA with higher priority
After executing the transfer, the original DMA transfer is restarted. Regarding this interruption, the DMA transfer system writes the data left in the buffer of the currently executing DMA transfer with a low priority to the transfer destination sequentially, irrespective of the page boundary, instead of accessing each partial area, and emptying the buffer. And then DMA
Interrupt transfer.

FIG. 11 is a block diagram showing a configuration of a DMA transfer system according to the second embodiment of the present invention. This DMA transfer system includes a DMA transfer device 6 corresponding to DMA channel 0, a DMA transfer device 7 corresponding to DMA channel 1, a buffer 130, and an access request arbitration unit 1400. It is assumed that the priority of the DMA channel 1 is higher than the priority of the DMA channel 0.

The access request arbitration unit 1400 receives the access request for the DMA channel 0 from the DMA transfer device 6 and
An access request for the DMA channel 1 from the MA transfer device 7 is input, and when the two conflict, they are arbitrated. Here, the access request refers to a request for reading or writing to the partial area or the memory area including the page boundary.

Specifically, access request arbitration unit 1400
Determines whether DMA transfer requests for DMA channels 0 and 1 have not been set in the DMA transfer devices 6 and 7. This determination is made based on, for example, the unwritten data sizes (REMAIN_W_SIZE_1302, REMAIN_W_SIZ) held in the write management unit 1300 and the write management unit 2300, respectively.
E_2302) is 0 or not.

As a result of the determination, the DM of one DMA channel
When the A transfer request is set, the access request arbitration unit 1400 accepts the access request of the channel and outputs the request to the SDRAM I / F3. DMA channel 0 of lower priority during DMA transfer of DMA channel 1
When the DMA transfer request of the DMA channel 0 is set, the access request arbitration unit 1400 accepts the access request of the DMA channel 0 after the DMA transfer of the DMA channel 1 is completed.
Output to SDRAM I / F3.

When a DMA transfer request of the DMA channel 1 having a higher priority is set during the DMA transfer of the DMA channel 0, the access request arbitration unit 1400 outputs an interruption instruction to the DMA transfer device 6 and responds to the interruption instruction. When the DMA transfer device 6 receives a notification that the buffer 130 has become empty, the DMA transfer device 7 receives an access request for the DMA channel 1 and outputs it to the SDRAM I / F 3. As a result, when the inter-D transfer of the DMA channel 1 is completed, a restart instruction is output to the DMA transfer device 6.

The DMA transfer device 6 includes a mode setting unit 110
0, access determination unit 1110, access control unit 112
0, read management unit 1200, read determination unit 121
0, write management unit 1300, write determination unit 1310
Consists of The mode setting unit 1100, the read management unit 1200, the read determination unit 1210, and the write management unit 1300 include the mode setting unit 10 shown in FIG.
0, the read management unit 200, the read determination unit 210, and the write management unit 300. Hereinafter, description of the same components will be omitted, and different points will be mainly described.

The access determining unit 1110 has the same function as the access determining unit 110 shown in FIG. 2, and additionally receives a DMA transfer interruption instruction and a restart instruction from the access request arbitration unit 1400 via the access control unit 1120. It is configured to suspend and resume the DMA being transferred. As shown in FIG. 12, the access determination unit 1110
11, a read / write determination unit 1112.

The buffer management unit 1111 manages the data amount of the buffer 130 in the same manner as the buffer management unit 111 shown in FIG. The read / write deciding unit 1112 is the
The following functions are added as compared with the read / write determination unit 112 shown in FIG. That is, the read / write determination unit 1
112, when receiving an interruption instruction from the access control unit 1120, does not decide to perform read thereafter,
The operation of the partial area determination unit 1311 is temporarily prohibited, the calculated data amount is notified to the buffer management unit 1111 to the write determination unit 1310, and the data amount is set in the size register 1313. Further, the buffer management unit 1111
When the calculated data amount becomes “0”, it notifies the access request arbitration unit 1400 via the access control unit 1120 that the buffer 130 has become empty.

The read / write determining unit 1112
When a restart instruction is received from the access control unit 1120 during the DMA transfer, the operation prohibition of the partial area determination unit 1311 is released, and the same determination as the read / write determination unit 112 illustrated in FIG. 2 is performed. The write determining unit 1310 includes a partial area determining unit 1311, an address register 1312, and a size register 1313 as shown in FIG.

The address register 1312 and the size register 1313 correspond to the address register 312 shown in FIG.
It is the same as the size register 313. However, PARTIAL_
W_SIZE_313 The size register 1313 indicates that the read / write determination unit 1112 has received a read / write
The data amount is directly set by the write determination unit 1112.
Thereby, the buffer 1 is stored in the size register 1313.
The size of the data remaining in 30 is set.

The partial area determination section 1311 is the same as the partial area determination section 311 shown in FIG. 2 except that the operation is temporarily prohibited by the read / write determination section 1112. The access control unit 1120 has an access request arbitration unit 14 in addition to the functions of the access control unit 120 shown in FIG.
It outputs the suspend instruction and the resume instruction input from 00 to the access determining unit 1110, and outputs a notification to the effect that the buffer 130 is empty from the access determining unit 1110 to the access request arbitrating unit 1400.

The DMA transfer device 7 includes a mode setting section 210
0, access determination unit 2110, access control unit 212
0, read management unit 2200, read determination unit 221
0, write management unit 2300, write determination unit 2310
Consists of This configuration is the same as that of the DMA transfer device 1 shown in FIG. <Description of Operation> FIG. 13 is a time chart showing the timing of DMA transfer in the DMA transfer system of the present embodiment. In the figure, XBRD, XBWT, ADR, SIZE, DAT
A and XACK are the same as in FIG. In the figure, the same DMA transfer request as in FIGS. 3, 4, and 10 is set in the DMA transfer device 6 (DMA channel 0), and another DMA transfer request is sent to the DMA transfer device 7 (DMA channel 1) at the timing of T1 in FIG. DMA
This shows the timing when a transfer request is set.

In FIG. 10, (1), (2) and (3) correspond to FIG.
Similarly to the above, the timings of reading (1) and (2) from the transfer source partial area of the DMA channel 0 and writing (3) to the transfer destination partial area are shown. It is assumed that a DMA transfer request of the DMA channel 1 having a high priority is set in the mode setting unit 2100 during execution of writing (3) to the partial area.

Access request arbitration unit 1400 determines that a DMA transfer request for DMA channel 1 is to be set, and
Since the DMA transfer request for the DMA channel 0 has already been set, an interruption instruction is issued to the DMA transfer device 6. In response to the interruption instruction, the read / write determination unit 1112 in the DMA transfer device 6 does not determine that a new read is to be performed when (3) in FIG. It is set in the register 1313 and it is determined that writing is performed. Thus, the access control unit 1
Reference numeral 120 denotes transfer data of DMA channel 0 and buffer 1
All of the data remaining in 30 is written to the transfer destination storage area (FIG. 7 (7)).

After the completion of the writing, the read / write determining unit 1112 notifies the access request arbitrating unit 1400 that the buffer 130 is empty. Upon receiving this notification, the access request arbitration unit 1400 receives the access request for the DMA channel 1 from the DMA transfer device 7 with priority, and outputs it to the SDRAM I / F 3 ((8) in the same figure).

Thereafter, the access request arbitration unit 1400
When it is determined that the DMA data transfer of the DMA channel 1 has been completed, a restart instruction is issued to the DMA transfer device 6. As described above, according to the DMA data transfer system of the present embodiment, there is no need to provide an independent buffer for each channel, and a high-priority DMA transfer request is issued from another channel during data transfer while keeping the circuit size small. , The DMA transfer being executed can be temporarily suspended, and a DMA transfer request with a high priority can be processed first. <Third Embodiment> FIG. 14 is a block diagram showing a configuration of a DMA transfer device 8 according to a third embodiment of the present invention. This figure is different from FIG.
0, an access decision unit 411 instead of the write management unit 300, the access control unit 120, and the buffer 130.
0, an access control unit 4120, and a buffer 4130. Components having the same reference numerals as those in FIG. 2 have the same functions, and thus description thereof will be omitted, and different points will be mainly described below.

The buffer 4130 is a two-port memory that can perform write and read operations in parallel. Buffer 4
The two ports of 130 are connected to different buses.
One port is SDRA via SDRAM I / F3.
The other port is connected to M4 and SDRAM I / F40
03 is connected to the SDRAM 4004. A read operation and a write operation are possible from any of the ports. A write operation from one port and a read operation from the other port are possible at the same time.

The access determining unit 4110 determines whether the buffer 41
The amount of data (the number of bytes) held in 30 is directly acquired from the buffer 4130 and managed. Therefore, every time one word is written and read from / to the buffer 4130, the access determining unit 4110 updates the data amount. Further, the access determining unit 411 determines the size of the partial area (PAR
If a free area equal to or larger than TIAL_R_SIZE_213 exists in the buffer 4130, it is determined that reading is to be performed, and the size of the partial area (PARTIAL_W_S
If data equal to or greater than (IZE_313) exists in the buffer 4130, it is determined that writing is to be performed. The determination of the read of the transfer source partial area and the determination of the write of the transfer destination partial area are not performed alternately but are performed independently. Therefore, the write determination timing is shorter than that in the first embodiment. Be faster.

The access control unit 4120 is connected to the SDRAM 4
And reading from and writing to the SDRAM 4004 are performed in parallel. That is, the access control unit 4120
Performs reading of the partial area determined by the reading determining unit 210, and in parallel with this, the writing determining unit 43
Writing is performed in the transfer destination area based on the address input from the address 10. <Description of Operation> FIG. 15 is a time chart showing the timing of DMA transfer in the DMA transfer device of the present embodiment.

In the figure, the upper half is the access control unit 41
20 are output to the SDRAM I / F3 by:
The lower half shows a signal group output to the SDRAM I / F 4003. The transfer source is 500 of the SDRAM4.
An area of 7 words from address 8, the transfer destination is SDRAM 40
It is an area for 7 words from address 600C of 04.

When comparing FIG. 15 with FIG. 10, in FIG. 15, the start timing of writing to the partial area ((3), (5), (6) in FIG. 15) is advanced. Since the access determining unit 4110 manages the amount of data held in the buffer 4130 in word units, the access determining unit 4110 stores in the buffer 4130 the data corresponding to the data size to be written to the transfer destination partial area. This is because writing can be determined at the time of writing.

As described above, according to the DMA transfer apparatus of the present embodiment, in addition to performing high-speed page access for each partial area, when the transfer source memory and the transfer source memory are connected to different buses, Reading from the source memory and writing to the destination memory can be performed in parallel. <Fourth Embodiment> In the second embodiment, the same memory (SDRAM 4) or a different memory on the same bus is to be transferred for both DMA channels 0 and 1. However, in the present embodiment, different DMAs on different buses are used. D to transfer data to memory
The MA transfer system will be described.

FIG. 16 is a block diagram showing a configuration of a DMA transfer system according to the fourth embodiment of the present invention. 11 is different from FIG. 11 in the second embodiment in that an access request arbitration unit 4400 is provided instead of the access request arbitration unit 1400 and a buffer 4130 is provided instead of the buffer 130. Components having the same reference numerals as those in FIG. 11 have the same functions, and thus description thereof will be omitted, and different points will be mainly described below.

The buffer 4130 is a two-port memory that can perform write and read operations in parallel. Buffer 4
The two ports of 130 are connected to different buses.
One port is SDRA via SDRAM I / F3.
The other port is connected to M4 and SDRAM I / F40
03 is connected to the SDRAM 4004. A read operation and a write operation are possible from any of the ports.

FIG. 17 shows a configuration example of the buffer 4130. The buffer 4130 in FIG.
0a, FIFO 4130b, demultiplexer 4130
It comprises a multiplexer 4130a, a FIFO 4130b, and a demultiplexer 4130c. Ports 0 and 1 are
Both are connected to the multiplexer 4130a and the demultiplexer 4130c. Thus, the buffer 4130 can execute the write operation from one port and the read operation from the other port in parallel.

The access request arbitration unit 4400 sets a transfer request of the high-priority DMA channel 1 during the DMA transfer of the DMA channel 0, and sets the transfer destination memory of the DMA channel 0 and the transfer source memory of the DMA channel 1 to the same. In the case of the same memory or a memory on the same bus, the same operation as the access request arbitration unit 1400 in the second embodiment is performed.

The access request arbitration unit 4400
When a transfer request of another DMA channel is set during MA transfer, and the transfer destination memory and the transfer source memory of the DMA channel are memories on different buses, reading of all transfer data in the DMA transfer from the transfer source is performed. Is completed, and the buffer 4130 starts to read the first partial area of the DMA channel when there is a free area of the read size of the first partial area of the DMA channel.

FIGS. 18A to 18F show a case where the transfer destination of the DMA channel 0 and the transfer source of the DMA channel 1 are different memories. In the figure, SRC0,
DST0 indicates a transfer source storage area and a transfer destination storage area of the DMA channel 0, and SRC1 and DST1 indicate a transfer source storage area and a transfer destination storage area of the DMA channel 1, respectively. The dashed line in FIG.
Of the last partial area of (memory → buffer 413)
0) indicates that the last partial area of the DMA channel 0 is written (from the buffer 4130 to the memory).
Another arrow indicates reading of the first partial area of the DMA channel 1 (memory → buffer 4130). The access request arbitration unit 4400 executes writing and reading to and from two memories connected to different buses in parallel. <Description of Operation> FIG. 19 is a time chart showing an example of operation in the case of FIG.

In the figure, the upper half shows a signal group output from the access request arbitration unit 4400 to the SDRAM I / F3, and the lower half shows a signal group output to the SDRAM I / F 4003. The figure in the figure corresponds to that in FIG. As shown in FIG.
00 indicates that a transfer request of the DMA channel 1 is set during the DMA transfer of the DMA channel 0 and the transfer destination of the DMA channel 0 and the transfer source of the DMA channel 1 are different memories (SDRAMs 4 and 4004). Reading of all the transfer data of the DMA channel 0 from the transfer source is completed (at the time of completion in the figure) and the buffer 413
At the time point when there is a free area corresponding to the read size of the first partial area of the DMA channel 1 at 0 (start time in the figure), the reading of the first partial area of the DMA channel 1 is started. Control.

As described above, the DMA in this embodiment is
According to the transfer system, a DMA transfer request of another DMA channel is set during the DMA transfer, and the transfer destination memory of the preceding transfer and the transfer destination memory of the newly set DMA transfer request are connected to different buses. In this case, the access request arbitration unit 4400 completes reading the last partial area of the preceding DMA transfer, and
When a space corresponding to the size of the first partial area of another DMA channel is generated, the reading of a new DMA transfer request is started, so that the bus use efficiency due to two consecutive DMA transfer requests can be improved. .

In FIGS. 18A to 18F, the DMA
DMA of DMA channel 1 during DMA transfer of channel 0
Although the case where a transfer request is set is shown, the opposite case, that is, the case where a DMA transfer request of DMA channel 0 is set during the DMA transfer of DMA channel 1 is also used.
This is the same as long as the transfer destination memory of the A transfer and the transfer source memory of the new DMA transfer are on different buses.

The DMA transfer system according to the present embodiment may include three or more DMA transfer devices. In that case, the access request arbitration unit detects that the reading of the last partial area has been completed from all the DMA transfer devices, and determines the transfer destination and transfer source memory in each DMA transfer device, and based on them. The control shown in FIG. <Others> In each of the above embodiments, the description has been made on the assumption that both the transfer source and the transfer destination are memories capable of high-speed page access. In this case, only the memory that can be accessed at high speed is accessed for each partial area separated by the page boundary. For example, high-speed page access to the memory can be guaranteed even in the case of DMA transfer between a memory capable of high-speed page access and I / O to which a fixed address is allocated, and the buffer capacity of the buffer 130 or 4130 May be less.

In the first embodiment, the lower four bits of REMAIN_R_A_201 in FIG.
A logic circuit or a table having input / output logic for inputting bits and outputting the same value as the subtraction result may be provided.

[0077]

(1) The DMA transfer device of the present invention is a DMA transfer device for a memory corresponding to high-speed page access, and includes a plurality of partial areas constituting a memory area to be transferred. Determining means for determining each partial area between the beginning of the memory area and the page boundary, between page boundaries, and between the page boundary and the end of the memory area; and performing high-speed page access for each determined partial area. Performing access means.

According to this configuration, when at least one of the transfer source and the transfer destination is a memory capable of high-speed page access, the DMA transfer device can be used for each partial area divided by a page boundary in the memory area to be transferred. In addition, high-speed page access can be guaranteed. As a result, this DM
The A transfer device is compatible with a memory capable of high-speed page access without sacrificing the performance of the memory, and can reduce the idle period of the bus and the DMA transfer time.

(2) The discriminating means holds the start address of the area to be transferred as an initial value, and every time a high-speed page access is made by the access means, the held content is stored in the untransferred area of the memory area to be transferred. Address updating means for updating to the start address of the area of the area, and holding the data size of the area to be transferred as an initial value, and each time the high-speed page access is performed by the access means, the held content is set to A data size updating unit for updating to the untransferred data size, and a partial area from a start address held as an initial value in the address updating unit to a nearest page boundary. Area determination means for determining the next partial area from the top address of the first to the nearest page boundary or the end of the memory area It may be configured with.

According to this configuration, each time the high-speed page access is performed, the determination unit determines the partial area from the head of the memory area to be transferred to the nearest page boundary, and the part from the page boundary to the next page boundary. .., Sequentially determining a plurality of partial areas such as partial areas from a page boundary to the end of the memory area, and performing high-speed page access to each partial area by the access unit. Can be done.

(3) The partial area discriminating means is discriminated by a size discriminating means for discriminating a size from a head address held in the address updating means to a nearest page boundary or the end of the memory area, and a discriminating means. Size holding means for holding the size as the size of the partial area, wherein the access means accesses the partial area of the size held by the size holding means from the start address held by the address updating means at high speed page access. May be configured.

According to this configuration, the partial area determination means
Since the partial area represented by the parameter of the combination of the start address and the size is determined, it is possible to output a parameter suitable for high-speed page access to the access means. (4) The size discriminating means subtracts, from the size of the page area, lower bits representing the relative position in the page area, which are the lower bits of the head address held in the address updating means, thereby obtaining the nearest page boundary. Subtraction means for calculating the size up to, and comparison means for comparing the size calculated by the subtraction means with the untransferred data size held in the data size updating means. Selecting means for selecting, and the size holding means may hold the selection result of the selecting means as the size of the partial area.

According to this configuration, the size determining means can determine the size of the partial area by a simple configuration of subtraction and comparison. (5) Further, the DMA transfer device of the present invention is a DMA transfer device for transferring a memory corresponding to high-speed page access, and includes a plurality of transfer source partial areas constituting a first memory area serving as a transfer source. A first discriminating means for discriminating a plurality of transfer source partial areas separated by any one of a head of the first memory area, a page boundary, and an end of the first memory area and a page boundary; and a transfer destination. A plurality of transfer destination partial areas constituting a second memory area;
Second determining means for determining a plurality of transfer destination partial areas demarcated by any one of a head of a memory area, a page boundary and the end of the second memory area, and a transfer source determined by the first determining means Access means for reading data from the partial area by high-speed page access and writing the read data to the transfer destination partial area determined by the second determination means by high-speed page access.

According to this configuration, in the DMA transfer device, when the transfer source and the transfer destination are high-speed page accessible memories, the DMA transfer device is separated by the page boundary in the first and second memory areas to be transferred. High-speed page access can be guaranteed for each of the transfer source partial area and the transfer destination partial area. As a result, the present DMA transfer device is compatible with a memory capable of high-speed page access without sacrificing the performance of the memory, and can reduce the idle period of the bus and the DMA transfer time.

(6) The first discriminating means holds the start address of the first memory area as an initial value, and changes the held contents according to the access of the access means to the start address of the untransferred area of the first memory area. First address updating means for updating to an address, and holding the data size of the first memory area as an initial value, and storing the held content according to the access of the access means as the untransferred data size of the data size of the first memory area. First data size updating means for updating the first data size;
The transfer source partial area from the start address held as an initial value by the address update unit to the nearest page boundary is determined, and every time the first address update unit updates, the updated page address or the nearest page boundary from the updated start address is updated. A first partial area determining means for determining a next transfer source partial area up to the end of the first memory area;

According to this configuration, each time the high-speed page access is performed, the first determination means determines the transfer source partial area from the head of the first memory area to the nearest page boundary, and the next page boundary from the page boundary. Source partial area up to ...
.. Sequentially determining a plurality of transfer source partial areas such as a transfer source partial area from a page boundary to the end of the first memory area, and an access unit performing high-speed page access to each transfer source partial area. Can be performed in parallel.

(7) The first partial area determining means determines the data size from the start address held by the first address updating means to the nearest page boundary or the end of the first memory area. There is provided a size discriminating means, and a first size holding means for holding the size determined by the first size discriminating means as the size of the transfer source partial area. The access unit reads a transfer source partial area of the size held in the first size holding unit from the head address held in the first address holding unit by high-speed page access.

According to this configuration, the first partial area determining means determines the partial area represented by the parameter of the combination of the start address and the size, and outputs a parameter suitable for high-speed page access to the access means. be able to. (8) The first size discriminating means subtracts, from the size of the page area, lower bits representing the relative position in the page area, which are the lower bits of the start address held in the first address updating means, First subtraction means for calculating the size up to the nearest page boundary; first comparison means for comparing the size calculated by the first subtraction means with the untransferred data size held in the first data size updating means; And a first selecting means for selecting a smaller one as a result of the comparison by the first comparing means, wherein the first size holding means comprises:
The selection result of the first selection means is stored as the size of the partial area.

According to this configuration, the first size determination means can determine the size of the partial area by a simple configuration of subtraction and comparison. (9) The second determination means holds the start address of the second memory area as an initial value, and updates the held content to the start address of an untransferred area in the second memory area in response to access by the access means. A second address updating unit that holds the data size of the second memory area as an initial value, and updates the held content to an untransferred data size of the data size of the second memory area in response to access by the access unit. A second data size updating unit for determining a transfer destination partial area from a start address held as an initial value in the second address updating unit to a nearest page boundary, and each time the second address updating unit updates, And a second partial area determining means for determining a next transfer destination partial area from the start address of the first to the nearest page boundary or the end of the second memory area.

According to this configuration, the second determining means determines the partial area from the head of the second memory area to the nearest page boundary,
Partial area from the page boundary to the next page boundary,
..Simultaneously determining a plurality of partial areas such as partial areas from a page boundary to the end of the memory area and performing high-speed continuous access to each partial area by the access unit in parallel Can be.

(10) The second partial area determination means determines the size from the start address held in the second address update means to the nearest page boundary or the end of the second memory area. And a second size holding unit for holding the size determined by the second size determining unit as the size of the transfer destination partial area, wherein the access unit determines the first address from the first address held in the second address holding unit. The transfer destination partial area of the size held in the two-size holding means is written in the high-speed page access.

According to this configuration, the second partial area determining means includes a partial area from the head of the memory area to be transferred to the nearest page boundary, a partial area from the page boundary to the next page boundary,... It is possible to simultaneously determine a plurality of partial areas, such as partial areas from a page boundary to the end of the memory area, and perform high-speed continuous access to each partial area by the access unit in parallel. .

(11) The second size discriminating means subtracts, from the size of the page area, lower bits representing the relative position in the page area, which are the lower bits of the head address held in the second address updating means. Thus, the second subtraction means for calculating the size up to the nearest page boundary, and the second comparison means for comparing the size calculated by the second subtraction means with the untransferred data size held in the second data size updating means A comparison unit, and a second selection unit that selects a smaller one as a result of the comparison by the second comparison unit, wherein the second size holding unit holds the selection result of the second selection unit as a size of the partial area. .

According to this configuration, the second size determination means can determine the size of the partial area by a simple configuration of subtraction and comparison. (12) Further, the DMA transfer device of the present invention includes a plurality of transfer source partial areas constituting a first memory area serving as a transfer source, wherein a plurality of transfer source partial areas are provided between a head of the first memory area and a page boundary.
First determining means for determining each source partial area between page boundaries and between the page boundary and the end of the first memory area; and a plurality of destination partial areas constituting a second memory area serving as a destination The second memory area, between the beginning and the page boundary, between the page boundaries, and between the page boundary and the second
A second determining means for determining each transfer destination partial area from the end of the memory area; and a high-speed page access to read data from the transfer source partial area determined by the first determination means and store the data in the buffer means. Access means for writing the data stored in the means into the transfer destination partial area determined by the second determination means by high-speed page access.

According to this configuration, when both the transfer source and the transfer destination are memories that can be accessed at a high speed, the DMA transfer device can transfer the transfer source divided by the page boundary in the first memory area of the transfer source. Reading by high-speed page access can be guaranteed for each partial area. In addition, it is possible to guarantee that writing by high-speed page access is performed for each transfer destination partial area delimited by a page boundary in the transfer destination second memory area. As a result, the idle period of the bus can be reduced and the DMA transfer time can be reduced.

(13) The first memory area and the second
The memory area is an area in the same memory or an area in a different memory connected to the same bus, and the access unit determines the size of data held in the buffer unit, the free size of the buffer unit, Read / write determining means for comparing the size of the source partial area with the size of the transfer destination partial area, and determining whether to read the transfer source partial area or write to the transfer destination partial area according to the comparison result; Access control means for reading from the transfer source partial area and writing to the transfer destination partial area in accordance with the determination of the read / write determination means.

(14) The buffer means has at least a capacity obtained by subtracting the memory access size from twice the page area, and the read / write determining means determines the free size of the buffer means by the first determining means. If the data size is equal to or larger than the size of the transfer source partial area, it is determined that reading is to be performed. If the data size acquired by the buffer management means is equal to or larger than the size of the transfer destination partial area determined by the second determination means, Is determined to be written.

According to this configuration, it is possible to guarantee that reading is performed by high-speed page access for each transfer source partial area, and that writing is performed for each transfer destination partial area by high-speed page access. Further, since the storage capacity of the buffer means only needs to have at least a capacity obtained by subtracting the access size of the memory from twice the page area, the DMA transfer can be efficiently realized with a small buffer capacity.

(15) The buffer means is a two-port memory connected to two buses, and the first memory area and the second memory area are areas in a memory connected to different buses. The access means determines whether or not to read from the source partial area according to the size of the data held in the buffer means and the free size of the buffer means. Read / write deciding means for deciding whether or not to write data, and access control means for reading from the source partial area and writing to the destination partial area in accordance with the decision of the read / write deciding means.

According to this configuration, when the first memory area of the transfer source and the second memory area of the transfer destination are areas in a memory connected to different buses, the transfer source portion divided by the page boundary Transfer from the area to the buffer and transfer from the buffer to the transfer destination partial area can be performed in parallel, and DMA transfer can be efficiently realized with a small buffer capacity.

(17) The present invention relates to a DMA transfer system having a plurality of DMA channels having different priorities,
A DMA transfer request is provided for each DMA channel and accepts a DMA transfer request of the corresponding DMA channel.
A: a plurality of accepting means for holding the transfer request; and a plurality of partial areas which are provided for each DMA channel and which constitute the memory area for the transfer target memory area specified in the DMA transfer request of the corresponding DMA channel. A plurality of determination means for determining each partial area between the beginning of the memory area and the page boundary, between the page boundaries, and between the page boundary and the end of the memory area; A plurality of access request generating means for generating an access request for instructing high-speed page access for each partial area determined by the DMA channel determining means;
It includes a buffer unit shared by the MA channel and temporarily holding data to be transferred, and an arbitration unit. Here, when the plurality of accepting units hold the DMA transfer request for only one DMA channel, the arbitrating unit performs access according to the access request corresponding to the DMA channel, and holds the DMA transfer request. If a DMA transfer request for a DMA channel with a higher priority is accepted, the preceding DM
A: Instruct the discriminating means and the access request generating means corresponding to the DMA channel of the transfer request to empty the buffer means and then suspend, and at the time when the buffer means becomes empty, the access request of the high priority DMA channel After completion of the high-priority DMA transfer, an instruction is issued to the determining means and the access request generating means corresponding to the DMA channel of the preceding DMA transfer request to restart the DMA transfer.

According to this configuration, in the memory area to be transferred, for each partial area delimited by the page boundary,
High-speed page access can be guaranteed, and D
If another high-priority DMA transfer request is accepted during the MA transfer, the preceding DMA transfer can be interrupted and switched to a high-priority DMA transfer for execution.

(18) The discriminating means corresponding to the preceding DMA channel discriminates the transfer destination area corresponding to the data held in the buffer means when instructed to stop by the arbitrating means, and The access request generation means corresponding to the channel generates an access request to the transfer destination area determined by the determination means when instructed by the arbitration means to suspend, and the arbitration means performs high-speed page access according to the access request.

According to this configuration, when an interruption is instructed from the arbitration means, the determination means determines the transfer destination area corresponding to the data held in the buffer means, and the access request means determines the transfer destination area determined. Since an access request is generated to write the data in the buffer unit to the area, and the arbitration unit executes the access request, the buffer unit can be emptied immediately after the interruption instruction, and the DMA channel can be shifted to a high priority DMA channel. .

(19) The discriminating means corresponding to the preceding DMA channel, when instructed to resume by the arbitrating means, discriminates a partial area constituting an untransferred area in the memory area to be transferred. According to this configuration, when the restart is instructed, the determination unit restarts the determination of the partial area from the interrupted untransferred area, and thus can immediately return to the original DMA transfer after the restart instruction.

(20) The present invention is also directed to a DMA transfer system having a plurality of DMA channels, wherein the DMA transfer system is provided for each DMA channel.
A plurality of receiving means for receiving a transfer request and holding the DMA transfer request until the completion of the DMA transfer; and a plurality of memory means provided for each DMA channel and for a transfer target memory area specified in the DMA transfer request of the corresponding DMA channel A plurality of determination means for determining a plurality of partial areas constituting an area, wherein each partial area is located between a head of the memory area and a page boundary, between page boundaries, and between a page boundary and an end of the memory area. A plurality of access request generation means provided for each DMA channel and generating an access request for instructing high-speed page access for each partial area determined by the corresponding DMA channel determination means; shared by each DMA channel; It comprises a buffer means which is a two-port memory connected to two buses, and an arbitration means. Here, if the plurality of accepting units hold the DMA transfer request for only one DMA channel, the arbitrating unit performs access according to the access request corresponding to the DMA channel, and the arbitrating unit already holds the DMA transfer request. And DM for other DMA channels
When the A transfer request is accepted and the transfer destination of the preceding DMA transfer and the transfer source of the new DMA transfer are memories on different buses, reading from the transfer source all transfer data being transferred. Is completed, and when the buffer means has a free area of the read size of the first partial area of another DMA channel,
The reading of the first partial area of another DMA channel is started.

According to this configuration, for each partial area delimited by a page boundary in the memory area to be transferred,
High-speed page access can be guaranteed, and after reading of all data from the memory area to the buffer in the preceding DMA transfer, writing of the preceding DMA transfer and writing of a new DMA transfer are executed in parallel. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a main part of an information processing apparatus including a DMA transfer device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a DMA transfer device.

FIG. 3 shows an example of a partial area determined by a reading determination unit.

FIG. 4 shows an example of a partial area determined by a writing determination unit.

FIG. 5 is a block diagram illustrating a detailed configuration example of a partial area determination unit.

FIG. 6 is a diagram showing the result of subtracting the lower 4 bits of the head address of an unread area from a constant corresponding to a page size, and showing the number of bytes from the head address to the nearest page boundary.

FIG. 7 is a block diagram illustrating a detailed configuration example of a partial area determination unit.

FIG. 8 is a diagram showing the result of subtracting the lower 4 bits of the head address of an unwritten area from a constant corresponding to a page size, and showing the number of bytes from the head address to the nearest page boundary.

FIG. 9 is an explanatory diagram showing a state in which DMA transfer is performed between the transfer source and transfer destination storage areas shown in FIGS.

FIG. 10 is a time chart showing the timing of the DMA transfer of FIG. 9;

FIG. 11 is a block diagram illustrating a configuration of a DMA transfer system according to a second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a detailed configuration of an access determination unit.

FIG. 13 is a time chart showing DMA transfer timing in the DMA transfer system.

FIG. 14 is a block diagram illustrating a configuration of a DMA transfer device 8 according to a third embodiment of the present invention.

FIG. 15 is a diagram illustrating a DMA in the DMA transfer device according to the embodiment;
6 is a time chart showing transfer timing.

FIG. 16 is a block diagram illustrating a configuration of a DMA transfer system according to a fourth embodiment of the present invention.

FIG. 17 shows a configuration example of a two-port buffer.

FIG. 18 is an explanatory diagram showing a case where the transfer destination of the DMA channel 0 and the transfer source of the DMA channel 1 are different memories. .

FIG. 19 is a time chart illustrating an operation example in the case of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DMA transfer apparatus 2 CPU 3 SDRAM I / F 4 SDRAM 5 I / O part 100 Mode setting part 101-105 Register 110 Access decision part 111 Buffer management part 112 Read / write decision part 120 Access control part 130 Buffer 200 Read management part 201 address counter 202 data counter 210 read determination section 211 partial area determination section 211a subtractor 211b comparator 211c selector 212 address register 213 size register 300 write management section 301 address counter 302 data counter 310 write determination section 311 partial area determination section 312 address Register 313 Size register 411 Access decision unit

Claims (20)

[Claims] 1. A DMA transfer apparatus for a memory corresponding to a high-speed page access, comprising: a plurality of partial areas constituting a memory area to be transferred; A DMA transfer, comprising: a determination unit that determines a plurality of partial regions separated by any one of the end of the memory region and a page boundary; and an access unit that performs high-speed page access for each of the determined partial regions. apparatus. 2. The method according to claim 1, wherein the determining unit stores, as an initial value, a start address of an area to be transferred, and each time a high-speed page access is performed by the access unit, stores the held content in an untransferred area of the memory area to be transferred. Address updating means for updating to the start address of the area; and holding the data size of the area to be transferred as an initial value, and each time a high-speed page access is performed by the access means, the held content is read out of the data size of the transfer target. A data size updating unit for updating to an untransferred data size; and a partial area from a start address held as an initial value in the address updating unit to a nearest page boundary. A partial area determining means for determining a next partial area from the start address to the nearest page boundary or the end of the memory area. 2. The DMA transfer device according to claim 1, further comprising: 3. The partial area discriminating means determines a size from a head address held in an address updating means to a nearest page boundary or an end of the memory area. Size holding means for holding the size as the size of the partial area, wherein the access means performs high-speed page access to the partial area of the size held in the size holding means from the start address held in the address updating means. 3. The DMA transfer device according to claim 2, wherein: 4. The size discriminating means subtracts, from the size of the page area, lower bits representing the relative position in the page area, which are the lower bits of the head address held in the address updating means, thereby obtaining the most recent bit. Subtraction means for calculating the size up to the page boundary; comparison means for comparing the size calculated by the subtraction means with the untransferred data size held in the data size updating means; 4. The DMA transfer device according to claim 3, further comprising: a selection unit that selects the one of the two areas, wherein the size holding unit holds a selection result of the selection unit as a size of the partial area. 5. A DMA transfer apparatus for transferring data to a memory corresponding to high-speed page access, comprising: a plurality of transfer source partial areas constituting a first memory area serving as a transfer source; First determining means for determining a plurality of transfer source partial areas separated by any one of a head, a page boundary, and the end of the first memory area and a page boundary; and a plurality of parts forming a second memory area serving as a transfer destination A second determination means for determining a plurality of transfer destination partial areas separated by any one of a head of the second memory area, a page boundary, and an end of the second memory area and a page boundary. Data is read out from the transfer source partial area determined by the first determination means by high-speed page access, and the data read into the transfer destination partial area determined by the second determination means is A DMA transfer device comprising: an access unit for writing by fast page access. 6. The first determining means holds a start address of a first memory area as an initial value,
First address updating means for updating the held content to the start address of an untransferred area of the first memory area in response to access by the access means; holding the data size of the first memory area as an initial value;
First data size updating means for updating the held content to the untransferred data size of the data size of the first memory area in response to access by the access means; and a first address held as an initial value by the first address updating means. From the start address after the update to the nearest page boundary or the end of the first memory area every time the first address updating means updates the transfer source partial area from the transfer source partial area to the nearest page boundary or the end of the first memory area. 6. The DMA transfer device according to claim 5, further comprising: a first partial area determination unit that determines a partial area. 7. The first size discriminating means, wherein the first partial area discriminating means discriminates a data size from a start address held in a first address updating means to a nearest page boundary or an end of the first memory area. And a first size holding means for holding the size determined by the first size determination means as the size of the transfer source partial area, wherein the access means determines a first address from the first address held by the first address holding means. 7. The DMA transfer apparatus according to claim 6, wherein the transfer source partial area of the size stored in the one-size storage unit is read by high-speed page access. 8. The first size discriminating means subtracts, from the size of the page area, lower bits representing a relative position in the page area, which are lower bits of the start address held by the first address updating means. A first subtraction means for calculating the size up to the nearest page boundary, and a first comparison for comparing the size calculated by the first subtraction means with the untransferred data size held in the first data size updating means. Means, and a first selection means for selecting a smaller one as a result of the comparison by the first comparison means, wherein the first size holding means holds the selection result of the first selection means as a size of the partial area. 8. The DMA transfer device according to claim 7, wherein: 9. The method according to claim 9, wherein the second determination unit holds a start address of the second memory area as an initial value,
Second address updating means for updating the held content to the start address of an untransferred area in the second memory area in response to access by the access means; holding the data size of the second memory area as an initial value;
Second data size updating means for updating the held content to the untransferred data size of the data size of the second memory area in response to access by the access means; and a start address held as an initial value by the second address updating means. From the starting address after the update to the nearest page boundary or the end of the second memory area each time the second address updating means updates the transfer destination partial area from 9. The DMA transfer device according to claim 8, further comprising a second partial area determination unit that determines a partial area. 10. The second partial area discriminating means, a second size discriminating means for discriminating a size from a start address held in a second address updating means to a nearest page boundary or an end of the second memory area. And a second size holding means for holding the size determined by the second size determining means as the size of the transfer destination partial area, wherein the access means obtains a second address from the head address held by the second address holding means. 10. The DMA transfer device according to claim 9, wherein the transfer destination partial area of the size held in the size holding means is written in the high-speed page access. 11. The second size discriminating means subtracts, from the size of the page area, lower bits representing a relative position in the page area, which are lower bits of a head address held in the second address updating means. A second subtraction means for calculating the size up to the nearest page boundary, and a second comparison for comparing the size calculated by the second subtraction means with the untransferred data size held in the second data size updating means. Means, and a second selecting means for selecting a smaller one as a result of the comparison by the second comparing means, wherein the second size holding means holds the selection result of the second selecting means as a size of the partial area. The DMA transfer device according to claim 10, wherein: 12. A DMA transfer device for transferring a memory corresponding to a high-speed page access to a plurality of transfer source partial areas constituting a first memory area serving as a transfer source, wherein the first memory area First determining means for determining a plurality of transfer source partial areas separated by any one of a head, a page boundary, and the end of the first memory area and a page boundary; and a plurality of parts forming a second memory area serving as a transfer destination A second determination means for determining a plurality of transfer destination partial areas separated by any one of a head of the second memory area, a page boundary, and an end of the second memory area and a page boundary. Data is read from the transfer source partial area determined by the first determination means by high-speed page access, stored in the buffer means, and the data stored in the buffer means is read by the second determination means. An access means for writing the transfer destination partial area determined by the stage by high-speed page access. 13. The first memory area and the second memory area are areas in the same memory or areas in different memories connected to the same bus, and the access unit is held in a buffer unit. The size of the data and the free size of the buffer means are compared with the size of the transfer source partial area and the size of the transfer destination partial area, and the reading of the transfer source partial area and the writing of the transfer destination partial area are performed according to the comparison result. Read / write determining means for determining which one to perform, and access control means for performing reading from the source partial area and writing to the destination partial area in accordance with the determination of the read / write determining means. 13. The DMA transfer device according to claim 12, wherein: 14. The buffer unit according to claim 1, wherein the buffer unit is a page area.
The read / write determining means has at least a capacity obtained by subtracting one access size of the memory from the double, and the read / write deciding means has a vacant size of the buffer means equal to or larger than the size of the transfer source partial area determined by the first determining means. Determines that reading is to be performed, and determines that writing is to be performed if the data size acquired by the buffer management unit is equal to or larger than the size of the transfer destination partial area determined by the second determination unit. 14. The DMA transfer device according to claim 13, wherein: 15. The buffer means is a two-port memory connected to two buses, wherein the first memory area and the second memory area are areas in a memory connected to different buses. The means determines whether or not to read from the transfer source partial area according to the size of the data held in the buffer means and the free size of the buffer means. Read / write determining means for determining whether or not to perform writing; and access control means for performing reading from the source partial area and writing to the destination partial area in accordance with the determination by the read / write determining means. 13. The DMA transfer device according to claim 12, wherein: 16. The read / write determining means determines that reading is to be performed when the empty size of the buffer means is equal to or larger than the size of the transfer source partial area determined by the first determining means. 16. The DMA according to claim 15, wherein when the data size acquired by the buffer management unit is equal to or larger than the size of the transfer destination partial area determined by the second determination unit, it is determined that writing is performed.
Transfer device. 17. A DMA transfer system having a plurality of DMA channels having different priorities, provided for each DMA channel, receiving a DMA transfer request of a corresponding DMA channel, and performing a DM transfer until completion of the DMA transfer.
A: a plurality of accepting means for holding the transfer request; and a plurality of partial areas which are provided for each DMA channel and which constitute the memory area of the transfer target memory area specified in the DMA transfer request of the corresponding DMA channel. A plurality of discriminating means for discriminating a plurality of partial areas demarcated by any one of the top of the memory area, the page boundary, and the end of the memory area and the page boundary; A plurality of access request generation means for generating an access request for instructing high-speed page access for each partial area determined by the determination means; and a buffer means shared by each DMA channel for temporarily holding data to be transferred. A plurality of accepting means hold a DMA transfer request for only one DMA channel. In this case, access is performed in accordance with the access request corresponding to the DMA channel. If the DMA transfer request is held and a DMA transfer request for a high-priority DMA channel is accepted, the preceding DMA transfer is performed. Instructing the determination means and the access request generation means corresponding to the requested DMA channel to empty the buffer means and then suspending the access, and when the buffer means becomes empty, access is performed according to the access request of the high-priority DMA channel. And arbitration means for instructing the access request generation means to resume the DMA transfer to the determination means corresponding to the DMA channel of the preceding DMA transfer request after the completion of the high-priority DMA transfer. DMA transfer system. 18. A determination means corresponding to the preceding DMA channel, when instructed to stop by the arbitration means, determines a transfer destination area corresponding to data held in a buffer means, and The access request generation means corresponding to the above, when instructed by the arbitration means to interrupt, generates an access request to the transfer destination area determined by the determination means, the arbitration means performs high-speed page access according to the access request 18. The DMA according to claim 17, wherein:
Transfer system. 19. A method according to claim 19, wherein the determining means corresponding to the preceding DMA channel determines a partial area constituting an untransferred area in the memory area to be transferred when instructed to resume by the arbitrating means. 19. The DMA according to claim 18,
Transfer system. 20. A DMA having a plurality of DMA channels.
A transfer system, provided for each DMA channel, for receiving a DMA transfer request of a corresponding DMA channel,
A plurality of accepting means for holding a DMA transfer request until the completion of the A transfer; and a plurality of memory means provided for each DMA channel and constituting a memory area to be transferred specified in the DMA transfer request of the corresponding DMA channel. A plurality of determination means for determining each partial area between the beginning of the memory area and the page boundary, between the page boundaries, and between the page boundary and the end of the memory area; A plurality of access request generating means for generating an access request for instructing high-speed page access for each partial area determined by the corresponding DMA channel determining means; shared by each DMA channel and connected to two buses Buffer means, which is a two-port memory, and a plurality of receiving means, each of which has a D When the MA transfer request is held, the access is performed according to the access request corresponding to the DMA channel, and the DMA transfer request is already held and another DM transfer request is held.
When a DMA transfer request for the A channel is accepted and the transfer destination of the preceding DMA transfer and the transfer source of the new DMA transfer are memories on different buses, the transfer source for all transfer data being transferred is When the reading from the first DMA is completed and the buffer means has a free area of the read size of the first partial area of the other DMA channel, the first partial area of the other DMA channel is read. Arbitration means for starting the DMA transfer.