JP4536189B2 - DMA transfer apparatus and DMA transfer system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
DMA data transfer apparatus for guaranteeing continuous access in page units for a memory capable of high-speed page access
[0002]
[Prior art]
A conventional DMA data transfer apparatus transfers data at high speed between a memory and a memory or between a memory and an input / output device.
In the transfer between memories connected to the same bus and the transfer between different storage areas of the same memory, the DMA data transfer apparatus temporarily holds the data read from the transfer source storage area in a buffer in the DMA data transfer apparatus. Further, DMA data transfer is performed by writing from the buffer to the storage area of the transfer destination. This buffer has a capacity equal to or larger than the size of one access to the memory. Conventional typical DMA data transfer performs reading from the transfer source, storing in the buffer, and writing from the buffer to the transfer destination storage area for each data of one access size. This enables DMA data transfer with the minimum necessary buffer size.
[0003]
If the buffer size is a multiple of the access size, the DMA transfer device reads the data from the transfer source until it reaches the buffer size, stores it in the buffer, and transfers the data for the buffer size from the buffer. Write to the destination storage area. In this case, reading and writing are performed in units of buffer size.
[0004]
[Problems to be solved by the invention]
In recent years, SDRAM capable of high-speed page access has been used as a main memory. However, when this SDRAM is a transfer target, there is a problem that the high-speed performance of the SDRAM is sacrificed and its usefulness cannot be fully utilized. It was. This is because the conventional DMA transfer apparatus accesses data regardless of page boundaries in reading from the transfer source to the buffer and writing from the buffer to the transfer destination.
[0005]
An object of the present invention is to provide a useful DMA transfer device that is compatible with a memory capable of high-speed page access and that realizes high-speed DMA transfer without sacrificing performance.
[0006]
[Means for Solving the Problems]
The DMA transfer apparatus according to the present invention is a DMA transfer apparatus for a memory corresponding to high-speed page access, and includes a plurality of partial areas constituting a memory area to be transferred, the top of the memory area and a page A discriminating unit that discriminates each partial region between the borders, between page borders, and between the page border and the end of the memory region; and an access unit that performs high-speed page access for each discriminated partial region.
[0007]
Further, the DMA transfer apparatus of the present invention is a plurality of transfer source partial areas constituting the first memory area as a transfer source, and is between the head of the first memory area and the page boundary, between the page boundaries and between the pages. First discriminating means for discriminating each transfer source partial area between a boundary and the end of the first memory area; and a plurality of transfer destination partial areas constituting a second memory area serving as a transfer destination, A second discriminating means for discriminating each transfer destination partial area between the top of the two memory areas and the page boundary, between the page boundaries and between the page boundary and the end of the second memory area; The data is read from the transfer source partial area by high-speed page access and stored in the buffer means, and the data stored in the buffer means is written to the transfer destination partial area determined by the second determination means by high-speed page access. And a non-access means.
[0008]
The DMA transfer system of the present invention is a DMA transfer system having a plurality of DMA channels having different priorities, provided for each DMA channel, accepting a DMA transfer request for the corresponding DMA channel, and completing the DMA transfer. A plurality of receiving means for holding a DMA transfer request and a transfer target memory area provided for each DMA channel and designated in the DMA transfer request of the corresponding DMA channel are a plurality of partial areas constituting the memory area. A plurality of discriminating means for discriminating each partial area between the top of the memory area and the page boundary, between page boundaries and between the page boundary and the end of the memory area, An access request for instructing high-speed page access is generated for each partial area determined by the DMA channel determination means. To include a plurality of access request generating means, is shared by each DMA channel, a buffer means for temporarily holding data to be transferred, and arbitration means. Here, when a plurality of accepting means holds a DMA transfer request for only one DMA channel, the arbitrating means performs access according to the access request corresponding to the DMA channel, and holds the DMA transfer request. If a DMA transfer request for a DMA channel with a high priority is accepted, the buffer means is emptied for the determination means and the access request generation means corresponding to the DMA channel of the preceding DMA transfer request. When the buffer means becomes empty, access is performed in accordance with the access request for the high priority DMA channel, and after completion of the high priority DMA transfer, the DMA channel corresponding to the preceding DMA transfer request is handled. Instruct the discriminating means and access request generating means to resume DMA transfer. To.
[0009]
The DMA transfer system according to the present invention is a DMA transfer system having a plurality of DMA channels, and is provided for each DMA channel. The DMA transfer system accepts a DMA transfer request of the corresponding DMA channel, and makes a DMA transfer request until the DMA transfer is completed. A plurality of accepting means for holding, and a plurality of partial areas constituting the memory area, each of which is provided for each DMA channel and which is a transfer target memory area specified in the DMA transfer request of the corresponding DMA channel, A plurality of discriminating means for discriminating each partial area between the head of the area and the page boundary, between the page boundary and between the page boundary and the end of the memory area, and provided for each DMA channel, A plurality of applications that generate an access request for instructing high-speed page access for each partial area determined by the determining means. Seth request generating means, each DMA channel is shared, two-port memory connected to the two buses is there Buffer means and arbitration means are provided. Here, when a plurality of accepting means holds a DMA transfer request for only one DMA channel, the arbitrating means performs access according to the access request corresponding to the DMA channel, and already holds the DMA transfer request. If a transfer request for another DMA channel is accepted and the transfer destination of the previous DMA transfer and the transfer source of the new DMA transfer are memories on different buses, the transfer is in progress. When the reading from the transfer source for all the transfer data of the other DMA channel is completed and there is a free area corresponding to the read size of the first partial area of the other DMA channel in the buffer means, the other DMA Start reading the first partial region of the channel.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
<First Embodiment>
<Overall configuration>
FIG. 1 is a block diagram showing a configuration of a main part of an information processing apparatus including a DMA (Direct Memory Access) transfer apparatus according to the first embodiment of the present invention. The information processing apparatus shown in the figure includes, for example, a digital satellite broadcast receiving apparatus (hereinafter referred to as STB (Set Top Box)), an optical disk recording / reproducing apparatus such as a DVD (Digital Video / Versatile Disk), DVD-RAM, etc. It is used for control and includes an I / O unit 5, SDRAM 4, SDRAM I / F 3, CPU 2, and DMA transfer device 1.
[0011]
The I / O unit 5 inputs / outputs MPEG streams and inputs key data from a remote controller (not shown).
The SDRAM 4 is a memory that supports high-speed page access. High-speed page access means high-speed access to a continuous storage area called a predetermined page. And is there. In the present embodiment, the SDRAM 4 has a data width of 32 bits (hereinafter, 32 bits are defined as one word), and one page is a continuous storage area every 4 words (16 bytes). Here, the size of one page can be set to other sizes such as 2 words and 8 words, but it is preferable to set the size to the same as the cache fill size (unit for updating the cache memory) of the CPU 2. This is because the configuration of the SDRAM I / F 3 can be shared between the CPU 2 and the DMA transfer apparatus 1 and can be simplified. In this embodiment, it is assumed that the cache fill size is 16 bytes.
[0012]
The SDRAM I / F 3 accesses the SDRAM 4 by converting the access signal group (address, data, various control signals) sent from the DMA transfer device 1 and the CPU 2 onto the bus to the input / output specifications of the SDRAM 4.
The CPU 2 has an internal cache memory, controls the entire information processing apparatus, and sets a DMA transfer request to the DMA transfer apparatus 1. DMA transfer in FIG. 1 includes transfer from SDRAM 4 to SDRAM 4 (that is, between different storage areas in SDRAM 4), transfer between SDRAM 4 and I / O unit 5, and between SDRAM 4 and MPEG decoder (not shown). There is a transfer etc.
[0013]
The DMA transfer device 1 performs DMA transfer between different storage areas of the SDRAM 4, between the SDRAM 4 and the I / O unit 5, and the like. At that time, when the transfer source or transfer destination is SDRAM 4, the DMA transfer apparatus 1 determines a partial area delimited by the page boundary existing in the transfer target area in the SDRAM 4, and for each partial area, Access is performed continuously by high-speed page access.
<Configuration of DMA transfer device 1>
FIG. 2 is a block diagram showing a configuration of the DMA transfer apparatus 1. As shown in the figure, the DMA transfer apparatus 1 includes a mode setting unit 100, a read management unit 200, a read determination unit 210, a write management unit 300, a write determination unit 310, an access determination unit 110, an access control unit 120, and a buffer 130. Configured. The values in parentheses given to the arrow lines in the figure mean that the contents of the registers of the corresponding code are input / output.
[0014]
The mode setting unit 100 includes registers 101 to 105 that hold DMA transfer requests set by the CPU 2. Here, the DMA transfer request includes various parameters for requesting DMA transfer between different areas of the SDRAM 4 or between the SDRAM 4 and the I / O unit 5 without using the CPU 2. Various parameters include (1) DMA transfer size, (2) read start address, (3) write start address, (4) addressing mode, and (5) access size. Here, (1) “transfer size” indicates the total data length (assumed to be the number of bytes) to be DMA transferred. (2) “Read start address” indicates the start address of the data to be transferred stored in the transfer source (SDRAM 4, I / O unit 5, etc.). (3) “Write start address” indicates the start address of the transfer destination (SDRAM 4, I / O unit 5, etc.). (4) “Addressing mode” indicates whether to access each of the transfer source and transfer destination in ascending order of addresses or access with fixed addresses. (5) “Access size” indicates the data size to be read or written in one access for each of the transfer source and transfer destination. In the present embodiment, it is assumed that the access size is 32 bits.
[0015]
The registers 101 to 105 sequentially hold a transfer size, a read start address, a write start address, an addressing mode, and an access size, and are cleared after completion of the DMA transfer by the DMA transfer request. Hereinafter, the contents held in the registers 101 to 103 are abbreviated as TRANSFER_SIZE_101, SRC_A_102, and DST_A_103.
The read management unit 200 manages the start address of unread data (hereinafter abbreviated as REMAIN_R_A_201) and the unread data size (hereinafter abbreviated as REMAIN_R_SIZE_202) in the transfer source recording area specified by TRANSFER_SIZE_101 and SRC_A_10. To do. Therefore, the read management unit 200 includes an address counter 201 and a data counter 202.
[0016]
The address counter 201 holds SRC_A_102 input from the register 102 as an initial value of REMAIN_R_A_201 when a DMA transfer request is issued to the mode setting unit 100, and further reads when the addressing mode is in ascending order of addresses. Each time the notification about the number of bytes of the partial area that has been completed is received from the read determining unit 210, the notified number of bytes is added to REMAIN_R_A_201, thereby updating REMAIN_R_A_201 to indicate the start address of the next partial area. The number of bytes of the partial area that has been read is notified from the read determination section 210 when the data in the transfer source partial area is read by the access control section 120 and stored in the buffer 130. On the other hand, when the addressing mode is fixed, the address counter 201 does not update during DMA transfer while storing SRC_A_102 input from the register 102.
[0017]
When a DMA transfer request is issued to the mode setting unit 100, the data counter 202 holds TRANSFER_SIZE_101 as an initial value of REMAIN_R_SIZE_202, and further notifies the read determination unit 210 of the number of bytes in the partial area that has been read. Every time it is updated by subtracting the number of bytes from REMAIN_R_SIZE_202. As a result, REMAIN_R_SIZE_202 represents the unread data size in TRANSFER_SIZE_101.
[0018]
The read determination unit 210 includes a partial area determination unit 211, an address register 212, and a size register 213. A storage area for unread data specified by REMAIN_R_A_201 and REMAIN_R_SIZE_202 after a DMA transfer request is issued to the mode setting unit 100 The partial area delimited by the page boundary is determined, the start address (hereinafter abbreviated as PARTIAL_R_A_212) for each determined partial area is set in the address register 212, and the determined partial area size (PARTIAL_R_SIZE_213) is set in the size register 213 To do. After the setting, upon receiving notification from the access control unit 120 that reading of the partial area and storage in the buffer 130 have been completed, the read determination unit 210 sets PARTIAL_R_SIZE_213 of the size register 213 to the size of the partial area that has been read. Is read out to the read management unit 200 and the next partial area is determined and set in the address register 212 and the size register 213 in the same manner as described above.
[0019]
FIG. 3 shows an example of a partial region that is discriminated by the read determination unit 210. This figure shows the storage area of the transfer source in the SDRAM 4. This transfer source storage area is a 28 byte storage area starting from address 500C (hexadecimal), that is, SRC_A_102 is address 500C, and TRANSFER_SIZE_101 is 28 bytes (7 words: (1) to (7) in the figure). It shall be. Since the page size of the SDRAM 4 is 16 bytes (4 words), data to be transferred (seven words (1) to (7) in the figure) is stored across three pages.
[0020]
In this case, the read determination unit 210 sequentially determines the next first to third partial areas. The first partial area is a storage area of the word (1) represented by (PARTIAL_R_A_212, PARTIAL_R_SIZE_213) = (500C, 4). The second partial area is a storage area for the words (2) to (5) represented by (5010, 16). The third partial area is a storage area for the word (6) (7) represented by (5020,8). As described above, each partial area does not include a page boundary, and thus is suitable for high-speed page access.
[0021]
The write management unit 300 manages the start address of the unwritten area (abbreviated as REMAIN_W_A_301) and the unwritten data size (abbreviated as REMAIN_W_SIZE_302) in the transfer destination recording area specified by TRANSFER_SIZE_101 and DST_A_103. Therefore, the write management unit 300 includes an address counter 301 and a data counter 302.
[0022]
The address counter 301 receives DST_A_103 input from the register 103 when a DMA transfer request is issued to the mode setting unit 100. The first When the addressing mode is in ascending order of address, and the notification about the number of bytes in the partial area that has been written is received from the write determination unit 310, the notified number of bytes is added to REMAIN_W_A_301. By doing so, REMAIN_W_A_301 is updated so as to indicate the head address of the next partial area. The number of bytes of the partial area for which the above writing has been completed is notified from the write determination section 310 when data is written to the transfer destination partial area by the access control section 120. On the other hand, when the addressing mode is fixed, the address counter 301 does not update during DMA transfer while storing DST_A_103 input from the register 103.
[0023]
When a DMA transfer request is issued to the mode setting unit 100, the data counter 302 holds TRANSFER_SIZE_101 as an initial value of REMAIN_W_SIZE_302, and further notifies the write determination unit 310 of the number of bytes in the partial area that has been written. Every time it is updated by subtracting the number of bytes from REMAIN_W_SIZE_302. As a result, REMAIN_R_SIZE_202 represents the unread data size in TRANSFER_SIZE_101.
[0024]
The write determination unit 310 includes a partial area determination unit 311, an address register 312, and a size register 313, and after a DMA transfer request is issued to the mode setting unit 100, in the unwritten storage area specified by REMAIN_W_A_301 and REMAIN_W_SIZE_302 The partial area divided by the page boundary is discriminated, and the start address (hereinafter abbreviated as PARTIAL_W_A_312) for each discriminated partial area is set in the address register 312 and the size of the discriminated partial area (hereinafter abbreviated as PARTIAL_W_SIZE_313) is set in the size register 313 To do. After the setting, when the notification indicating that the writing to the partial area is completed is received from the access control unit 120, the PARTIAL_W_SIZE_313 of the size register 313 is notified to the writing management unit 300 as the size of the writing completed, and again in the same manner as above. The next partial area is discriminated and the next partial area is set in the address register 312 and the size register 313.
[0025]
FIG. 4 shows an example of a partial area determined by the writing determination unit 310. This figure shows a part of the transfer destination storage area in the SDRAM 4. This transfer destination storage area is a 28-byte storage area starting from address 6008, that is, DST_A_103 is address 6008 (hexadecimal), and TRANSFER_SIZE_101 is 28 bytes (7 words: (1) to (7) in the figure). Shall. Since the page size of the SDRAM 4 is 16 bytes (4 words), the storage area of the transfer destination ((1) to (7) in the figure) is stored across three pages.
[0026]
In this case, the writing determination unit 310 sequentially determines the next fourth to sixth partial areas. The fourth partial area is a storage area of the words (1) and (2) represented by (PARTIAL_W_A_302, PARTIAL_W_SIZE_303) = (6008,8). The fifth partial area is a storage area for the words (3) to (6) represented by (6010, 16). The sixth partial area is a storage area for the word (7) represented by (6020, 4). As described above, each partial area does not include a page boundary, and thus is suitable for high-speed page access.
[0027]
The access determination unit 110 includes a buffer management unit 111 and a read / write determination unit 112, and reads from the transfer source partial area determined by the read determination unit 210 and stores it in the buffer 130 (hereinafter abbreviated as read). The data stored in the buffer 130 indicates which of the data stored in the buffer 130 is to be executed by the access control unit 120 among the writing to the partial area of the transfer destination determined by the write determination unit 310 (hereinafter abbreviated as “write”). Decide according to the amount.
[0028]
The buffer management unit 111 receives REMAIN_R_SIZE_202 and REMAIN_W_SIZE_302, and calculates the amount of data temporarily held in the buffer 130 by subtracting REMAIN_W_SIZE_302 from REMAIN_R_SIZE_202.
When the amount of data calculated by the buffer management unit 111 is smaller than PARTIAL_W_SIZE_313, the read / write determination unit 112 determines to cause the access control unit 120 to perform reading, otherwise, the write control is performed. It is determined to be executed by the unit 120.
[0029]
In accordance with the determination by the read / write determination unit 112, the access control unit 120 reads the data from the transfer source partial area by the read determination unit 210 and stores it in the buffer 130, and also reads the data stored in the buffer 130. Writing to the partial area of the transfer destination determined by the writing determination unit 310 is performed.
The buffer 130 temporarily holds data read from the transfer source and is erased when it is written to the transfer destination. The size of the buffer 130 is 32 bytes (for two pages).
<Configuration Example of Partial Area Determination Unit 211>
FIG. 5 is a block diagram illustrating a detailed configuration example of the partial region determination unit 211. As shown in the figure, the partial area determination unit 211 includes a subtractor 211a, a comparator 211b, and a selector 211c.
[0030]
The subtractor 211a subtracts the lower 4 bits of REMAIN_R_A_201 from a constant (10H) corresponding to the page size. This subtraction result means the number of bytes from REMAIN_R_A_201 to the nearest page boundary, and in this embodiment, it is one of four types of values as shown in FIG.
The comparator 211b compares the number of bytes of the subtraction result (A in the figure) with the magnitude relationship between REMAIN_R_SIZE_202 (B in the figure).
[0031]
The selector 211c selects the subtraction result when REMAIN_R_SIZE_202 is larger than the subtraction result, and selects REMAIN_R_SIZE_202 otherwise (that is, when unread data exists only before the most recent page boundary). The selection result is output to the size register 213 as the data size PARTIAL_R_SIZE_213 of the partial area to be read next.
[0032]
In this way, the data size of one partial area is determined. The start address of the partial area is REMAIN_R_A_201 (updated by the address counter 201) itself. REMAIN_R_A_201 is set in the address register 212 as PARTIAL_R_A_212 at the same time that the output of the selector 211c is set in the size register 213.
<Partial region determination unit 311>
The partial area determination unit 311 also sequentially determines the partial area of the transfer destination with the configuration as shown in FIGS. 7 and 8 have substantially the same configuration as the partial region determination unit 211 shown in FIGS.
<Description of operation>
The operation of the DMA transfer apparatus 1 configured as above according to the first embodiment of the present invention will be described.
[0033]
FIG. 9 is an explanatory diagram showing a state of DMA transfer between the transfer source and transfer destination storage areas shown in FIGS. In this case, the CPU 2 sets TRANSFER_SIZE_101 = 28 (byte, decimal), SRC_A_102 = 500 C (hexadecimal), DST_A_103 = 6008 (hexadecimal) as a TDMA transfer request in the mode setting unit 100, and the addressing is set in the register 104. As the mode, the address ascending order is set for both the transfer source and transfer destination, and the access size is set in the register 105 (4 bytes).
[0034]
In response to this setting, the DMA transfer device 1 reads out data from the transfer source storage area (SDRAM 4 → buffer 130) for each of the partial areas (1), (2), and (4) in FIG. Write (buffer 130 → SDRAM 4) is performed in numerical order for each of the partial areas (3), (5), and (6) in FIG.
FIG. 10 is a time chart showing the timing of DMA transfer in FIG. In the figure, XBRD is a read signal (negative logic), XBWT is a write signal (negative logic), ADR is an address, SIZE is an access size, DATA is read / write data, and XACK is an acknowledge signal. These signals are input / output between the access control unit 120 and the SDRAM I / F 3. In the following, description will be given in order.
[0035]
(1) By setting the DMA transfer request, the read management unit 200 holds REMAIN_R_A_201 = 500C (hexadecimal) and REMAIN_R_SIZE_202 = 28 (decimal) as initial values. Also, the write management unit 300 holds REMAIN_W_A_301 = 6008 and REMAIN_W_SIZE_302 = 28 as initial values.
The read determination unit 210 determines the size of the first partial area based on REMAIN_R_A_201, REMAIN_R_SIZE_202, the addressing mode (address ascending order), and the access size of the read management unit 200. The first partial area is determined as an area for storing the transfer source word (1) in FIG. 5. As a result, the address register 212 and the size register 213 have PARTIAL_R_A_212 = 500C (hexadecimal), PARTIAL_R_SIZE_213 = 4 (decimal). ).
[0036]
In parallel with this, the write determination unit 310 similarly determines that the storage area of the transfer destination word (1) (2) is the first partial area, sets PARTIAL_W_A_312 = 6008 in the address register 312, and stores it in the size register 313. PARTIAL_W_SIZE_313 = 8 is set.
After the transfer source partial area and the transfer destination partial area are set in this way, the access determination unit 110 reads 0 because the data amount of the buffer 130 managed by the buffer management unit 111 is 0. The access control unit 120 is instructed to read the transfer source partial area set by.
[0037]
In response to this instruction, the access control unit 120 reads data from the first partial area of the transfer source (area storing the word (1) in the figure) and writes it into the buffer 130 ((1) in FIGS. 9 and 10). .
(2) After completing the reading of the first partial area (word {circle around (1)}) of the transfer source, the access control unit 120 notifies the reading determining unit 210 that the reading has been completed, and the reading determining unit 210 sets PARTIAL_R_SIZE_213. The read management unit 200 is notified of the read completion size.
[0038]
With this notification, the read management unit 200 updates REMAIN_R_A_201 and REMAIN_R_SIZE_202 to 5010h and 24 (bytes). On the other hand, since the write determination unit 310 has not received a notification from the access control unit 120 that the write has been completed, PARTIAL_W_A_312 = 6008 and PARTIAL_W_SIZE_313 = 8 remain unchanged.
[0039]
At this time, since only one word is stored in the buffer 130, the access determination unit 110 determines to read the transfer source partial area set by the read determination unit 210, and instructs the access control unit 120 to that effect. To do.
In response to this instruction, the access control unit 120 reads the data from the second partial area (words {circle around (2)} to {circle around (5)}) of the transfer source by high-speed page access and writes it to the buffer 130 (in FIGS. 9 and 10). 2)).
[0040]
(3) After the reading of the second partial area of the transfer source is completed, the read management unit 200 and the read determination unit 210 have REMAIN_R_A_201 = 5020 (hexadecimal), REMAIN_R_SIZE_202 = 8 (decimal), PARTIAL_R_A_212 = 5020 (hexadecimal) , PARTIAL_R_SIZE_213 The size register 213 is updated to 8 = 8.
At this point, the access determination unit 110 stores 5 words in the buffer 130. Have Therefore, it is determined to read the first partial area of the transfer destination set by the write determination unit 310, and the access control unit 120 is instructed to that effect.
[0041]
In response to this instruction, the access control unit 120 reads the data from the buffer 130 and writes the data to the first partial area (word (1) (2)) of the transfer destination by continuous access ((3) in FIGS. 9 and 10).
(4) to (6) Hereinafter, similarly, the DMA transfer apparatus 1 sequentially reads the partial area (4), the partial area (5), and the (6) partial area in FIG. 9 and FIG. Do.
[0042]
As described above, the DMA transfer apparatus 1 performs high-speed page access in the reading (2), the writing (3) (4), and the writing (5) in FIG.
That is, for each transfer source and transfer destination of the DMA transfer apparatus 1, high-speed page access is performed in units of one page for partial areas other than the first and last partial areas, and two words are also used in the first and last partial areas. In the above case, high-speed page access is performed. As a result, the DMA transfer apparatus 1 can complete the DMA transfer at high speed. Further, the storage capacity of the buffer 130 may be at least two pages (more accurately, (size of two pages) − (1 word)).
[0043]
In the above embodiment, the case where both the transfer source and the transfer destination are SDRAMs 4 has been described. Z If one of them is an SDRAM 4, the SDRAM 4 may be accessed for each partial area.
<Second Embodiment>
The DMA transfer system of the present embodiment has a plurality of DMA channels sharing the buffer 130, and when DMA transfer requests of different DMA channels are not competing, each DMA channel is the same as that of the first embodiment. Similarly, access is made for each partial area, and when the DMA transfer request conflicts (when a DMA transfer request of another DMA channel having a higher priority is issued during DMA transfer), the DMA transfer is interrupted and priority is given. After performing a high-frequency DMA transfer, the original DMA transfer is resumed. For this interruption, the DMA transfer system writes the data remaining in the low-priority DMA transfer buffer currently being executed to the transfer destination sequentially, regardless of the page boundary, instead of accessing each partial area. Then, the DMA transfer is interrupted.
[0044]
FIG. 11 is a block diagram showing a configuration of the DMA transfer system according to the second embodiment of the present invention. This DMA transfer system includes a DMA transfer device 6 corresponding to DMA channel 0, a DMA transfer device 7 corresponding to DMA channel 1, a buffer 130, and an access request arbitration unit 1400. Assume that the priority of DMA channel 1 is higher than the priority of DMA channel 0.
[0045]
The access request arbitration unit 1400 receives a DMA channel 0 access request from the DMA transfer device 6 and a DMA channel 1 access request from the DMA transfer device 7, and arbitrates them when they conflict. Here, the access request refers to a request for reading or writing to the memory area including the partial area or page boundary.
[0046]
Specifically, the access request arbitration unit 1400 determines whether or not DMA transfer requests for DMA channels 0 and 1 are set in the DMA transfer apparatuses 6 and 7. This determination depends on, for example, whether or not the unwritten data sizes (REMAIN_W_SIZE_1302, REMAIN_W_SIZE_2302) held in the write management unit 1300 and the write management unit 2300 are 0, respectively.
[0047]
As a result of the determination, if a DMA transfer request for one of the DMA channels is set, the access request arbitration unit 1400 receives the access request for that channel and outputs it to the SDRAM I / F 3.
When a DMA transfer request for DMA channel 0 with a lower priority is set during the DMA transfer for DMA channel 1, the access request arbitration unit 1400 performs an access request for DMA channel 0 after the DMA transfer for DMA channel 1 is completed. Is output to the SDRAM I / F 3.
[0048]
When a DMA transfer request for DMA channel 1 having a higher priority is set during DMA transfer of DMA channel 0, the access request arbitration unit 1400 outputs an interruption instruction to the DMA transfer device 6, and performs DMA transfer according to the interruption instruction. When the notification that the buffer 130 is empty is received from the device 6, the DMA transfer device 7 receives the DMA channel 1 access request and outputs it to the SDRAM I / F 3. As a result, when the inter-D transfer of the DMA channel 1 is completed, a restart instruction is output to the DMA transfer device 6.
[0049]
The DMA transfer apparatus 6 includes a mode setting unit 1100, an access determination unit 1110, an access control unit 1120, a read management unit 1200, a read determination unit 1210, a write management unit 1300, and a write determination unit 1310.
Among these, the mode setting unit 1100, the read management unit 1200, the read determination unit 1210, and the write management unit 1300 have the same configuration as the mode setting unit 100, read management unit 200, read determination unit 210, and write management unit 300 shown in FIG. Is an element. Hereinafter, description of the same components will be omitted, and different points will be mainly described.
[0050]
The access determination unit 1110 has the same function as the access determination unit 110 shown in FIG. 2, and in addition, the access request arbitration unit 1400 is performing transfer by a DMA transfer interruption instruction or resumption instruction via the access control unit 1120. It is configured to suspend and resume DMA. As shown in FIG. 12, the access determination unit 1110 includes a buffer management unit 1111 and a read / write determination unit 1112.
[0051]
The buffer management unit 1111 manages the data amount of the buffer 130 in the same manner as the buffer management unit 111 illustrated in FIG.
The read / write determination unit 1112 has the following functions compared to the read / write determination unit 112 shown in FIG.
That is, when the read / write determination unit 1112 receives an interruption instruction from the access control unit 1120, the read / write determination unit 1112 temporarily prohibits the operation of the partial region determination unit 1311 without performing a determination to perform reading thereafter, and the buffer management unit The data amount calculated in 1111 is notified to the write determination unit 1310, and the data amount is set in the size register 1313. Further, when the data amount calculated by the buffer management unit 1111 becomes “0”, the access request arbitration unit 1400 is notified via the access control unit 1120 that the buffer 130 has become empty.
[0052]
When the read / write determination unit 1112 receives a restart instruction from the access control unit 1120 during the DMA transfer, the read / write determination unit 1112 cancels the prohibition of the operation of the partial area determination unit 1311 and reads / write determination unit 112 shown in FIG. The same determination is performed.
The write determination unit 1310 includes a partial area determination unit 1311, an address register 1312, and a size register 1313 as shown in FIG.
[0053]
The address register 1312 and the size register 1313 are the same as the address register 312 and the size register 313 shown in FIG. However, the PARTIAL_W_SIZE_313 size register 1313 is directly set with the data amount from the read / write determination unit 1112 when the read / write determination unit 1112 receives an interruption instruction. As a result, the size of the data remaining in the buffer 130 is set in the size register 1313.
[0054]
The partial area determination unit 1311 is the same as the partial area determination unit 311 illustrated in FIG. 2 except that the operation is temporarily prohibited by the read / write determination unit 1112.
In addition to the functions of the access control unit 120 illustrated in FIG. 2, the access control unit 1120 outputs a suspend instruction and a resume instruction input from the access request arbitration unit 1400 to the access determination unit 1110 and inputs from the access determination unit 1110 The notification that the buffer 130 to be used is empty is output to the access request arbitration unit 1400.
[0055]
The DMA transfer apparatus 7 includes a mode setting unit 2100, an access determination unit 2110, an access control unit 2120, a read management unit 2200, a read determination unit 2210, a write management unit 2300, and a write determination unit 2310. Since this configuration is the same as that of the DMA transfer apparatus 1 shown in FIG.
<Description of operation>
FIG. 13 is a time chart showing the timing of DMA transfer in the DMA transfer system of this embodiment. In the figure, XBRD, XBWT, ADR, SIZE, DATA, and XACK are the same as those in FIG. In the same figure, the DMA transfer request similar to that in FIGS. 3, 4 and 10 is set in the DMA transfer apparatus 6 (DMA channel 0), and other DMA transfer apparatus 7 (DMA channel 1) is set in the DMA transfer apparatus 7 (DMA channel 1) at the timing T1 in FIG. The timing when a DMA transfer request is set is shown.
[0056]
In the same figure, (1), (2) and (3) are read from the transfer source partial area of DMA channel 0 (1) (2) and written to the transfer destination partial area (FIG. 10). The timing of 3) is shown.
It is assumed that a DMA transfer request of DMA channel 1 having a high priority is set in the mode setting unit 2100 during execution of the partial area writing (3).
[0057]
The access request arbitration unit 1400 is set with a DMA transfer request for DMA channel 1. The Since the DMA transfer request for DMA channel 0 has already been set, an interruption instruction is issued to the DMA transfer device 6. In response to this interruption instruction, the read / write determining unit 1112 in the DMA transfer device 6 does not determine to newly read when (3) in FIG. It is set in the register 1313 and determined to be written. As a result, the access control unit 1120 writes all of the data transferred in the DMA channel 0 and remaining in the buffer 130 to the transfer destination storage area ((7) in the figure).
[0058]
After this writing is completed, the read / write determination unit 1112 notifies the access request arbitration unit 1400 that the buffer 130 is empty. Upon receiving this notification, the access request arbitration unit 1400 gives priority to an access request for the DMA channel 1 from the DMA transfer device 7 and outputs it to the SDRAM I / F 3 ((8) in the figure).
[0059]
Thereafter, the access request arbitration unit 1400 has completed the DMA data transfer of the DMA channel 1. When If it is determined, the DMA transfer apparatus 6 is instructed to resume.
As described above, according to the DMA data transfer system in the present embodiment, it is not necessary to provide an independent buffer for each channel, and a DMA transfer request having a high priority from another channel during data transfer while suppressing the circuit scale. When this occurs, the DMA transfer being executed can be temporarily suspended, and a DMA transfer request with a high priority can be processed first.
<Third Embodiment>
FIG. 14 is a block diagram showing a configuration of the DMA transfer apparatus 8 according to the third embodiment of the present invention. 2 differs from FIG. 2 in that an access determination unit 4110, an access control unit 4120, and a buffer 4130 are provided instead of the access determination unit 110, the write management unit 300, the access control unit 120, and the buffer 130, respectively. ing. Components having the same reference numerals as those in FIG. 2 have the same functions, and thus description thereof will be omitted. Hereinafter, differences will be mainly described.
[0060]
The buffer 4130 is a two-port memory capable of writing and reading in parallel. The two ports of the buffer 4130 are connected to different buses. One port is connected to the SDRAM 4 via the SDRAM I / F 3 and the other port is connected to the SDRAM 4004 via the SDRAM I / F 4003. A read operation and a write operation can be performed from any port. A read operation from the other port is possible simultaneously with a write operation from one port.
[0061]
The access determination unit 4110 directly acquires and manages the data amount (number of bytes) held in the buffer 4130 from the buffer 4130. Therefore, each time one word is written to or read from the buffer 4130, the access determination unit 4110 updates the data amount. Further, the access determination unit 411 determines to perform reading if there is an empty area in the buffer 4130 that is equal to or larger than the size (PARTIAL_R_SIZE_213) of the partial area determined by the read determination unit 210, and is also determined by the write determination unit 310. If the buffer 4130 contains data larger than the size of the partial area (PARTIAL_W_SIZE_313) Set The Since the determination of the read of the transfer source partial area and the determination of the write of the transfer destination partial area are performed independently rather than being selected, the write determination timing is higher than that of the first embodiment. Get faster.
[0062]
Access control unit 4120 reads and writes SDRAM4 and SDRAM4004 in parallel. In other words, the access control unit 4120 reads the partial area determined by the read determination unit 210, and in parallel, writes to the transfer destination area based on the address input from the write determination unit 4310.
<Description of operation>
FIG. 15 is a time chart showing the timing of DMA transfer in the DMA transfer apparatus of this embodiment.
[0063]
In the figure, the upper half shows a signal group output from the access control unit 4120 to the SDRAM I / F 3 and the lower half shows a signal group output to the SDRAM I / F 4003. The transfer source is an area for 7 words from the address 5008 of the SDRAM 4, and the transfer destination is an area for 7 words from the address 600C of the SDRAM 4004.
[0064]
Comparing FIG. 15 with FIG. 10, in FIG. 15, the start timing of writing to the partial area ((3), (5), (6) in FIG. 15) is earlier. This is because the access determination unit 4110 manages the amount of data held in the buffer 4130 in units of words, so that the access determination unit 4110 stores data for the size of the write data in the transfer destination partial area in the buffer 4130. Because the write can be determined at the time of writing In The
[0065]
As described above, according to the DMA transfer apparatus of the present embodiment, in addition to performing high-speed page access for each partial area, when the transfer source memory and the transfer source memory are connected to different buses, the transfer source memory Reading from the memory and writing to the transfer destination memory can be executed in parallel.
<Fourth embodiment>
In the second embodiment, the same memory (SDRAM 4) is used for both DMA channels 0 and 1 or different memories on the same bus. However, in this embodiment, DMA transfer is also performed for memories on different buses. The system will be described.
[0066]
FIG. 16 is a block diagram showing a configuration of a DMA transfer system according to the fourth embodiment of the present invention. This figure is different from FIG. 11 in the second embodiment in that an access request arbitration unit 4400 is provided instead of the access request arbitration unit 1400, and a buffer 4130 is provided instead of the buffer 130. Components having the same reference numerals as those in FIG. 11 have the same functions, and thus description thereof will be omitted.
[0067]
The buffer 4130 is a two-port memory capable of writing and reading in parallel. The two ports of the buffer 4130 are connected to different buses. One port is connected to the SDRAM 4 via the SDRAM I / F 3 and the other port is connected to the SDRAM 4004 via the SDRAM I / F 4003. A read operation and a write operation can be performed from any port.
[0068]
FIG. 17 shows a configuration example of the buffer 4130. The buffer 4130 shown in the figure includes a multiplexer 4130a, a FIFO 4130b, a demultiplexer 4130 multiplexer 4130a, a FIFO 4130b, and a demultiplexer 4130c. The ports 0 and 1 are both connected to the multiplexer 4130a and the demultiplexer 4130c. Thus, the buffer 4130 can execute a write operation from one port and a read operation from the other port in parallel.
[0069]
The access request arbitration unit 4400 sets a DMA channel 1 transfer request having a high priority during DMA transfer of the DMA channel 0, and the transfer destination memory of the DMA channel 0 and the transfer source memory of the DMA channel 1 are the same memory or When the memories are on the same bus, the same operation as the access request arbitration unit 1400 in the second embodiment is performed.
[0070]
Further, the access request arbitration unit 4400, when a transfer request for another DMA channel is set during the DMA transfer and the transfer destination memory and the transfer source memory of the DMA channel are memories on different buses, When reading of the transfer data from the transfer source is completed and the buffer 4130 has a free area corresponding to the read size of the first partial area of the DMA channel, the first partial area of the DMA channel Starts reading.
[0071]
FIG. 18A to FIG. 18F show a case where the transfer destination of the DMA channel 0 and the transfer source of the DMA channel 1 are different memories. In the figure, SRC0 and DST0 indicate a transfer source storage area and a transfer destination storage area of DMA channel 0, and SRC1 and DST1 indicate a transfer source storage area and a transfer destination storage area of DMA channel 1, respectively. In the figure, a broken line marked with (1) indicates reading of the last partial area of the DMA channel 0 (memory → buffer 4130), and an arrow indicated by (2) indicates writing of the last partial area of the DMA channel 0 ( Buffer 4130 → memory). The arrow line (3) means reading of the first partial area of the DMA channel 1 (memory → buffer 4130). The access request arbitration unit 4400 executes in parallel because (2) and (3) are writing and reading to two memories connected to different buses.
<Description of operation>
FIG. 19 is a time chart showing an operation example in the case of FIG.
[0072]
In the figure, the upper half shows a signal group output from the access request arbitration unit 4400 to the SDRAM I / F 3, and the lower half shows a signal group output to the SDRAM I / F 4003. (1), (2), and (3) in the figure correspond to (1), (2), and (3) in FIG.
As shown in the figure, the access request arbitration unit 4400 has a DMA channel 1 transfer request set during DMA transfer of the DMA channel 0, and the transfer destination of the DMA channel 0 and the transfer source of the DMA channel 1 are different (SDRAM 4). 4004), reading of all transfer data of DMA channel 0 from the transfer source is completed (at the time of completion of (1) in the figure), and the first partial area of DMA channel 1 is stored in buffer 4130. Control is performed so that reading of the first partial area of the DMA channel 1 is started when a free area corresponding to the read size exists (at the start of (3) in the figure).
[0073]
As described above, according to the DMA transfer system of the present embodiment, a DMA transfer request for another DMA channel is set during the DMA transfer, the transfer destination memory being transferred in advance, and the newly set DMA transfer request When the transfer request memory is connected to a different bus, the access request arbitration unit 4400 completes reading of the last partial area of the preceding DMA transfer and stores the first part of another DMA channel in the buffer 4130. Since reading of a new DMA transfer request is started when a space corresponding to the size of the area is generated, it is possible to improve the bus use efficiency by two consecutive DMA transfer requests.
[0074]
18A to 18F show the case where a DMA transfer request for DMA channel 1 is set during DMA transfer for DMA channel 0, but the reverse case, that is, during DMA transfer for DMA channel 1 is shown. When the DMA transfer request for DMA channel 0 is set to the same, the same applies as long as the transfer destination memory of the preceding DMA transfer and the transfer source memory of the new DMA transfer are on different buses.
[0075]
The DMA transfer system according to the present embodiment may be configured to include three or more DMA transfer devices. In that case, the access request arbitration unit detects that the reading of the last partial area from all the DMA transfer devices has been completed, determines the transfer destination and the transfer source memory in each DMA transfer device, and based on them Thus, the control as shown in FIG. 19 may be performed.
<Others>
In each of the embodiments described above, the transfer source and the transfer destination are both assumed to be memory capable of high-speed page access, but one of the transfer source and transfer destination is a memory capable of high-speed page access. Only the memory capable of high-speed page access is accessed for each partial area delimited by the page boundary. For example, even in a DMA transfer between a memory capable of high-speed page access and an I / O to which a fixed address is assigned, high-speed page access to the memory can be guaranteed, and the buffer capacity of the buffer 130 or 4130 There may be less.
[0076]
Further, in the first embodiment, instead of the subtractor 211a, a logic circuit or table having input / output logic for inputting the lower 4 bits of REMAIN_R_A_201 in FIG. 6 and outputting the same value as the subtraction result may be provided. Good.
[0077]
【The invention's effect】
(1) A DMA transfer apparatus according to the present invention is a DMA transfer apparatus for a memory corresponding to high-speed page access, and includes a plurality of partial areas constituting a memory area to be transferred, Discrimination means for discriminating each partial area between the top and page boundaries, between page boundaries and between the page boundary and the end of the memory area, and access means for performing high-speed page access for each identified partial area Prepare.
[0078]
According to this configuration, when at least one of the transfer source and the transfer destination is a memory capable of high-speed page access, the DMA transfer device performs high-speed for each partial area delimited by the page boundary in the transfer target memory area. You can guarantee page access. As a result, the present DMA transfer device is compatible with a memory capable of high-speed page access without sacrificing the performance of the memory, and can reduce the bus idle period and the DMA transfer time.
[0079]
(2) The discriminating means holds the initial address of the area to be transferred as an initial value, and each time high speed page access is made by the access means, the held contents are stored in the untransferred area of the memory area to be transferred. Address update means for updating to the start address and the data size of the area to be transferred are held as initial values, and the held contents are transferred for each high-speed page access by the access means, not transferred among the data size to be transferred Data size update means for updating to the data size and the partial area from the start address held as the initial value in the address update means to the nearest page boundary, and the updated start address every time the address update means updates And a partial area discriminating means for discriminating the next partial area from the last page boundary to the end of the memory area. It may be configured to.
[0080]
According to this configuration, each time a high-speed page access is performed, the determination means includes a partial area from the beginning of the memory area to be transferred to the nearest page boundary, a partial area from the page boundary to the next page boundary, ..Sequentially determining a plurality of partial areas such as a partial area from the page boundary to the end of the memory area and the access means performing high-speed page access to each partial area in parallel Can do.
[0081]
(3) The partial area determination means includes a size determination means for determining a size from a head address held in the address update means to the nearest page boundary or the end of the memory area, and a size determined by the size determination means. Size holding means for holding the size of the partial area, and the access means is held by the address updating means. Ru A partial area corresponding to the size held in the size holding means from the start address may be configured to perform high-speed page access.
[0082]
According to this configuration, since the partial area determination unit determines the partial area represented by the parameter of the combination of the start address and the size, the parameter suitable for high-speed page access can be output to the access unit.
(4) The size discriminating unit subtracts a lower bit representing a relative position in the page area, which is a lower bit of the head address held in the address updating unit, from the size of the page area, thereby obtaining the nearest page boundary. The subtraction means for calculating the size up to, the comparison means for comparing the size calculated by the subtraction means with the untransferred data size held in the data size update means, and the result of comparison of the comparison means, whichever is not large Selecting means for selecting, and the size holding means may hold the selection result of the selecting means as the size of the partial area.
[0083]
According to this configuration, the size determination unit can determine the size of the partial region with a simple configuration of subtraction and comparison.
(5) The DMA transfer apparatus according to the present invention is a DMA transfer apparatus for transferring a memory corresponding to high-speed page access, and includes a plurality of transfer source partial areas constituting the first memory area as a transfer source. A first discriminating unit for discriminating a plurality of transfer source partial areas separated by any one of a head, a page boundary, and a tail of the first memory area, and a page boundary; A plurality of transfer destination partial areas constituting the second memory area, wherein the transfer destination parts are divided by any one of a head, a page boundary and a tail of the second memory area and a page boundary. A second discriminating means for discriminating the area, and a transfer destination partial area discriminated by the second discriminating means by reading data from the transfer source partial area discriminated by the first discriminating means by high-speed page access And an access means for writing the read data by the high-speed page access.
[0084]
According to this configuration, when the transfer source and the transfer destination are memories capable of high-speed page access, the DMA transfer device transfers the transfer source portion separated by the page boundary in the first and second memory areas to be transferred. It is possible to guarantee high-speed page access for each area and transfer destination partial area. As a result, the present DMA transfer device is compatible with a memory capable of high-speed page access without sacrificing the performance of the memory, and can reduce the bus idle period and the DMA transfer time.
[0085]
(6) The first discriminating means retains the start address of the first memory area as an initial value, and updates the retained content to the start address of the untransferred area in the first memory area in response to access by the access means. The first address updating means that stores the data size of the first memory area as an initial value, and updates the held content to the untransferred data size of the data size of the first memory area in response to access by the access means. The first data size update means and the transfer source partial area from the head address held as the initial value in the first address update means to the nearest page boundary are discriminated and updated each time the first address update means updates. First partial area discriminating means for discriminating the next transfer source partial area from the first address to the nearest page boundary or the end of the first memory area.
[0086]
According to this configuration, each time high-speed page access is performed, the first determination unit transfers the transfer source partial area from the beginning of the first memory area to the nearest page boundary, and transfers from the page boundary to the next page boundary. The original partial area,..., Sequentially determining a plurality of transfer source partial areas such as a transfer source partial area from the page boundary to the end of the first memory area, and the access means for each transfer source partial area And high-speed page access can be performed in parallel.
[0087]
(7) Further, the first partial area determination means determines the data size from the head address held in the first address update means to the nearest page boundary or the end of the first memory area. And first size holding means for holding the size determined by the first size determining means as the size of the transfer source partial area. The access means reads the transfer source partial area of the size held in the first size holding means from the head address held in the first address holding means by high-speed page access.
[0088]
According to this configuration, since the first partial area determination unit determines the partial area represented by the parameter of the combination of the start address and the size, the parameter suitable for high-speed page access can be output to the access unit. .
(8) The first size determining means subtracts, from the size of the page area, the lower bits representing the relative position in the page area, which is the lower bits of the head address held in the first address update means, First subtracting means for calculating the size up to the nearest page boundary; first comparing means for comparing the size calculated by the first subtracting means with the untransferred data size held in the first data size updating means; And a first selection means for selecting the smaller one as a result of the comparison by the first comparison means, and the first size holding means holds the selection result of the first selection means as the size of the partial region.
[0089]
According to this configuration, the first size determination unit can determine the size of the partial region with a simple configuration of subtraction and comparison.
(9) The second discriminating means holds the start address of the second memory area as an initial value, and updates the held contents to the start address of the untransferred area in the second memory area in response to access by the access means. Second address updating means for holding the data size of the second memory area as an initial value, and updating the held content to the untransferred data size of the data size of the second memory area in response to access by the access means The second data size updating means and the transfer destination partial area from the head address held as the initial value in the second address updating means to the nearest page boundary are discriminated and updated every time the second address updating means updates. Second partial area discriminating means for discriminating the next transfer destination partial area from the first address to the nearest page boundary or the end of the second memory area.
[0090]
According to this configuration, the second discriminating unit has a partial area from the top of the second memory area to the nearest page boundary, a partial area from the page boundary to the next page boundary,. It is possible to simultaneously determine a plurality of partial areas such as partial areas up to the end of, and to access each partial area at a high speed continuously in parallel.
[0091]
(10) The second partial area determination means includes a second size determination means for determining the size from the head address held in the second address update means to the nearest page boundary or the end of the second memory area; Second size holding means for holding the size determined by the two size determining means as the size of the transfer destination partial area, and the access means holds the second size from the head address held in the second address holding means The transfer destination partial area for the size held in the means is written to the high-speed page access.
[0092]
According to this configuration, the second partial area determination means includes a partial area from the beginning of the memory area to be transferred to the nearest page boundary, a partial area from the page boundary to the next page boundary,. Thus, it is possible to simultaneously determine a plurality of partial areas, such as partial areas from the memory area to the end of the memory area, and to access each partial area at a high speed continuously.
[0093]
(11) The second size determining means subtracts, from the size of the page area, lower bits representing the relative position in the page area, which is the lower bits of the head address held in the second address updating means, Second subtracting means for calculating the size up to the nearest page boundary; second comparing means for comparing the size calculated by the second subtracting means with the untransferred data size held in the second data size updating means; And second selection means for selecting the one that is not larger as a result of the comparison by the second comparison means, and the second size holding means holds the selection result of the second selection means as the size of the partial area.
[0094]
According to this configuration, the second size determination unit can determine the size of the partial region with a simple configuration of subtraction and comparison.
(12) Further, the DMA transfer apparatus of the present invention is a plurality of transfer source partial areas constituting the first memory area as the transfer source, and the page boundary between the head of the first memory area and the page boundary. First discriminating means for discriminating each transfer source partial area between the page boundary and the end of the first memory area, and a plurality of transfer destination partial areas constituting a second memory area as a transfer destination, A second discriminating means for discriminating each transfer destination partial area between the head of the second memory area and the page boundary, between page boundaries, and between the page boundary and the end of the second memory area; The data is read from the transfer source partial area determined by the means by high-speed page access and stored in the buffer means, and the data stored in the buffer means is transferred to the transfer destination partial area determined by the second determination means for high-speed page access. Ri and an access means for writing.
[0095]
According to this configuration, when both the transfer source and the transfer destination are memories capable of high-speed page access, the DMA transfer device can transfer each transfer source partial area delimited by a page boundary in the first memory area of the transfer source. In addition, it is possible to guarantee reading by high-speed page access. In addition, it is possible to guarantee that writing is performed by high-speed page access for each transfer destination partial area delimited by page boundaries in the transfer destination second memory area. As a result, the idle period of the bus can be reduced and the DMA transfer time can be shortened.
[0096]
(13) The first memory area and the second memory area are areas in the same memory or areas in different memories connected to the same bus, and the access means is held in the buffer means. The size of the stored data and the free space of the buffer means are compared with the size of the transfer source partial area and the size of the transfer destination partial area, and according to the comparison result, the transfer of the transfer source partial area and the write of the transfer destination partial area Read / write determination means for determining which to perform, and access control means for performing reading from the transfer source partial area and writing to the transfer destination partial area in accordance with the determination of the read / write determination means.
[0097]
(14) The buffer means has at least a capacity obtained by subtracting the memory access size from twice the page area, and the read / write determination means performs transfer in which the free size of the buffer means is determined by the first determination means. If the size is larger than the size of the original partial area, it is determined that reading is performed. If the data size acquired by the buffer management means is larger than the size of the transfer destination partial area determined by the second determination means, write is performed. Decide to do.
[0098]
According to this configuration, it is possible to ensure that reading is performed by high-speed page access for each transfer source partial area and writing is performed by high-speed page access for each transfer destination partial area. Further, since the storage capacity of the buffer means only needs to have at least a capacity obtained by subtracting the memory access size from twice the page area, DMA transfer can be efficiently realized with a small buffer capacity.
[0099]
(15) The buffer means is a two-port memory connected to two buses, and the first memory area and the second memory area are areas in a memory connected to different buses, and the access means In accordance with the size of the data held in the buffer means and the free size of the buffer means, it is determined whether or not to read from the transfer source partial area, and independently of this, writing to the transfer destination partial area is performed. Read / write determining means for determining whether or not to perform, and access control means for performing reading from the transfer source partial area and writing to the transfer destination partial area in accordance with the determination of the read / write determination means.
[0100]
According to this configuration, when the first memory area of the transfer source and the second memory area of the transfer destination are areas in the memory connected to different buses, the buffer is transferred from the transfer source partial area delimited by the page boundary. And the transfer from the buffer to the transfer destination partial area can be performed in parallel, and DMA transfer can be efficiently realized with a small buffer capacity.
[0101]
(17) The present invention is a DMA transfer system having a plurality of DMA channels having different priorities, provided for each DMA channel, accepting a DMA transfer request of the corresponding DMA channel, and performing a DMA transfer request until completion of the DMA transfer A plurality of receiving means for holding each of the memory areas to be transferred, which are provided for each DMA channel and specified in the DMA transfer request of the corresponding DMA channel, and a plurality of partial areas constituting the memory area, A plurality of discriminating means for discriminating each partial area between the top of the memory area and the page boundary, between the page boundaries and between the page boundary and the end of the memory area, and a corresponding DMA channel provided for each DMA channel; A plurality of accesses for generating an access request for instructing high-speed page access for each partial area determined by the determining means. Includes a request generation unit, are shared in each DMA channel, a buffer means for temporarily holding data to be transferred, and arbitration means. Here, when a plurality of accepting means holds a DMA transfer request for only one DMA channel, the arbitrating means performs access according to the access request corresponding to the DMA channel, and holds the DMA transfer request. If a DMA transfer request for a DMA channel with a high priority is accepted, the buffer means is emptied for the determination means and the access request generation means corresponding to the DMA channel of the preceding DMA transfer request. When the buffer means becomes empty, access is performed in accordance with the access request for the high priority DMA channel, and after completion of the high priority DMA transfer, the DMA channel corresponding to the preceding DMA transfer request is handled. Instruct the discriminating means and access request generating means to resume DMA transfer. To.
[0102]
According to this configuration, it is possible to guarantee high-speed page access for each partial area delimited by the page boundary in the memory area to be transferred, and other DMA transfer requests with high priority can be accepted during DMA transfer. In this case, the preceding DMA transfer can be interrupted and switched to a higher priority DMA transfer.
[0103]
(18) The discriminating means corresponding to the preceding DMA channel discriminates the transfer destination area corresponding to the data held in the buffer means when instructed to be interrupted by the arbitrating means, and corresponds to the preceding DMA channel. The access request generating means generates an access request for the transfer destination area determined by the determining means when instructed by the arbitrating means, and the arbitrating means performs high-speed page access according to the access request.
[0104]
This configuration By Thus, when the arbitration means is instructed to interrupt, the determination means determines the transfer destination area corresponding to the data held in the buffer means, and the access request means determines the data in the buffer means to the transfer destination area. Since the arbitration unit executes the access request, the buffer unit can be emptied immediately after the interruption instruction, and the DMA channel can be shifted to a higher priority channel.
[0105]
(19) The discriminating means corresponding to the preceding DMA channel discriminates a partial area constituting an untransferred area in the memory area to be transferred when instructed to resume from the arbitrating means.
According to this configuration, when the restart is instructed, the determination unit restarts the determination of the partial area from the interrupted untransferred area, so that the original DMA transfer can be quickly restored after the restart instruction.
[0106]
(20) Further, the present invention is a DMA transfer system having a plurality of DMA channels, which is provided for each DMA channel, receives a DMA transfer request of the corresponding DMA channel, and holds the DMA transfer request until the completion of the DMA transfer. A plurality of accepting means and a plurality of partial areas constituting the memory area, each of which is provided for each DMA channel and designated in the DMA transfer request of the corresponding DMA channel, A plurality of determination means for determining each partial area between the head and the page boundary, between the page boundaries and between the page boundary and the end of the memory area, and a corresponding DMA channel determination means provided for each DMA channel Multiple access request generation that generates an access request instructing high-speed page access for each partial area determined by Means and a two-port memory shared by each DMA channel and connected to two buses. is there Buffer means and arbitration means are provided. Here, when a plurality of accepting means holds a DMA transfer request for only one DMA channel, the arbitrating means performs access according to the access request corresponding to the DMA channel, and already holds the DMA transfer request. If a transfer request for another DMA channel is accepted and the transfer destination of the previous DMA transfer and the transfer source of the new DMA transfer are memories on different buses, the transfer is in progress. When the reading from the transfer source for all the transfer data of the other DMA channel is completed and there is a free area corresponding to the read size of the first partial area of the other DMA channel in the buffer means, the other DMA Start reading the first partial region of the channel.
[0107]
According to this configuration, it is possible to guarantee high-speed page access for each partial area delimited by page boundaries in the memory area to be transferred, and to read all data from the memory area to the buffer in the preceding DMA transfer. After the completion, the previous DMA transfer write and the new DMA transfer write can be executed in parallel.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a main part of an information processing apparatus including a DMA transfer apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a DMA transfer apparatus.
FIG. 3 shows an example of a partial area determined by a read determination unit.
FIG. 4 shows an example of a partial area determined by a writing determination unit.
FIG. 5 is a block diagram illustrating a detailed configuration example of a partial region determination unit.
FIG. 6 is a diagram showing the number of bytes from the head address to the most recent page boundary as a result of subtracting the lower 4 bits of the head address of the unread area from the constant corresponding to the page size.
FIG. 7 is a block diagram illustrating a detailed configuration example of a partial region determination unit.
FIG. 8 is a diagram showing the number of bytes from the head address to the most recent page boundary as a result of subtracting the lower 4 bits of the head address of an unwritten area from a constant corresponding to the page size.
9 is an explanatory diagram showing a state of DMA transfer between the transfer source and transfer destination storage areas shown in FIGS. 3 and 4. FIG.
10 is a time chart showing the timing of DMA transfer in FIG. 9;
FIG. 11 is a block diagram showing a configuration of a DMA transfer system according to a second embodiment of the present invention.
FIG. 12 is a block diagram illustrating a detailed configuration of an access determination unit.
FIG. 13 is a time chart showing the timing of DMA transfer in the DMA transfer system.
FIG. 14 is a block diagram showing a configuration of a DMA transfer apparatus 8 according to a third embodiment of the present invention.
FIG. 15 is a time chart showing the timing of DMA transfer in the DMA transfer apparatus of this embodiment.
FIG. 16 is a block diagram showing a configuration of a DMA transfer system according to a fourth embodiment of the present invention.
FIG. 17 shows a configuration example of a 2-port buffer.
18 is an explanatory diagram showing a case where the transfer destination of DMA channel 0 and the transfer source of DMA channel 1 are different memories; FIG. .
FIG. 19 is a time chart showing an operation example in the case of FIG.
[Explanation of symbols]
1 DMA transfer device
2 CPU
3 SDRAM I / F
4 SDRAM
5 I / O section
100 Mode setting section
101-105 registers
110 Access decision unit
111 Buffer manager
112 Read / write decision unit
120 Access control unit
130 buffers
200 Read manager
201 Address counter
202 Data counter
210 Read determination unit
211 Partial region determination unit
211a subtractor
211b comparator
211c selector
212 Address register
213 size register
300 Write manager
301 Address counter
302 data counter
310 Write determination unit
311 Partial region determination unit
312 Address register
313 size register
411 Access decision unit

Claims (7)

A DMA transfer apparatus for transferring a memory corresponding to high-speed page access,
In the first memory area that is the transfer source, a plurality of addresses delimited by a start address of the first memory area, one or more page boundaries in the first memory area, and an end address of the first memory area A first discriminating unit for discriminating a transfer source partial area;
In a second memory area that is a transfer destination and has a start address in which an address indicating a relative position in the page area is different from the start address of the first memory area, the start address of the second memory area, the second memory area A second discriminating unit that discriminates a plurality of transfer destination partial areas each divided by one or a plurality of existing page boundaries and an end address of the second memory area;
A buffer unit having a data holding function;
The size of the empty area of the buffer unit is compared with the size of the first transfer source partial area, and when the size of the empty area of the buffer unit is larger than the size of the first transfer source partial area, the first It is determined that the first data in the transfer source partial area is read and written to the buffer unit, and is delimited by the data size of the first data held in the buffer unit , the start address, and the page boundary comparing the size of the first transfer destination subregion, when the data size of the first data is larger than the size of the first transfer destination subregion, among the pre-Symbol first data, the first transfer destination portion A read / write determining unit that determines that second data having the same size as the region is read from the buffer unit and written to the first transfer destination partial region;
According to the determination of the read / write determination unit, the first data is read from the first transfer source partial area and written to the buffer unit, and the second data is read from the buffer unit and the first transfer destination part An access control unit for writing to the area;
A DMA transfer apparatus. The buffer unit is a 1-port memory,
The access control unit reads the first data from the first transfer source partial area to write to the buffer unit and reads the second data from the buffer unit according to the determination of the read / write determination unit. 2. The DMA transfer device according to claim 1, wherein the DMA transfer device performs any one of writing to the first transfer destination partial area. The DMA transfer device according to claim 1,
In the case where the memory to be transferred is composed of the first transfer source partial area,
The read / write determination unit reads the second data from the buffer unit and writes the second data in the transfer destination partial area after the access control unit reads out the second data from the buffer unit. A DMA transfer apparatus that reads three data from the buffer unit and decides to write to a second transfer destination partial area having a next address after a tail address in the first transfer destination partial area as a head address. In the case where the memory to be transferred includes data of a plurality of transfer source partial areas,
The read / write determination unit, after the access control unit reads the second data from the buffer unit and writes the second data to the first transfer destination partial region, the size of the empty region of the buffer unit, The size of the second transfer source partial area whose head address is the next address after the end address in the first transfer source partial area is compared, and the size of the empty area of the buffer unit is larger than the size of the second transfer source partial area. when is large, DMA transfer device according to claim 1, wherein determining that intends row write to the buffer unit fourth data reads of the second transfer source subregion. The read / write determining unit includes a third address other than the second data and the fourth data in the first data, and a first address that is an address next to the end address in the first transfer destination partial area. 2 When the size of the third data and the fourth data is larger than the size of the second transfer destination partial area, the sizes of the third data and the fourth data are compared. 5. The DMA transfer apparatus according to claim 4, wherein data having the same size as the second transfer destination partial area is read from the buffer unit and is determined to be written to the second transfer destination partial area. The buffer unit is a two-port memory connected to two buses,
The access control unit reads the first data from the transfer source partial area and writes to the buffer unit, and reads the second data from the buffer unit according to the determination of the read / write determination unit. An access control unit that independently performs writing to the destination partial area;
The DMA transfer apparatus according to claim 1, comprising: A DMA transfer method for transferring a memory corresponding to high-speed page access,
In the first memory area that is the transfer source, a plurality of addresses delimited by a start address of the first memory area, one or more page boundaries in the first memory area, and an end address of the first memory area Determine the transfer source partial area,
In a second memory area that is a transfer destination and has a start address in which an address indicating a relative position in the page area is different from the start address of the first memory area, the start address of the second memory area, the second memory area A plurality of transfer destination partial areas delimited by one or a plurality of existing page boundaries and the end address of the second memory area,
The size of the free area of the buffer unit having a data holding function is compared with the size of the transfer source partial area, and when the size of the free area of the buffer unit is larger than the size of the transfer source partial area, the transfer Deciding to read the first data of the original partial area and write to the buffer unit,
Comparing the size of the data size of the first data held in the buffer unit and the transfer destination subregion, when the data size of the first data is larger than the size of the transfer destination partial region, wherein of the first data, it determines that writing to the transfer destination subregion the second data having the same size as the transfer destination partial region the heading buffer unit or Ra読,
According to whether the decision performs write write-out, the transfer and writing to the buffer unit from the original partial region reading said first data, said to the destination subregion from the buffer unit reads the second data DMA transfer method for performing writing of data.

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