JP2972711B2 - Ordering control method and node - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ordering control method and a node in a distributed shared memory system in which a plurality of nodes having a central processing unit, a memory, an input / output control unit, and an input / output device are connected.

[0002]

2. Description of the Related Art Conventionally, in a memory system in one node, processing is performed in the order in which memory writes are issued, so that it is not necessary to manage the processing order of memory writes.

[0003]

By the way, in response to a memory write request from an input / output device, a memory write is executed to a processing destination in accordance with an address, and a memory write process is completed with a completion report signal. I was able to receive the request. Therefore, the memory write cannot be executed while waiting for the completion report signal, and the throughput of the entire system is reduced.

In a distributed shared memory system, since memory is distributed and shared by a plurality of nodes, there is a high possibility that overwriting of memory write processing will occur in the case of node switching as it is conventionally. Requires management of the memory write processing order (ordering). In addition, if ordering between devices is required, it is the responsibility of software and hardware does not need to guarantee that much. By the way,
The space between the devices is not “device A → device B” but “device A → memory, device B → memory”.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an ordering control mechanism capable of improving throughput and managing ordering.

[0006]

The present invention has the following arrangement to solve the above-mentioned problems. The gist of the invention according to claim 1 is an ordering control method in a distributed shared memory system in which a plurality of nodes having a central processing unit, a memory, an input / output control unit, and an input / output device are connected, wherein the input / output device A plurality of memory write buffers for holding the memory writes issued by each of the input / output devices are provided in the input / output control unit, and the ordering management of the memory writes is performed in units of the memory write buffers. The node number of the issued memory write is stored and compared with the node number of the memory write to be issued from now on.If the write completion notice of the previous memory write has already been received, the memory write is issued and the node If the numbers do not match and a write completion notice for the preceding memory write has not been received, It consists in ordering control method characterized by inhibiting the memory write you were trying al issued. Claim 2
The gist of the described invention is a node in a distributed shared memory system including a central processing unit and a memory,
The input / output control unit further includes a plurality of input / output devices and an input / output control unit. The input / output control unit includes a memory write buffer for sequentially storing memory writes held for each of the input / output devices, and an ordering management circuit for determining a processing destination. And a node selection table having comparison data for selecting which node is the memory write. The ordering management circuit includes a node number storage unit for storing the node number of the previous memory write, and a node number output from the node number storage unit. A comparator for comparing the node numbers to be executed, a pre-processing count control unit for counting the memory write being executed, an OR circuit for outputting when there is a memory write being executed, and an OR circuit for An AND circuit for ANDing an output and a signal output from the comparator; an inverter for inverting an output of the AND circuit; An AND circuit for and a signal and the request signal emanating from the converter resides in a node, characterized in that it comprises an internal arbitration for arbitrating an output from said AND circuit. The gist of the invention according to claim 3 is that the pre-processing count control unit has an adder / subtractor, and the adder / subtractor adds the value to the pre-processing count control unit for execution of memory write, and 3. The node according to claim 2, wherein the subtraction is performed. Claim 4
The gist of the present invention is characterized in that the OR circuit outputs an output to one of the preprocessing count control units 3 to 5 and an OR operation result indicating whether or not a memory write is executed from an IO device. A node according to claim 2 or 3. The gist of the invention according to claim 5 is that the internal arbitration determines which request is processed first, and issues a permission signal. Exist. The gist of the invention according to claim 6 resides in a distributed shared memory system characterized in that a plurality of the nodes according to claim 2 are connected.

That is, according to the present invention, the processing order is managed by the input / output control unit for identifying the node switching.
Eliminate memory write overtaking.

In addition, by setting a memory write buffer for each of a plurality of input / output devices, when a node is switched by a memory write requested by one of the input / output devices, a waiting time during the node switching is performed. In addition, the memory write from the other input / output device can be processed to improve the throughput of the entire system.

In the present invention, the memory writes input to a plurality of input devices need not be exactly the same.

[0010]

According to the present invention, when the node number of the memory write input to each input / output device is determined and the node numbers match, or when the write completion notice of the previous memory write has already been received, Issues a memory write, and otherwise blocks the issue of a memory write.

More specifically, a memory write buffer for holding the memory write issued by the input / output device for each input / output device is provided in the input / output control unit, and the ordering management of the memory write is performed for each memory write buffer.

Since the memory write from the input / output control unit to the same node has the same path, the order is not likely to be reversed. On the other hand, when node switching occurs, there is a possibility that the write order of the memory write is reversed. Therefore, a node selection table for associating the memory address with the node number is provided, and the node number of the transfer destination is known by referring to the table with the address of the memory write. Also, the node number of the memory write issued from the memory write buffer immediately before is remembered and compared with the node number of the memory write to be issued from now on. If the node numbers do not match and a write completion notification of the preceding memory write has not been received, the order is guaranteed by suppressing the memory write that is about to be issued. However, during this time, issuance of the memory write is suppressed, so that the memory write throughput naturally deteriorates. If the node numbers match, memory writes are issued continuously.

As described above, since it is not necessary to guarantee the order of memory write between input / output devices, if a plurality of memory write buffers are provided for each device, one memory write buffer satisfies the above condition. Even while the issuance is suppressed, if the preceding and succeeding node numbers are the same from another write buffer, memory writes can be continuously issued from this buffer.

As described above, continuous issuance is not possible with one memory buffer to guarantee the order. However, by providing a plurality of memory write buffers, the probability of continuous memory write is increased, and the entire system is guaranteed while ensuring the order. To improve the memory write throughput.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. As shown in FIG. 1, the present embodiment is a distributed shared memory system in which a plurality of nodes are connected, and the configuration thereof includes central processing units A and B, memories C and D, input / output control units α and β, and input / output control units α and β. Output device 1,
It has 2, 3, and 4. This distributed shared memory system logically has one memory in the whole system, and gives a physical address to this memory. This memory is divided into certain units of physical addresses. Each node has the partitioned memory, so that the memory is distributed. For example, there is a memory space of 4 Gbytes, which is divided into four segments. It is assumed that the node 0 handles 0 to less than 2 Gbytes and the node 1 handles 2 Gbytes to 4 Gbytes or less.

The input / output control units α and β include memory write buffers 11 and 21 for sequentially storing memory writes output from the input / output devices 1, 2, 3, and 4, an ordering management circuit 4 for determining a processing destination, A node selection table 5 having comparison data for selecting which node 0 or 1 is a memory write is provided.

As shown in FIG. 3, the ordering management circuit 4 includes node number storages 13 and 23 for storing the node numbers of the previous memory write, and a comparator 15 and a comparator 15 for comparing the node number 100 output from these. 25, preprocessing count controllers 14 and 24 for counting the number of memory writes being executed, OR circuits 16 and 26 for outputting when there is a memory write being executed, and OR circuits 16 and 26. AND circuits 18 and 28 for ANDing the output of 26 and the signals from comparators 15 and 25;
Inverters 17 and 27 for inverting the outputs of the AND circuits 18 and 28, and inverters 17 and 2
7 and the request signal 101
AND circuits 19 and 29 for arbitration, and an internal arbiter 30 for arbitrating outputs from the AND circuits 19 and 29.

The memory write buffers 11 and 21 store the memory writes required by the input / output devices 1, 2, 3, and 4 to enable independent memory write processing without being affected by each other's memory write operation. It is prepared for each device to be stored.

The pre-processing count control unit 14 actually
The adder / subtractor (○) written next to the pre-processing count controller 14
Is added to the value of the pre-processing count control unit 14 for the execution of the memory write,
It is decremented when memory write is completed. Due to these additions and subtractions, the preprocessing count control unit outputs “1” when there is a memory write currently being executed, that is, when the count result is “0”, and when there is no memory write currently being executed, When the result is "0", "0" is output.

The OR circuits 16 and 26 output the output of the pre-processing count control unit 14 and the result of an OR operation on the presence or absence of execution of memory write from the IO device.

The internal arbitration 30 determines which request is processed first, based on the permission signal 102 output from the internal arbitration 30. Memory write buffers 11 and 2
The memory write stored in “1” can execute processing for the memories 0 and 1 of the processing destination. Further, the memory write issuance of both the memory write buffers 11 and 21 is selectively prevented.

Next, the operation of the present invention will be described with reference to FIGS. FIG. 4 is a flowchart showing the flow of the operation.

First, memory writes issued from the input / output devices 1 and 2 are transmitted to the memory write buffers 11 and 21.
Are stored sequentially.

Next, the memory write buffers 11 and 1
2 and the node selection table 5
Is compared with the data stored in the memory through the ordering management circuit 4, the processing node is identified, the memory write operation is arbitrated, the memory write is suppressed, and the memory write is executed.

Next, as shown in FIG. 2, in a 4-gigabyte memory space, when each of the nodes 0 and 1 has a 2-gigabyte area and the addresses of the nodes are compared in binary, the first two
Bit, "00-01" is node 0, "10-11"
Can be separated from node 1. In order to identify the switching of the memory write processing destination node, data in which the first two bits of the address and the setting of the processing destination node are stored in the node selection table 5 in advance, and the input / output devices 1, 2, 3 , 4 for each memory write, the first two bits of the processing destination address and the data of the node selection table 5 are compared to identify the switching of the memory write node.

Next, as shown in FIG. 3, in the operation of identifying a node by comparison, the address of the memory write stored in the input / output devices 1 and 2 is identified by the method shown in FIG. And the node numbers of the node number storage units 13 and 23 storing the node numbers in the previous memory write are compared by the comparators 15 and 25, and if they do not match, "1"
Is output. Pre-processing count control unit 14 that counts the number of memory writes that are being executed earlier
And 24 manage the presence / absence of the memory write being processed by adding the count number if the memory write to be processed is being executed, and subtracting the count number if completed.

Next, if there is a memory write being executed through the OR circuits 16 and 26 from the count of the preprocessing count control unit, the output becomes "1". The output of the OR circuit and the outputs of the comparators 15 and 25 are connected to AND circuits 18 and 2
In step 8, “1” is output if there is a memory write in which the nodes do not match and are being processed by the pre-processing count controllers 14 and 24.

When the outputs of the AND circuits 18 and 28 through the inverters 17 and 27 and the request signal 101 of the memory write which is currently issuing a processing request are ANDed by the AND circuits 19 and 29, the nodes do not match and the processing is in progress. When there is a memory write, the request signal 101 to the internal arbitration 30 becomes “0”, the enable signal 102 outputs “0” by the internal arbitration 30, and the memory write at the time of node switching is suppressed.

Since the ordering control mechanism according to the embodiment is configured as described above, the following effects can be obtained.

The memory write buffers 11 and 21 are prepared for each of the input / output devices 1, 2, 3 and 4, so that the memory write processing can be performed independently without being affected by each other's memory access operation. While waiting for the completion report of the memory write stored in the memory write buffers 11 and 21, the memory write stored in the other memory write buffers 11 and 21 can be executed. As a result, it is possible to increase the probability of continuous memory write and to improve the memory write throughput of the entire system while guaranteeing the order.

Further, in a distributed shared memory system in which a plurality of nodes are connected, identification of node switching by comparison operation of the ordering management circuit 4 as shown in FIG. 3 and suppression of a memory write request accompanied by node switching are provided. In addition, it is possible to realize ordering management for suppressing overtaking of the memory write process. As a result, according to the present embodiment, it is possible to reduce heat generation and power consumption of hardware.

In this embodiment, two input / output devices 1 to 4 are connected.
The present invention is not limited thereto, and may be any number suitable for applying the present invention.

Further, even if only a single input / output device and a memory write buffer are provided for each node, the above effects can be obtained.

The number, position, shape, and the like of the above-mentioned constituent members are not limited to the above-described embodiment, but can be set to a number, position, shape, and the like suitable for carrying out the present invention. In the drawings, the same components are denoted by the same reference numerals.

[0035]

Since the present invention is configured as described above, the following effects can be obtained. The first effect is an improvement in throughput. A memory write buffer is prepared for each input / output device so that memory write processing can be performed independently without being affected by each other's memory access operation, so that completion of memory write stored in one memory write buffer can be reported. , The memory write stored in the other memory write buffer can be executed. This increases the probability of continuous memory writes,
It is possible to improve the memory write throughput of the entire system while guaranteeing the order.

The second effect is that ordering management can be performed. In a distributed shared memory system with a plurality of nodes connected, memory write processing is overtaken by a function of identifying node switching by a comparison operation of an ordering management circuit as shown in FIG. 3 and a function of suppressing a memory write request involving node switching. The ordering management that suppresses is realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a shared memory computer according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the ordering management circuit shown in FIG.

FIG. 3 is a configuration diagram of an ordering management circuit shown in FIG. 1;

FIG. 4 is a flowchart of the ordering management circuit shown in FIG. 1;

[Explanation of symbols]

 α, β Input / output control unit 4 Ordering management circuit 5 Node selection table 11, 21 Memory write buffer 12, 22 Node selection table 13, 23 Node number storage unit 14, 24 Preprocessing count control unit 15, 25 Comparator 16, 26 OR circuit 17, 27 AND circuit 18, 28 AND circuit 30 Internal arbitration 100 Node number 101 Request signal 102 Enable signal

Claims (6)

(57) [Claims] 1. An ordering control method in a distributed shared memory system in which a plurality of nodes having a central processing unit, a memory, an input / output control unit, and an input / output device are connected, the memory write issued by the input / output device Are provided in the input / output control unit, the ordering management of the memory write is performed in units of the memory write buffer, and the memory write buffer issued from the memory write buffer immediately before is provided. Is stored, and compared with the node number of the memory write to be issued from now on, if the write completion notice of the previous memory write has already been received, a memory write is issued, and the node numbers become inconsistent, If you have not received the write completion notification for the preceding memory write, let's issue it now Ordering control method characterized by inhibiting the memory write that was. 2. A node in a distributed shared memory system comprising a central processing unit and a memory, further comprising: a plurality of input / output devices; and an input / output control unit. A memory write buffer for sequentially storing memory writes held for each output device,
An ordering management circuit for determining a processing destination; and a node selection table having comparison data for selecting which node is a memory write. The ordering management circuit stores a node number for storing a node number of a previous memory write. And a comparator for comparing the node numbers output from them,
A pre-processing count control unit for counting a memory write being executed; an OR circuit for outputting when a memory write is being executed; and an output of the OR circuit and a signal output from the comparator. AND circuit to perform AND operation, an inverter for inverting the output of the AND circuit,
A node comprising: an AND circuit for ANDing a signal output from the inverter and a request signal; and an internal arbitrator for arbitrating output from the AND circuit. 3. The pre-processing count control unit includes an adder / subtractor, and the adder / subtracter adds the value to the pre-processing count control unit when performing a memory write, and subtracts when the memory write is completed. The node according to claim 2, wherein 4. The OR circuit outputs an output and an OR operation result indicating whether or not to execute a memory write from an IO device to any one of 3 to 5 of the pre-processing count control unit. The node according to 2 or 3. 5. The node according to claim 2, wherein the internal arbitration determines which request is processed first, and issues a permission signal. 6. A distributed shared memory system, wherein a plurality of the nodes according to claim 2 are connected.