JP2694812B2 - Arbitration system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration system for arbitrating usage rights required by a plurality of arbitrators for exclusively using shared resources.

[0002]

2. Description of the Related Art Conventionally, there is a technique in which a least recently used (hereinafter, LRU) algorithm is created based on a bus arbitration algorithm.
-219156. In the technique described in this publication (hereinafter referred to as the first technique), the priority order logic circuit (134 in FIG. 2) that has received the bus request signal indicating the current request status appropriately requests the bus grant signal according to the above-described priority algorithm. Supplied to the bus unit. Using the feedback and input bus grant signal, the priority next state logic 138 updates the priority status for the next bus grant.

In addition to this, Japanese Patent Laid-Open No. 4-246758 discloses a technique in which priority is held in each arbitration circuit and an external device is required to change the priority. In the technique described in this publication (hereinafter, referred to as the second technique), the arbitration priority request is transmitted from each external device to the arbitration bus (40 in FIGS. 4 and 5) only when the first clock (C1 in FIG. 3) rises. To be done. At the end of the last clock (C2 in FIG. 3), the priority code of the highest priority external device is determined and specifies the external device to become the bus master.
Addresses and data are transferred between the designated bus master and memory or other external device over the non-dedicated bus during the next cycle after the active bus master has finished controlling.

[0004]

The above-mentioned first technique is applied to a system which is composed of a plurality of arbitration means (hereinafter, arbiter) that share one resource and exclusively use it, and issue a resource use request to a shared bus. To do. In this system, the decision circuit arbitrates based on the resource request signal and the arbiter identification information issued from each arbiter. For example, arbitration is performed as follows according to the value of the arbiter identification information so that only one of the four arbiters 1, 2, 3 and 4 acquires the usage right.

When the arbiter identification information is "00", the use right permission signal is unconditionally sent to the resource access section to give priority to the own arbiter and the resource is accessed. Next, if the arbiter identification information is "01", when the arbiter 1 has not issued a usage right request, a usage right permission signal is sent to the resource access unit to access the resource. When the arbiter identification information is "10", the right-of-use permission signal is sent to the resource access unit and the resource is accessed when the arbiters 1 and 2 have not issued the right-of-use request. If the arbiter identification information is "11", and no other arbiter outputs a usage right request, a usage right permission signal is output to the resource access unit to access the resource.

In such a system, some arbiter, for example, the arbiter 1 is fixedly treated as the highest priority, and there is a high probability that a resource request is granted as compared with other arbiters. On the other hand, there is an arbiter that is fixedly treated as a non-priority, for example, the arbiter 4, and the probability that the use permission will be obtained is lower than that of other arbiters.

In such a system, the priorities among the arbiters are fixed, so that the arbiters are unfair in the probability that the use permission is obtained.

As a result, there is a problem that the arbiter having a low priority takes a long time until the use permission is obtained, and the processing performance of the arbiter is extremely deteriorated.

In the above-mentioned second description, the priority order is held in each arbiter, and the change requires the intervention of an external device. Therefore, the priority order change at a high frequency is accompanied by a large hardware addition. In addition, there is a problem that it causes performance degradation.

An object of the present invention is to provide an arbitration system which prevents an unfairness in which only a specific arbiter preferentially acquires a usage right, or a usage right cannot be acquired easily.

Another object of the present invention is to provide an arbitration system in which the processing performance of a specific arbitration circuit is not extremely deteriorated.

Another object of the present invention is to provide an arbitration system in which the arbitration priority can be constantly changed in all arbitration circuits without contradiction.

[0013]

The system of the present invention is an arbitration system that arbitrates a usage right among a plurality of arbitrators (hereinafter, arbiters) requesting the usage right for sharing resources and using them exclusively. And a change signal generating means for supplying a common change signal to the plurality of arbiters (hereinafter referred to as a change signal generation circuit), and each of the plurality of arbiters identifies its own arbiter by a change signal from the change signal generation circuit Priority generating means for modifying the information to generate a priority signal (hereinafter referred to as priority generation circuit), and use based on the priority signal from this priority generation circuit and the usage right request signal of itself and other arbiters And a determination unit (hereinafter referred to as a determination circuit) that generates a right permission signal.

The change signal generating circuit comprises a register and a subtractor for subtracting the contents of this register.

The change signal generating circuit includes a register and a pseudo random number generating circuit for generating a pseudo random number based on the contents of the register and storing it in the register.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a system including an embodiment of the present invention has a resource 5 having a property of being exclusively used by each arbiter, such as a shared bus, sharing this resource 5, and sharing the resource 5. Arbiters 1, 2, 3 and 4 for sending resource use requests to other arbiters prior to use, and a priority change signal generation circuit 6 for supplying a common priority change signal 600 to all these arbiters are provided. There is. The resource use request 100 is a resource use request output from the arbiter 1, and is given to the arbiters 2, 3 and 4. Similarly, the arbiters 2, 3 and 4 respectively request resource 20
Output 0, 300 and 400 to other arbiters. The resource 5 has a property of being exclusively used by each arbiter, and corresponds to, for example, a shared bus. Prior to using the resource 5, the arbiter sends a resource use request to another arbiter. At the same time, referring to the resource use request of another arbiter and the priority change signal 600, it is determined whether or not the own arbiter has the right to use the resource 5, and if the right is used, the resource 5 is used.

Next, the arbiter 1 in FIG. 1 will be described in detail with reference to FIG.

The configuration and operation of the arbiter 1 in FIG. 1 are the same as the other arbiters 2, 3 and 4 in FIG.

Referring to FIG. 2, the arbiter 1 has a holding circuit 13 for holding arbiter identification information, and a priority change signal 6
The arbiter identification information 113 is modified by 00 to output the priority signal 112, which is connected to the priority generation circuit 14, which is connected to the resource 5, and transmits a usage right request signal for resource use to the other arbiters 2, 3 and 4. Resource access unit 11,
The usage right request signal 100 from the resource access unit 11,
Right-to-use request signal 20 from other arbiters 2, 3 and 4
0, 300 and 400 and a determination circuit 12 for receiving the priority order signal 112 from the priority order generation circuit 14 and outputting the usage right permission signal 111 to the resource access unit 11.

Two detailed circuit configuration examples of the priority generation circuit 14 will be described in detail with reference to the drawings.

Referring to FIG. 3A, the first example of the priority generation circuit 14 is composed of exclusive OR gates 141 and 142. These exclusive OR gates 141
And 142 are arbiter identification information 1 from the holding circuit 6.
13 and the priority change signal 600 from the priority change signal generation circuit 6 are exclusive ORed.

Referring to FIG. 3B, the second example of the priority generation circuit 14 is an example in which only the lower 2 bits are used after arithmetic addition. That is, the circuit 14 takes the exclusive OR of the arbiter identification information 113 and the priority change signal 600, and the first exclusive OR gate 143, and the AND gate 144 that takes the logical product of the arbiter identification information 113 and the priority change signal 600. , And a second exclusive OR gate 145 that takes the exclusive OR of the logical product result of the AND gate 144, the arbiter identification information 113, and the priority change signal 600.

The detailed circuit configuration of the determination circuit 12 and the truth value state of the circuit will be described in detail with reference to the drawings.

In the following description, the decision circuit 12 is exemplified by the decision circuit of the arbiter 1. However, this determination circuit 12
Is not limited to the arbiter 1, and the other arbiters 2, 3 and 4 have a configuration showing the truth value state of a similar circuit.

Referring to FIGS. 1 and 4, the decision circuit 1
Reference numeral 2 denotes a NOR gate 121 that performs the NOR operation of the usage right request signals 200, 300 and 400 from the other arbiters 2, 3 and 4, the usage right request signals 200 and 300 from the other arbiters 2 and 3, and NOR gate 122 that NORs the priority signal 112 from the priority generation circuit 14, NOR gate NOR gate 112, the priority signal 112, and the usage right request signal 200 from another arbiter 2. A gate 123, a NOR gate 12 that performs a NOR operation of the priority signal 112.
4, a NOR gate 125 that performs a NOR operation on the outputs of the NOR gates 121 to 124, an inverter 127 that outputs a negation signal of the usage right request signal 100 from the own arbiter 1, and the inverter 127. The output and the output of the NOR gate 125 are NORed and the NOR (N
An OR gate 126 is provided. Such a configuration,
It is organized based on the following table. X in this table
Can be either "0" or "1" (Don '
t care).

[0027]

[Table 1]

Next, a configuration example of the priority order change signal generation circuit 6 shown in FIG. 1 will be described in detail with reference to the drawings.

Referring to FIG. 5, an example of the priority order change signal generating circuit 6 includes a register 61 and a subtractor 62. Since the subtractor 62 subtracts 1 from the content of the register 61 every cycle, the content of the register 61 is 00-> 11.
->10->01-> 00 ...

Referring to FIG. 6, another example of the priority order change signal generation circuit 6 includes a register 61 and a pseudo random number generation circuit 63. The contents of register 61 are 00->
It changes like 10->11->01-> 00 .... Pseudo-random number generation circuit 63 determines the value of the next cycle from the contents of the register 61.

An example of the pseudo random number generating circuit 63 will be described in detail with reference to the drawings.

Referring to FIG. 7, the pseudo random number generation circuit 63
One example is an inverter 6 that inverts the upper (lower) bits.
31 and higher (lower) bits are configured as lower (upper) bits.

Next, the operation of the arbiter 1 will be described in detail with reference to FIGS. 1 and 2.

First, the holding circuit 13 is initialized to hold unique identification information for each arbiter. 4 as in Figure 1
In a system consisting of one arbiter, for example, arbiter 1
For 00, 01 for arbiter 2, 10 for arbiter 3,
2-bit identification information such as 11 can be assigned to the arbiter 4. Although the following description will proceed with four arbiters that can be identified by 2-bit information, the present invention does not limit the number of arbiters to four. By increasing the number of bits of identification information, it can be applied to a system including an arbitrary number of arbiters. Next, the priority order generation circuit 14 modifies the arbiter identification information 113 output from the holding circuit 13 by the priority order change signal 600, and the priority order signal 11
Output as 2. When the output of the holding circuit 13 is 2 bits as in the above-mentioned example, it is sufficient that the priority change signal 600 also has 2 bits, and the priority signal 112 which is the modification result.
Is also 2 bits. The modification is performed such that if the arbiter identification information 113 is different for a certain priority change signal 600, the priority signal 112 is also different. As a modification that satisfies this condition, for example, there is an exclusive OR for each bit, or a method of using only the lower 2 bits after arithmetic addition.

When it becomes necessary to use the resource 5, the resource access unit 11 first outputs a resource use request 100. The usage request signal 100 is a resource usage request 2 from another arbiter.
It is input to the determination circuit 12 together with 00, 300 and 400. The determination circuit 12 uses the resource use requests 100, 200, 3
Arbitration is performed based on 00 and 400 and the priority signal 112. Only one of the arbiters 1, 2, 3 and 4 acquires the right to use the arbitration.

The arbitration operation in the example of the determination circuit 12 shown in FIG. 4 is performed as follows.

Each arbiter has one output port and three upper, middle and lower input ports for resource use requests. Assume that the ports are connected to each other as shown in FIG. For example, the resource use requests 400, 300 and 20 are respectively input to the upper, middle and lower input ports of the arbiter 1.
0 is given. In addition, the decision circuit in each arbiter,
As described above, different priority signals are input. When the own arbiter outputs a resource use request, if the priority signal is 00, the use right is unconditionally granted. If the priority signal is 01, the usage right is granted when there is no resource usage request to connect to the uppermost input port. If the priority signal is 10, the usage right is granted when there is no resource usage request to either the upper or middle input port. When the priority signal is 11, the usage right is granted when there is no resource usage request in any of the upper, middle, and lower input ports. By arbitrating as described above, use permission can be given to any one arbiter. As a result of the arbitration, resources 5 are provided to the own arbiter.
If it is determined that the user has the right to use, the decision circuit 12 outputs the right to use permission signal 111. The resource access unit 11 waits for the usage right permission signal 111 and uses the resource 5.
As described above, in both the configurations of FIG. 5 and FIG. 6, the output signal 600 of the register 61 changes periodically, so that the priority signal 112 of each arbiter can be changed periodically, and as a result, the priority signal 112 of each arbiter is changed. It is possible to evenly give the opportunity to acquire the usage right. Particularly, in the configuration of FIG. 5, the priority order of each arbiter gradually increases. Therefore, even if the usage right permission is not obtained at first as a result of the arbitration, the probability that the permission is obtained increases as the priority becomes higher. On the other hand, in the configuration of FIG. 6, the priority order changes randomly. Although almost the same effect can be obtained with either method, in a system with a large number of arbiters, FIG.
There is an advantage that the waiting time until the permission is obtained is equalized.

[0038]

According to the present invention, a change signal for supplying a common change signal to all arbiters having a holding means for holding the identification information of the arbiter and a changing means for changing the output of the holding means by the change signal. And a supply means. Due to this feature, the present invention has an effect that the arbitration priority can be changed in all the arbiters without any contradiction as the change signal supply circuit changes the change signal. The present invention can prevent the unfairness that only a specific arbiter preferentially acquires the usage right or that the usage right cannot be acquired easily. As a result, it is possible to prevent the arbiter having a low priority from taking a long time until the use permission is obtained, and it is possible to prevent the processing performance of the arbiter from being extremely lowered.

[Brief description of the drawings]

FIG. 1 illustrates a system including an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of an arbiter shown in FIG.

FIG. 3 is a diagram showing a configuration of a priority generation circuit shown in FIG.

4 is a diagram showing a configuration of a determination circuit 12 in the arbiter shown in FIG.

5 is a diagram showing an example of a configuration of a priority order change signal generation circuit 6 shown in FIG.

FIG. 6 is a diagram showing another example of the configuration of the priority order change signal generation circuit 6 shown in FIG.

7 is a diagram showing an example of a pseudo random number generation circuit 63 used in the priority order change signal generation circuit 6 shown in FIG.

[Explanation of symbols]

 1, 2, 3, 4 Arbiter 5 Resource 6 Priority change signal generation circuit 11 Resource access unit 12 Judgment circuit 13 Holding circuit 14 Priority generation circuit 61 Register 62 Subtractor 63 Pseudo random number generation circuit

Claims (3)

(57) [Claims] 1. An arbitration system that arbitrates a usage right among a plurality of arbiters requesting the usage right for sharing a resource and making an exclusive use, and supplies a common change signal to the plurality of arbiters. Change signal generating means, each of the plurality of arbiters, priority generating means for modifying the identification information of its own arbiter with the change signal from the change signal generating means to generate a priority signal, and the priority generating means. An arbitration system comprising: a determination unit that generates a right-of-use permission signal based on a priority order from the unit and a right-of-use request signal of its own and other arbiters . 2. The change signal generating means includes the change signal.
The arbitration system according to claim 1 , further comprising a register for holding and a subtractor for subtracting the contents of the register. 3. The change signal generating means includes the change signal.
Based on the register holding and the contents of this register
And a circuit for generating a predetermined random number
The arbitration system according to claim 1.