JP4266900B2 - Image processing system - Google Patents

Description

  The present invention relates to an image processing system, and more particularly to an image processing system having a DRAM (Dynamic Random Access Memory) that primarily stores image data and a cache memory.

  In recent years, the primary storage area required for image processing is increasing as the image processing becomes more complicated and more accurate. As such a primary storage, an SRAM (Static Random Access Memory) cannot be used or becomes expensive, so an inexpensive and large-capacity DRAM is used. However, because of the structure of the DRAM, the access waiting time (latency) is larger than that of the SRAM. Therefore, the data transfer bandwidth of the DRAM is often a bottleneck, resulting in a slow image processing speed.

  Therefore, a system that realizes high-speed image processing by arranging a cache memory between the DRAM and the image processing unit is known. For example, Patent Document 1 describes an image processing circuit that enables high-speed transfer and low power consumption by subdividing a DRAM and placing it close to a cache memory to shorten the wiring length. . Since this cache memory has a three-port configuration of 1 read / 1 write / 1 read / write, it is possible to simultaneously execute reading to the arithmetic unit, writing of the arithmetic result, and data transfer to the main memory (DRAM). it can. Although not shown in the figure, the cache memory also holds flag data indicating which data in the cache memory is newly written in addition to the block holding pixel data. It is configured. For this flag, when operation result data is written to the cache memory, the bit corresponding to that data is set, and when data is written back from the cache memory to the main memory, only the data for which the flag bit is set is written. If the flag bit is reset, no data is written. As a result, unnecessary write buffer operations can be eliminated, and power consumption can be reduced. Note that writing control to the main memory by this flag can be designated by an external control signal. This flag is reset when data is transferred from the main memory to the cache memory or by an external control signal.

  Further, as a related technique, Patent Document 2 discloses an image generation apparatus that can maintain a drawing speed at a high speed by using an inexpensive memory such as a DRAM as a frame buffer. This apparatus temporarily stores pixel data generated by a drawing processing means such as a drawing engine in a memory such as a FIFO (First In First Out) memory that can be prefetched temporarily, and the FIFO memory and frame buffer that can be prefetched. A high-speed cache memory is provided between them, and the cache control means pre-reads the contents of the pre-readable FIFO memory to control the read / write of the cache memory.

Japanese Patent Laid-Open No. 7-249116 (pages 1, 27 and 27) Japanese Patent Laid-Open No. 9-212661 (FIG. 3)

  In a conventional image processing system using a DRAM, an access latency to the DRAM is reduced by a cache memory arranged between the image processing unit and the DRAM to improve the image processing speed of the image processing system. In particular, since the cache memory described in Patent Document 1 has a three-port configuration of 1 read / 1 write / 1 read / write, it reads data to the arithmetic unit, writes arithmetic results, and data with the main memory (DRAM). The transfer can be executed simultaneously, and the image processing speed can be increased. However, since the cache memory performs data transfer with the DRAM through one read / write port, the transfer speed between the DRAM and the cache memory cannot be increased sufficiently. Therefore, when trying to increase the image processing speed, the transfer speed between the cache memory and the DRAM becomes a bottleneck, and it is difficult to increase the image processing speed. This is particularly noticeable when a plurality of image processes are executed simultaneously.

  An object of the present invention is to provide an image processing system capable of further increasing the processing speed.

An image processing system according to one aspect of the present invention that achieves the above object includes a DRAM (Dynamic Random Access Memory) that primarily stores image data, a DRAM control unit that performs read / write control of the DRAM, and image data. An image processing unit that performs predetermined image processing, and a cache system that is disposed between the DRAM control unit and the image processing unit and that transfers image data. Cache system is configured and read system cache system to perform a pre-read operation by the first-out of the read address for DRAM, from, and write system cache system to perform a write-back operation to write later collectively data to the DRAM, read The system cache system reads the image data from the read cache memory and the DRAM control unit, reads the image data from the DRAM control unit, and the read cache control unit that controls the read image data to be temporarily stored in the read cache memory. And a read DMA (Direct Memory Access) unit that outputs a read address of the DRAM according to a predetermined address generation pattern and performs a pre-read operation.

In the image processing system of the first development form, the read DMA unit calculates a read address of the DRAM based on a predetermined address generation pattern, outputs the calculated address to the read cache control unit, and is input from the read cache control unit. A read address output unit that outputs a next read address in response to a read response signal; and a read FIFO (First In First Out) that temporarily stores image data input from the read cache control unit and outputs the read image data to the image processing unit. It is preferable to provide.

In the image processing system of the second development form, the read cache memory is composed of n (n is an integer of 2 or more) sets of memory groups, and the read cache control unit is provided for each of the n sets of memory groups. It is preferable to control whether or not valid image data to be output has been accumulated, and control to output from the memory group in which the image data has been accumulated to the image processing unit.

In the image processing system of the third development form, when the data bit width of the DRAM is k (k is a natural number) bits and the number of continuous accesses to the DRAM is m (m is a natural number) times, the read cache memory is k × It is preferable that the read data is input from the DRAM controller with an m-bit width.

An image processing system according to another aspect of the present invention includes a DRAM (Dynamic Random Access Memory) that primarily stores image data, a DRAM control unit that performs read / write control of the DRAM, and predetermined image processing on the image data. An image processing unit to be performed, and a cache system that is arranged between the DRAM control unit and the image processing unit and transfers image data. The cache system is composed of a read cache system that performs a read-ahead operation by first writing a read address to a DRAM, and a write cache system that performs a write-back operation that writes data to the DRAM and writes them later. The system cache system includes a write cache memory and a write DMA unit that outputs a write address of a DRAM according to a predetermined address generation pattern and performs a write back operation when reading image data from the image processing unit and writing to the write cache memory If a write cache control unit for controlling to write the temporarily stored image data by the write cache memory to the DRAM controller, Ru comprising a.

In the image processing system according to the fourth development mode, the write DMA unit calculates a write address of the DRAM based on a predetermined address generation pattern, outputs the calculated address to the write cache control unit, and is input from the write cache control unit. It is preferable to include a write address output unit that outputs the next write address in response to a write response signal, and a write FIFO that temporarily stores image data input from the image processing unit and outputs the data to the write cache control unit.

In the image processing system of the fifth development form, the write cache memory is composed of n (n is an integer of 2 or more) sets of memory groups, and the write cache control unit is provided for each of the n sets of memory groups. It is preferable to manage whether or not valid image data to be output is accumulated, and to control to write to the DRAM controller from the memory group in which the image data is accumulated.

In the image processing system of the sixth development mode, when the data bit width of the DRAM is k (k is a natural number) bits and the number of continuous accesses to the DRAM is m (m is a natural number) times, the write cache memory is k × It is preferable that the write data is output to the DRAM controller with an m-bit width.

In the image processing system according to the seventh development form, it is preferable that the predetermined address generation pattern is determined based on the pixel access order in the image processing unit that requests the address generation by the address generation pattern.

In the image processing system according to the eighth development mode, the image processing unit includes a plurality of image processing units, and the write cache system includes a plurality of write DMA units respectively corresponding to the plurality of image processing units. It is preferable to further include a write DMA arbitration unit that arbitrates an access request from the DMA unit, and the write DMA arbitration unit connects a write DMA unit selected from a plurality of write DMA units according to a priority order to the write cache control unit.

In the image processing system according to the ninth development mode, a part of the plurality of image processing units is replaced with an image input unit, and the image input unit selects image data input from the image input device from the plurality of write DMA units. It is preferable to transfer to one write DMA unit.

The image processing system of the deployed configuration of the first 0, the image processing unit includes a plurality of image processing unit, the read system cache system includes a plurality of read DMA section respectively corresponding to the plurality of the image processing unit, a plurality of It is preferable to further include a read DMA arbitration unit that arbitrates an access request from the read DMA unit, and the read DMA arbitration unit connects the read DMA unit selected from the plurality of read DMA units according to the priority order to the read cache control unit.

In the image processing system according to the first development form, a part of the plurality of image processing units is replaced with an image output unit, and the image output unit is transferred from one read DMA unit selected from the plurality of read DMA units. It is preferable to output the image data to the image output device.

The image processing system of the first and second deployed configuration, the image processing unit may be constituted of a CPU (Central Processing Unit) or a DSP (Digital Signal Processor).

  According to the present invention, for each of the read system and the write system to the DRAM, the read cache side performs a read-ahead operation based on read-out of a read address, and the write cache side performs a write-back operation that performs a write operation later. By configuring the cache system, the transfer speed between the image processing unit and the DRAM can be increased. Therefore, it is possible to configure an image processing system having a very high processing speed.

  FIG. 1 is a block diagram showing a configuration of an image processing system according to an embodiment of the present invention. The image processing system 1 includes an image input unit 13 that inputs image data from the image input device 2, image processing units 15a, 15b, and 15c that perform various types of image processing on the input image data, and image processing. An image output unit 14 for outputting the image data to the image output device 3, a cache system 10, a DRAM control unit 12, and a DRAM 11. The cache system 10 includes DMA units 24a, 24b, 24c, 24d, and 24e that perform data exchange with the image input unit 13, the image processing units 15a, 15b, and 15c, and the image output unit 14 using DMA (Direct Memory Access). . Further, a DMA arbitration unit 23 that arbitrates requests from the DMA units 24a, 24b, 24c, 24d, and 24e, a read cache 21 that temporarily stores read data from the DRAM 11, and a write cache that temporarily stores write data to the DRAM 11 22 and a cache control unit 20 that controls the read cache 21 and the write cache 22.

  In the image processing system 1 configured as described above, in the cache system 10, the read data is pre-read by the read cache 21, and the write back operation is performed by the write cache 22. Therefore, the processing in the image input unit 13, the image processing units 15a, 15b, and 15c, and the image output unit 14 can be performed almost continuously. Further, the cache memory is configured to have a bit width necessary for continuous access to the DRAM 11 so that the DRAM 11 can be continuously accessed. Therefore, the image processing system 1 uses the DRAM 11 as a reference memory for image processing, and exchanges data between the DRAM 11 and the image input unit 13, the image processing units 15a, 15b, and 15c, and the image output unit 14. By applying the cache system 10, high-speed image processing is realized. Hereinafter, the image processing system 1 will be described in more detail with reference to examples.

  FIG. 2 is a block diagram showing the configuration of the image processing system according to the first embodiment of the present invention. The image processing system 1 includes an image input unit 13 that receives image data from an image input device 2 (for example, a scanner or a camera), image processing units 15a and 15b that perform image processing such as contour enhancement and enlargement / reduction, and the like. An image output unit 14 that outputs image data to an image output device 3 (for example, a television or a printer), a cache system 10, a DRAM control unit 12 that controls the DRAM 11, and a DRAM 11 are provided. The cache system 10 includes a write DMA unit 34a, 34b, 34c that reads data from the image input unit 13 and the image processing units 15a, 15b and writes the data to the write cache control unit 31 by DMA, and a read cache control unit. Read DMA units 35b, 35c, 35a that read data from 30 and write to the image processing units 15a, 15b, and image output unit 14 by DMA, write DMA units 34a, 34b, 34c, read DMA unit 35b, From the DMA arbitration unit 23 that receives requests from 35c and 35a and adjusts the respective requests according to the timing and priority, the read cache control unit 30 that controls the cache of data from the DRAM 11, and the DMA arbitration unit 23 Control the data cache And a preparative cache control unit 31.

  The write DMA units 34a, 34b, and 34c include write address generation units 36a, 36b, and 36c that generate DMA addresses for the DMA arbitration unit 23, respectively. The read DMA units 35b, 35c, and 35a include prefetch read address generation units 37b, 37c, and 37a that generate read addresses for DMA prefetching to the DMA arbitration unit 23, respectively. Further, the read cache control unit 30 includes a cache memory 80 that caches read data, and the write cache control unit 31 includes a cache memory 67 that caches write data.

  The image data to be processed is transferred and processed along the path P, for example. First, image data is input from the image input device 2, transferred in the order of the image input unit 13, the write DMA unit 34 a, the DMA arbitration unit 23, the write cache control unit 31, the DRAM control unit 12, and the DRAM 11, and stored in the DRAM 11. Is done. Next, the image data stored in the DRAM 11 is transferred to the image processing unit 15a in the order of the DRAM 11, the DRAM control unit 12, the read cache control unit 30, the DMA arbitration unit 23, the read DMA unit 35b, and the image processing unit 15a. Predetermined image processing is performed by the image processing unit 15a. The image data after the image processing in the image processing unit 15a is transferred in the order of the write DMA unit 34b, the DMA arbitration unit 23, the write cache control unit 31, the DRAM control unit 12, and the DRAM 11, and is stored again in the DRAM 11.

  When image processing is further performed on the image data processed by the image processing unit 15a by the image processing unit 15b, the image data stored again in the DRAM 11 is stored in the DRAM 11, the DRAM control unit 12, and the read cache control unit 30. The DMA arbitration unit 23, the read DMA unit 35c, and the image processing unit 15b are transferred in this order, and necessary image processing is performed by the image processing unit 15b. The image data after the image processing in the image processing unit 15b is transferred in the order of the write DMA unit 34c, the DMA arbitration unit 23, the write cache control unit 31, the DRAM control unit 12, and the DRAM 11, and is stored again in the DRAM 11.

  Further, the image data that has undergone the image processing is transferred to the image output unit 14 in the order of the DRAM 11, DRAM control unit 12, read cache control unit 30, DMA arbitration unit 23, read DMA unit 35 a, and image output unit 14. Are output to the image output device 3.

  Next, details of the read DMA units 35a, 35b, and 35c will be described. FIG. 3 is a block diagram showing the configuration of the read DMA unit according to the first embodiment of the present invention. The read DMA units 35a, 35b, and 35c have the same configuration, and are represented by the read DMA unit 35 in FIG. The read DMA unit 35 calculates and outputs a request address, an address pattern generation unit 44 that generates a next address based on a predetermined address generation pattern and passes the address to the address calculation unit 45, and a read DMA A read request control unit 43 that outputs a read request signal to the arbitration unit 38, a FIFO 41 that stores read data from the read DMA arbitration unit 38 and outputs the read data to the image processing unit, and manages the rest of the FIFO 41 Counter 42.

  The read request control unit 43 outputs a read request signal to the read DMA arbitration unit 38 and the counter 42 unless a full signal is output from the counter 42. When a read response signal is returned from the read DMA arbitration unit 38, the address calculation unit 45 calculates the next address and outputs the next address to the read DMA arbitration unit 38 as a request address. Read data from the read DMA arbitration unit 38 is stored in the FIFO 41 in synchronization with the data valid signal. The data stored in the FIFO 41 is output from the FIFO 41 by a read signal from the image processing unit 15 (representing the image processing units 15a and 15b and the image output unit 14). When the content of the FIFO 41 is empty, a wait signal is output to the image processing unit 15. The counter 42 indicates that the data in the FIFO 41 is full when the value immediately after the reset is 0, is incremented by the read request signal, is decremented by the read signal, and becomes the same value as the number of stages of the FIFO 41. The Full signal is output to the read request control unit 43.

  FIG. 4 is a timing chart in the read DMA unit according to the first embodiment of the present invention. As shown in FIG. 4, the read response signal corresponding to the read request signal output together with the request address and the data valid signal indicating the validity of the read data are divided in time, and the address flow and the data flow are piped. Lined up. Pre-reading of read data can be performed by pipelining.

  Next, details of the write DMA units 34a, 34b, and 34c will be described. FIG. 5 is a block diagram showing the configuration of the write DMA unit according to the first embodiment of the present invention. The write DMA units 34a, 34b, and 34c have the same configuration and are represented as the write DMA unit 34 in FIG. The write DMA unit 34 calculates and outputs a request address, an address pattern generation unit 54 that generates a next address based on a predetermined address generation pattern and passes it to the address calculation unit 55, and a write DMA A write request control unit 53 that outputs a write request signal to the arbitration unit 39; and a FIFO 51 that stores data from the image processing unit 15 and outputs the data to the write DMA arbitration unit 39. The write request control unit 53 outputs a write request signal to the write DMA arbitration unit 39 when data is stored in the FIFO 51 (the Empty signal is not output). When the write response signal is returned from the write DMA arbitration unit 39, the address calculation unit 55 calculates the next address and outputs it to the write DMA arbitration unit 39.

  FIG. 6 is a timing chart in the write DMA unit according to the first embodiment of the present invention. Unlike the read DMA unit shown in FIG. 4, the request address and the write data are output in synchronization, and the data flow and the address flow are not pipelined.

  Next, address generation in the read DMA and write DMA, that is, address generation in the address pattern generation unit 44 and the address pattern generation unit 54 will be described. In the case of image processing, unlike the case of the CPU cache, there is a specific pattern unique to image processing in the way the generated address advances. FIG. 7 is a diagram illustrating an example of how the address advances in the case of a simple increase in the address generation unit. In many cases, the address is simply increased, and changes in the order of 0, 1,..., 6, 7, 10, 11,..., 16, 17, 20,.

  FIG. 8 is a diagram illustrating an example of how to advance an address when a pixel filter is used for image processing. Here, an example is shown in which image processing is performed with an image calculation filter of 3 × 3 pixels, and the address increases not in a simple increase but in a certain pattern. The addresses change like 0, 10, 20, 1, 11, 21, 2, 21, 22,..., 7, 17, 27, 10, 20, 30, 11, 21, 31,.

  As in the above example, there is a certain pattern unique to the image processing in the advance of the address generated in the image processing. Therefore, it is possible to prefetch the address by a simple circuit based on this pattern. The address pattern generation unit 44 and the address pattern generation unit 54 may be configured to change the address pattern to be set by a control unit (not shown).

  Next, details of the write cache control unit 31 will be described. FIG. 9 is a block diagram illustrating a configuration of the write cache control unit. The write cache control unit 31 is located between the write DMA arbitration unit 39 and the DRAM control unit 12 and has a write cache memory 67 therein, and the cache memory 67 has 0 to n-1 (n is a natural number). A number is assigned. The configuration of the cache memory 67 has a bit width of the DRAM 11 times a bit width of the continuous number in order to continuously transfer data to the DRAM 11.

  In the example described below, the bus width of data from the write DMA units 34a, 34b, and 34c is 32 bits, the bit width of the DRAM 11 is 32 bits, the number of consecutive accesses is 8, and the configuration of the cache memory 67 is 32. The number of bits is 8 × n. In addition, in order to increase the data transfer bandwidth to the DRAM controller 12, the memory configuration has eight 32-bit × n 2-port memories, and write data is written in a width of 32 bits × 8 = 256 bits. Output to the DRAM controller 12.

  That is, for example, when n = 6 as shown in FIG. 10, the cache memory 67 is configured to input with a 32-bit width and output with a 256-bit width. Note that FIG. 10 illustrates an example in which valid data is represented by black marks, and the data of the cache number 4 is sufficient and output.

  In FIG. 9, the write cache control unit includes control registers of a flag register 64, an address register 65, and a write enable register 66 in order to control the write cache. The flag register 64 is composed of 1 bit × n, and bit 1 indicates that valid data is stored in the cache memory 67. The address register 65 is composed of p (p is a natural number) bits × n, stores a write address, and outputs it to the DRAM controller 12. The write enable register 66 is composed of 8 bits × n, holds information indicating where data is written in the eight cache memories 67, and outputs this information to the DRAM controller 12 as byte enable. .

  In order to control each register described above, each request signal from the write DMA units 34a, 34b, and 34c is arbitrated, and a write DMA arbitration unit 39 that determines a DMA channel to be processed, and a write DMA arbitration unit 39 From the write control unit 63 that receives a request and returns a write response and performs write control of each register, the cache number determination unit 61 that determines the cache number from the requested write address and the value of the register, and the write enable register 66 A write back control unit 62 that determines a write status to the cache memory 67 and writes back to the DRAM 11 is provided.

  On the other hand, the write DMA arbitration unit 39 includes selectors 68a, 68b, and 68c and a priority order determination unit 69. The priority order determination unit 69 prioritizes each request signal output from the write DMA units 34a, 34b, and 34c. The write request selected based on is output to the write control unit 63. In addition, the processing channel selected based on the priority order is output to the selectors 68a, 68b and 68c. The selector 68a outputs the write response output from the write control unit 63 to each of the corresponding write DMA units 34a, 34b, 34c selected based on the processing channel as each write response signal. The selector 68b selects each write address output from the write DMA units 34a, 34b, and 34c based on the processing channel, and outputs the selected address to the cache number determination unit 61, the address register 65, and the write enable register 66. Further, the selector 68 c selects each write data output from the write DMA units 34 a, 34 b, 34 c based on the processing channel and outputs it to the cache memory 67.

  Next, the operation of the write cache control unit will be described using an example of state change of the control register. FIG. 11 is a diagram illustrating a state change of the control register in the write cache control unit. In FIG. 11, the cache number n = 8, the state where “1” is written is indicated by hatching, and the state “0” which is cleared is indicated by blank.

  The state (1) indicates the initial state, and all the registers are cleared.

The state (2) indicates a state when a write request is received from the write DMA arbitration unit 39. When a write request is generated, the write control unit 63 determines whether a full signal is output from the cache number determination unit 61 and outputs a write response to each register and the cache memory 67. The cache number determination unit 61 performs determination according to the following priority order, and outputs the cache number to each register and the cache memory 67.
1. The flag register is 1, and the address register matches the write address.
2. The flag register is 0.
3. Otherwise, the cache full signal is output.
As a result of this write response, write data is stored in the cache memory 67, the value of the corresponding flag register becomes 1, the requested write address is stored in the address register, and the stored data is stored in the write enable register. The bit becomes 1.

  The state (3) indicates a state where all the write enable registers (representing byte enable bits) of the cache number 1 (second stage from the top) are set to 1. The write back control unit 62 determines this state from the state of the byte enable bit, and makes a write request for data of cache number 1 to the DRAM control unit 12.

  The state (4) indicates a state in which writing to the DRAM portion is completed. The flag register and the write enable register corresponding to the cache number 1 are cleared to 0 by the write response from the DRAM control unit 12. If all the caches are filled and a write request to a different address is received, the cache number determination unit 61 outputs a cache full signal to the write control unit 63 and the write back control unit 62. The write control unit 63 does not output a write response. Further, the write back control unit 62 that has received the cache full signal forcibly makes a write request for data of an appropriate cache number to the DRAM control unit 12 even if the byte enable bits are not all set to 1. In this case, the cache number is selected in the order of the smallest cache number, the order in which the byte enable bits are filled, the order in which the last write-back time is old, or the like.

  Next, details of the read cache control unit 30 will be described. FIG. 12 is a block diagram showing the configuration of the read cache control unit. Like the write cache control unit 31, the read cache control unit 30 has a read cache memory 80 and is assigned numbers 0 to n−1. The configuration of the cache memory 80 is the same as that of the write cache memory 67, and includes eight 32-bit × n 2-port memories.

  In order to control the read cache memory 80, each of a reception register 76, an address register 77, a frequency register 78, and a flag register 79 is provided. The flag register 79 is composed of 1 bit × n, and bit 1 indicates that valid data is stored in the cache memory 80. The reception register 76 is composed of 1 bit × n, and bit 1 indicates that a read request is made to the DRAM control unit 12. The address register 77 is composed of p bits × n and stores a read address. The number register 78 is composed of 4 bits × n and indicates the number of times read from the cache memory 80.

  In order to control each of the above registers, each read request signal from the read DMAs 35a, 35b, and 35c is arbitrated to determine a DMA channel to be processed, and a read request from the read DMA arbitration unit 38 The read control unit 72 that issues a read request to the DRAM control unit 12 and outputs a response signal to the read DMA arbitration unit 38, and a cache number that outputs a cache number and a cache hit signal from the requested read address. The determination unit 71, a read response FIFO 73 for storing a response signal from the read control unit 72, a read request FIFO 75 for storing a read request from the read control unit 72, the data of the read response FIFO 73 and the cache memory 80 Data that outputs read data based on the data storage status And an output control section 74. The DRAM control unit 12 is a general one, and an appropriate one is selected depending on the type of the DRAM 11.

  On the other hand, the read DMA arbitration unit 38 includes selectors 81a, 81b, 81c, and 81d and a priority order determination unit 82. The priority order determination unit 82 receives each read request signal output from the read DMA units 35a, 35b, and 35c. The read request selected based on the priorities is output to the read control unit 72. The processing channel selected based on the priority order is output to the selectors 81a and 81b and the read response FIFO 73. The selector 81 a selects each read address output from the read DMA units 35 a, 35 b, and 35 c based on the processing channel, and outputs the selected address to the cache number determination unit 71, read request FIFO 75, address register 77, and read response FIFO 73. The selector 81b outputs the response signal output from the read control unit 72 to any of the read DMA units 35a, 35b, and 35c as a read response signal selected based on the processing channel. The selector 81c outputs the data valid signal output from the data output control unit 74 to any of the read DMA units 35a, 35b, and 35c as the data valid signal selected based on the channel information output from the read response FIFO 73. To do. Further, the selector 81d outputs the read data from the cache memory 80 to the read DMA units 35a, 35b, and 35c based on the channel information output from the read response FIFO 73.

  Next, the operation of the read cache control unit will be described using an example of the state change of each control register. FIG. 13 is a diagram illustrating a state change of the control register in the read cache control unit. In FIG. 13, the cache number n = 8, except for the number register, the state where “1” is written is indicated by hatching, and the cleared state “0” is indicated by blank.

  The state (1) shows the initial state, and all the registers are cleared.

The state (2) indicates a state when a read request is received from the read DMA arbitration unit 38. When a read request occurs, the read control unit 72 looks at the cache Hit signal and cache Full signal from the cache number determination unit 71, the request Full signal from the read request FIFO 75, and the response Full signal from the read response FIFO 73, and reads the read request. Output signal and response signal. The cache number determination unit 71 performs determination according to the following priority order and outputs a cache number.
1. The flag register is 1 and the address register and the read address match (in this case, the cache number determination unit 71 outputs a cache Hit signal to the read control unit 72).
2. The flag register is 0 and the reception register is 0.
3. The reception register is 0, and the number of times register is the most.
4). Otherwise, the cache full signal is output.
Initially, the cache memory 80 does not yet contain the requested address data, so the cache hit signal is not output, and the read control unit 72 outputs a read request and a response signal. In response to the read request, the reception register 76 is set to 1, the read address is stored in the address register 77, and the number register 78 and the flag register 79 are cleared to 0. The read request FIFO 75 that has received a read request from the read control unit 72 makes a read request to the DRAM control unit 12.

  The state (3) indicates a state in which read data from the DRAM control unit 12 is stored in the cache memory having the cache number 0 (the uppermost stage). The reception register 76 is cleared to 0 and the flag register 79 is set to 1 by the data valid signal from the DRAM controller 12. When the flag register 79 becomes 1, the data output control unit 74 processes the response signal from the read response FIFO 73 and outputs a data valid signal. The read DMA arbitration unit 38 outputs read data and a data valid signal to the read DMAs 35a, 35b, and 35c. The value of the number register 78 is incremented by 1 by the data valid signal.

  The state (4) indicates a state in which all the cache memories 80 are filled with read data from the DRAM 11 or are scheduled to be filled. When a new read request comes in this state, the one with the largest value in the number register 78 (in this example, the fifth stage from the top is the largest with the number 8) is discarded (cache flush).

  The state (5) indicates a state in which a cache flush is executed when a new read request comes in the state (4). As a result, the old read cache is sequentially discarded and the next new read data is stored.

  Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a block diagram showing a configuration of an image processing system according to the second embodiment of the present invention. In FIG. 14, the same reference numerals as those in FIG. CPUs (Digital Signal Processors) 90a and 90b execute predetermined image processing based on programs built in the ROMs 92a and 92b, respectively, and correspond to the image processing units 15a and 15b in FIG. . Further, the CPU (DSP) 90a and 90b can perform setting of the read DMA units 35d and 35e or the write DMA units 34d and 34e as required. The ROMs 92a and 92b may be replaced with rewritable devices such as FROM and disk systems, and the image processing content can be flexibly changed by replacing programs. The SRAMs 91a and 91b function as work memories when the CPUs (DSPs) 90a and 90b operate. The image processing system configured as described above operates in the same manner as in the first embodiment.

  The field of application of the present invention is applicable to applications requiring image processing, such as a digital copying machine, a FAX, a printer, a digital camera, an HDD (Hard Disk Drive) recorder, and a DVD (Digital Versatile Disc) player.

1 is a block diagram illustrating a configuration of an image processing system according to an embodiment of the present invention. 1 is a block diagram illustrating a configuration of an image processing system according to a first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of a read DMA unit according to the first embodiment of the present invention. 3 is a timing chart in the read DMA unit according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of a write DMA unit according to the first embodiment of the present invention. 6 is a timing chart in the write DMA unit according to the first embodiment of the present invention. It is a figure which shows the example of how to advance the address in the case of simple increase in an address generation part. It is a figure which shows the example of how to advance the address in the case of using a pixel filter for image processing. It is a block diagram which shows the detail of a write cache control part. It is a figure showing the example of a structure of a cache memory. It is a figure showing the state change of the control register in a write cache control part. It is a block diagram which shows the detail of a read cache control part. It is a figure showing the state change of the control register in a read cache control part. It is a block diagram which shows the structure of the image processing system which concerns on 2nd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing system 2 Image input device 3 Image output device 10 Cache system 11 DRAM
12 DRAM control unit 13 Image input unit 14 Image output unit 15, 15a, 15b, 15c Image processing unit 20 Cache control unit 21 Read cache 22 Write cache 23 DMA arbitration unit 24a, 24b, 24c, 24d, 24e DMA unit 30 Read cache Control unit 31 Write cache control unit 34, 34a, 34b, 34c, 34d, 34e Write DMA unit 35, 35a, 35b, 35c, 35d, 35e Read DMA unit 36a, 36b, 36c Write address generation unit 37a, 37b, 37c Read address generation unit 38 Read DMA arbitration unit 39 Write DMA arbitration unit 41, 51 FIFO
42 Counter 43 Read request control unit 44, 54 Address pattern generation unit 45, 55 Address calculation unit 53 Write request control unit 61 Cache number determination unit 62 Write back control unit 63 Write control unit 64 Flag register 65 Address register 66 Write enable register 67 , 80 Cache memories 68a, 68b, 68c, 81a, 81b, 81c, 81d Selectors 69, 82 Priority determination unit 71 Cache number determination unit 72 Read control unit 73 Read response FIFO
74 Data output control unit 75 Read request FIFO
76 Reception register 77 Address register 78 Number of times register 79 Flag register 90a, 90b CPU
91a, 91b SRAM
92a, 92b ROM

Claims (14)

DRAM (Dynamic Random Access Memory) that primarily stores image data;
A DRAM controller for performing read / write control of the DRAM;
An image processing unit that performs predetermined image processing on the image data;
A cache system disposed between the DRAM control unit and the image processing unit for transferring image data;
With
The cache system is
A read cache system for performing a read-ahead operation by a read-out of a read address to the DRAM;
A write cache system that performs a write-back operation of writing data to the DRAM and writing the data later;
Consisting of
The read cache system is
Read cache memory,
A read cache control unit that reads image data from the DRAM control unit and controls the read image data to be temporarily stored by the read cache memory;
When reading image data from the DRAM control unit, a read DMA (Direct Memory Access) unit that outputs a read address of the DRAM according to a predetermined address generation pattern and performs a pre-read operation;
An image processing system comprising: The read DMA unit
A read that calculates the read address of the DRAM based on the predetermined address generation pattern and outputs the calculated read address to the read cache control unit, and outputs the next read address according to a read response signal input from the read cache control unit An address output section;
Read FIFO (First In First Out) that temporarily stores image data input from the read cache control unit and outputs the image data to the image processing unit;
The image processing system according to claim 1, further comprising: The read cache memory is composed of n (n is an integer of 2 or more) sets of memory groups,
The read cache control unit manages whether or not valid image data to be output is accumulated for each of the n groups of memory groups, and outputs the image data from the memory group in which the image data is accumulated to the image processing unit. the image processing system according to claim 1, wherein the controller controls so. When the data bit width of the DRAM is k (k is a natural number) bits and the number of continuous accesses to the DRAM is m (m is a natural number) times, the read cache memory reads the read data with a width of k × m bits. claim 1 or 3 image processing system according to characterized in that it is configured to input from the DRAM control unit. DRAM (Dynamic Random Access Memory) that primarily stores image data;
A DRAM controller for performing read / write control of the DRAM;
An image processing unit that performs predetermined image processing on the image data;
A cache system disposed between the DRAM control unit and the image processing unit for transferring image data;
With
The cache system is
A read cache system for performing a read-ahead operation by a read-out of a read address to the DRAM;
A write cache system that performs a write-back operation of writing data to the DRAM and writing the data later;
Consisting of
The write cache system is
Write cache memory,
A write DMA unit that outputs a write address of the DRAM according to a predetermined address generation pattern and performs a write-back operation when reading image data from the image processing unit and writing it to the write cache memory;
A write cache control unit that controls to write image data temporarily stored in the write cache memory to the DRAM control unit;
An image processing system comprising: The write DMA unit
Lights, calculated on the write address of the DRAM to the predetermined address generation pattern and outputs to the write cache controller, and outputs the next write address by the write response signal inputted from the write cache control unit An address output section ;
A write FIFO that temporarily stores image data input from the image processing unit and outputs the image data to the write cache control unit;
The image processing system according to claim 5, further comprising: The write cache memory is composed of n (n is an integer of 2 or more) memory groups,
The write cache control unit manages whether or not valid image data to be output has accumulated for each of the n groups of memory groups, and the memory control unit stores the image data from the memory group to the DRAM control unit. 6. The image processing system according to claim 5 , wherein the image processing system is controlled to write. When the data bit width of the DRAM is k (k is a natural number) bits and the number of continuous accesses to the DRAM is m (m is a natural number) times, the write cache memory has the write data in the k × m bit width. the image processing system according to claim 5 or 7, wherein being configured to output to the DRAM controller. Said predetermined address generation pattern according to any one of claims 1, 2, 5, 6, characterized in that determined based on the access order of the pixels in the image processing unit that requests the address generation by the address generation pattern Image processing system. The image processing unit includes a plurality of image processing units,
The write cache system includes a plurality of write DMA units respectively corresponding to the plurality of image processing units, and further includes a write DMA arbitration unit that arbitrates access requests from the plurality of write DMA units,
The image processing system according to claim 5, wherein the write DMA arbitration unit connects a write DMA unit selected from the plurality of write DMA units according to a priority order to the write cache control unit. Replacing a part of the plurality of image processing units with an image input unit;
11. The image processing system according to claim 10 , wherein the image input unit transfers image data input from the image input device to one write DMA unit selected from the plurality of write DMA units. The image processing unit includes a plurality of image processing units,
The read cache system includes a plurality of read DMA units corresponding to the plurality of image processing units, and further includes a read DMA arbitration unit that arbitrates access requests from the plurality of read DMA units,
The read DMA arbitration unit, an image processing system according to claim 1, wherein the connecting the read DMA section selected according to priority from the plurality of read DMA section in the read cache controller. Replacing a part of the plurality of image processing units with an image output unit;
13. The image processing system according to claim 12 , wherein the image output unit outputs image data transferred from one read DMA unit selected from the plurality of read DMA units to an image output device. The image processing system according to any one of claims 1 to 13, wherein the image processing unit is configured of a CPU (Central Processing Unit) or a DSP (Digital Signal Processor).

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