KR950001734Y1 - Realtime simulation circuit of high speed digital signal processor - Google Patents

Abstract

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Description

High speed digital signal processor real-time pseudo circuit

1 is a conventional program loading general purpose EP ROM circuit diagram.

2 is a circuit block diagram of the present invention.

3 is a circuit diagram of the embodiment of FIG.

4 is a timing chart of each part of FIG.

* Explanation of symbols for main parts of the drawings

1: High speed digital processor (DSP) real time pseudo circuit 11: Low speed ROM

12: High Speed RAM 13: Data Transfer Logic

14: high speed DSP 15: data buffer

The present invention relates to a real-time simulation circuit of a high-speed digital processor having a mask ROM, which is a real-time pseudo circuit that enables real-time doctors on the target board side of the digital processor using a relatively low-cost, low-speed ROM and a high-speed RAM. It is about a circuit.

In the case of using a digital signal processor in a computer system having a mask ROM, a general user needs to request a manufacturer to load his program.

In addition, at the time of such a production request, since a large quantity of requests were required in terms of price, loading based on one or two units of samples was impossible.

In addition, since it is almost impossible to modify the loaded program due to the characteristics of the mask ROM, it is difficult to use the mask ROM in simulation of a target board using a digital signal processor (DSP).

As described above, for the purpose of a high speed DSP having a mask ROM, an external circuit is formed of a general-purpose ROM, thereby generating a standby state corresponding to the access time of the built-in external memory, and thus every instruction (command). This has been a problem by inserting as much delay time as necessary to ensure operational stability.

For example, a typical form of this type is shown in FIG.

Here, the CPU 21 of the (Digital Signal Procsessor), the address multiplexers 22 to 24, the address decoder 25, the first EP ROM 26a and the second to fourth EP ROM blocks 26b to 26d, and standby The state generating circuit 27 or the like is included.

In this case, the DSP is a high-speed type with an instruction cycle of 60 ns, and at this operating speed, a high-speed memory having an access time of 25 ns or less is required to ensure real-time operation of zero standby without any standby state.

However, in reality, high-speed mass ROM of less than 25ns is expensive and difficult to obtain, and there is a disadvantage that the requirement of additional equipment for loading a program in such a special high-speed ROM is essential.

However, in the case of constructing a pseudo circuit by inserting 1 to 2 standby states according to the speed of an external ROM according to the related art, since real time operation is impossible with zero standby during program execution, it is more than 2 to 3 times higher than the real time operation There was a decisive drawback to having to deal with processing delays.

The present invention has been made to solve such a problem in the related art. In particular, in such a system, a program loaded in a low speed ROM is transferred to a high speed RAM before execution of the DSP program to ensure real-time intention of the program, and the DSP accesses the high speed RAM. It provides a high-speed digital processor real-time pseudo circuit that enables program execution to be zero standby real time.

In particular, the present invention has a low-speed ROM loaded with a user program and a RAM having random data. The data transfer logic of data transmission and signal generation from the low-speed ROM to the high-speed RAM together with the reset operation in the system, and the data It is characterized by a real-time pseudo circuit of the DSP which has a related structure between a high speed DSP controlled by the data transfer logic and a data buffer for temporarily storing data between the high speed ROM and the low speed RAM during the transfer operation of the transfer logic. .

Further features of the present invention will be understood by examining the present invention in more detail in conjunction with the embodiment drawings.

That is, FIG. 2 shows the DSP real time pseudo circuit 1 according to the present invention.

Here, the system has a low speed ROM 11 and a high speed RAM 12 that temporarily stores data from the low speed ROM 11, and transfers data from the low speed ROM 11 to the high speed RAM 12. A data transfer logic 13 which generates a predetermined signal by the set signal, a high speed DSP 14 which is operated and controlled when moving data from the low speed ROM 11 to the high speed RAM 12 in the data transfer logic 13; A DSP buffer for buffering data between the high speed RAM 12 and the low speed ROM 11, and a DSP reset for generating a reset of the DSP between the high speed DSP 14 and the data transfer logic 13; The set portion 16 is configured to include.

3 is an exemplary embodiment of FIG. 2 in more detail.

Here, a conventional DSP 14 IC, a data transfer logic block 13, a data buffer 15, four high speed RAM 12 chips (RA _{1 to} RA ₄ ), and four low speed ROM 11 chips (RO _{1 to} RO ₄ ), and the like, and a strobe and an address decoder I ₁ between the DSP 14, the low speed ROM 11, the high speed RAM 12, and the data transfer logic 13, respectively. A gate G ₁ for misaligning the output of the control unit and a control and address buffer I ₂ are provided.

The present invention of such a configuration is as follows.

That is, the real-time pseudo circuit 1 of the present invention is maintained in a state where a user program is loaded in the low speed ROM 11 and random data exists in the high speed RAM 12 in an initial state.

In this state, when the system reset 28 is input from the whole system, the DSP 14 keeps the DSP hold signal at a logic?, So that the DSP 14 remains in a standby state.

While the DSP 14 is dealing with, the data transfer logic starts counting as much as the data range to be transferred, and transfers the data to the high speed RAM 12 through the data buffer 15 for every address of the low-speed ROM 11. Transmit by 1 word.

After all the contents in the low speed RAM 11 to be transferred are transferred to the high speed RAM 12, the data buffer 15 is disabling so that the data path is closed from the low speed ROM 11 to the high speed RAM 12 and the DSP ( 14) With the hold signal as logic 1, the DSP 14 performs a real-time operation in which there is no standby state from the high speed RAM 12.

When the data is transferred from the low speed ROM 11 to the high speed RAM 12, the low speed ROM 11 read pulses and the high speed RAM 12 write pulses are generated on a regular basis. Each address is given a time of 400 ns. During this period, the low speed ROM 11 read pulse and the fast RAM 12 write pulse having a width of 100 ns are alternately generated to achieve the data transfer.

The present invention is advantageous in that the real-time pseudoprocessing of a high-speed DSP capable of real-time processing of the real-time processing while improving the processing speed of such a system by using the low-speed ROM and setting the standby state of the DSP to ø.

Claims (1)

In a computer system for accessing data of a mask ROM by a DSP 14, the mask ROM becomes a low speed ROM 11 and needs data in the high speed RAM 11 that receives the data of the low speed ROM 11. Transfer control to the high speed RAM 12 while temporarily suspending the DSP 14 and closing the data buffer 15 after the predetermined data of the low speed ROM 11 is transmitted to the high speed RAM 12. A high speed digital processor real-time pseudo circuit, characterized in that it is associated with a data transfer logic (13) adapted to initiate operation.