KR950003401B1 - Device which generates column address latch signal - Google Patents

Abstract

The column address latch signal generating unit makes video RAM output valid data independent of synchonization with output enable signal or CAS signal. The column address latch signal generating unit outputs column address latch signal by combination of RAS chain master clock and CAS chain master clock and comprises a latch unit inputting CAS chain master clock and controlled by some control signals; a decoder unit inputting RAS chain master clock and the output signals of latch unit.

Description

Column address latch signal generator

1 is a block diagram showing the flow of data in the serial read operation of the video RAM.

2 (a) and 2 (b) are circuit diagrams of a ФYAL signal generator according to the prior art.

3 is an operation timing diagram according to FIG.

4 is a block diagram of a ФYAL signal generator according to the present invention.

5 (a) and 5 (b) show the embodiment of FIG.

6 is an operation timing diagram according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to random access memory, and more particularly to an apparatus for generating a column address latch signal of a video RAM.

Video RAM is a dual port memory, as known in the art, and has two input / output terminals, random port and serial port, which are independently accessible from each of the two ports. Memory element. The video RAM is generally composed of dual-port dynamic RAM, and should have both a function of normal dynamic RAM and a function unique to video RAM. In particular, the page mode, which is a mode for repeatedly accessing consecutive addresses at high speed during a read cycle, is an essential operation mode of the normal dynamic RAM. Several times in a state This is a mode that allows you to access memory rows of different columns in the same row by toggling. In read transfer, the transfer from the RAM data port is done in the same way as the normal dynamic RAM, whereas the transfer from the SAM data port is via a data register called SAM (serial access memory).

In this regard, a block diagram showing the flow of data during the serial read operation in the video RAM is shown in FIG. When the predetermined data is accessed from the serial clock enable, the first data is output through the RAM port 140 during the transfer operation to satisfy the t _SCA . Then, the extra data from the second data is output from the sample port 180. That is, as shown, the first data is " ФYAL generator 100 → column address buffer 110 → decoder 120 → column select gate CSL → I / OS / A 130 → ФRDL generator 150 ), The RAM data port 140 → the Sam output pin 190 " are output in this order (In the above, the ФYAL signal is a column address latch signal and the ФRDL signal is a RAM data latch signal. Signal to enable 150) Of The signal is a data transmission / output enable signal, which is a control signal supplied from the outside of the chip (described in detail in the data book {MOS MEMORY Vol. 1} published by the present applicant in 1991). The extra data after the second is output in the order of "DTP signal generator 160-> Sam data register 170-> Sam data port 180-> Sam output pin 190". In this order, the first data is output from the array after the column address latched by the FYAL signal is decoded and the column select gate CSL is enabled. And amplified through I / OS / A 130 and input to RAM data port 140. At this time, the ФRDL signal latches only data input at a specific time and stores it in the RAM data port 140. Data after the second data is output from the sam as described above.

The output of the first data under the configuration of FIG. 1 is produced by the ФYAL signal, and is shown in FIG. 2A as a specific circuit diagram of the ФYAL signal generator. FIG. 2A is also applied to a normal dynamic RAM, and its configuration is as follows. In FIG. 2A, the generation of the signals PIR, PRAT, and PIR may be performed by the same logic as in FIG. The row address strobe signal Before the signal becomes active, ФR ( Chain master clock) and ФRAT are kept at the "L" level, respectively. remind When the signal becomes active, the ФR rises to the "high" level and the ФRAT rises to the "high" level to enable the third and fourth NAND gates 6 and 8. Further, when ФRCD rises to the "high" level, the output of the second NAND gate 5 becomes the "high" level. Then the column address strobe signal When the signal is active and goes to the "low" level, ФC ( Means the chain master clock) rises to the "high" level, and the ФC is made of a ФYAL signal.

On the other hand, this case is a case of long t _RCD , and in case of a short t _RCD , ФRCD generates a ФYAL signal.

The ФYAL signal is disabled from "high" to "low" to latch the valid column address of the column address buffer 110 of FIG. That is, the øYAL receives the ФRAT signal, which is information that the row address is latched, and goes from the "low" level to the "high" level. Receive inform ФC and latch it from "high" to "low" level. Under this operation, once During the cycle During the signal toggling several times, øC also toggles several times, followed by the toggle of the ФYAL signal in succession to latch the column address to implement page mode operation. As such, the øYAL signal is typically It is designed to change as the signal changes. From this, the ФYAL generator 100 as shown in FIG. When the signal goes from the active state to the precharge state, the enable period of the unnecessary ФYAL signal is generated once more as shown in FIG. That is, as shown in FIG. 3, the Of Signal generates a ФYAL signal that latches the column address. Changing to the "high" level later than the signal generates an invalid ФYAL signal (ie an invalid address), such as a hatched portion, after which the ФRDL signal is enabled, causing invalid data to be output. do.

Therefore, an object of the present invention is a data transmission / output enable signal in page mode. Of Or the column address latch (ФYAL) signal is It provides a video RAM that is enabled independently.

It is another object of the present invention to provide a data transmission / output enable signal in page mode. Of ) Or column address strobe ( ) Provides video RAM that outputs valid data regardless of signal.

Still another object of the present invention is to provide a data transmission / output enable signal in page mode. Of ) Or column address strobe ( The present invention provides a column address latch signal generator that generates a column address latch (ФYAL) signal capable of maintaining an independent signal state regardless of a signal.

In order to achieve the object of the present invention the present invention is the main path (main path) of the column address latch signal The purpose is to control the generation of the column address latch signal by controlling and latching the signal. In addition, the address signal control method according to the present invention to achieve the object of the present invention is a signal of the first falling edge of the column address strobe signal during the active period of the row address strobe signal in the transfer mode (transfer mode) Column address is latched, and this latch is an address signal control method that is disabled only when the row address strobe signal goes to the precharge period. In addition, the circuit configuration according to the embodiment of the present invention is a row address strobe signal ( Row address strobe chain master clock and column address strobe signal ( A column address latch signal generator for outputting a column address latch signal by a combination of column address strobe chain master clocks enabled by < RTI ID = 0.0 >),< / RTI > And a decoder unit for operating the latch stage and the decoder unit for inputting the row address strobe chain master clock and the output signal of the latch stage, respectively. The column address latch signal generating apparatus according to the present invention controls the column address strobe chain master clock to a signal receiving the mode when the specific mode is selected, and the circuit part after the latch stage is an external signal. It is asynchronous to.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 4 is a block diagram of a column address latch signal generating apparatus based on the technical idea of the present invention. An embodiment of the block configuration of FIG. 4 is illustrated in FIGS. 5A and 5B, and an operation timing diagram thereof is shown in FIG.

The block diagram of FIG. 4 is a block diagram of the column address latch signal generator according to the present invention. It consists of 100. The configuration of the decoder unit 100 can be easily realized by the conventional ФYAL generator as shown in FIG. In addition, the control signal for each operation mode means a signal that is enabled in each of a plurality of operation dances of the chip. For example, in page mode, a signal for performing the page mode is enabled. Refers to the enabled signal.

The structural features of FIG. 5 (a) which is a specific embodiment of FIG. 4 according to the present invention are as follows. In FIG. 5A, the block shown by the dotted line block 100A 'is a latch stage according to the present invention. The dotted line block 100 'has the same circuit configuration as that of FIG. 2A, and the operation characteristic according to the input signal also has the same characteristics as that of FIG. The structural features of the latch stage 100A 'are as follows. The transmission gate 12 and the latch circuits 13 and 14 are provided in the main path of ФC, which is a column address strobe chain master clock, and used as a control signal of the transmission gate 12. Is input. remind As shown in (b) of FIG. 5, the signal is a signal generated from the column enable signal generated in the transfer mode. Φ is a signal generated by delaying a predetermined time It is a signal that latches a valid address before the signal proceeds to a tap-load operation, which is an operation of specifying a second or later address which is input first after the address input. The operating characteristics under such a configuration are as follows. Φ, information called transfer mode When the signal is enabled, the main path of the ФYAL generator is completely blocked to prevent the generation of invalid addresses. That is, Φ during transmission If the signal is enabled (that is, occurs "low") The signal goes " low " to " turn-off " the transmission gate 12, from which latching operations are performed in the latch circuits 13 and 14. As shown in FIG. Thus, the previous ФC signal continues to be supplied by the latch circuits 13 and 14, and the subsequent ФC signal is interrupted.

This operation can be easily understood with reference to FIG. 6, which is an operation timing. That is, as shown Signal and Of Regardless of the signal, a valid ФYAL signal is generated only once and subsequently maintained at a "low" level, so that when the ФRDL signal is enabled to latch the RAM data port 140 of FIG. 1, column selection with valid address information is selected. The data of the gate CSL is latched. Therefore, as an external signal for enabling the column address By operating independently of the change of the signal, the possibility of generating an invalid address is almost eliminated.

5 (a) and 5 (b) are the best embodiment realized according to the block structure of FIG. 4 based on the idea of the present invention, but for example, the transmission gate is another switching circuit that receives a control signal for each mode. It should be noted that it may be constructed. In addition, although the present invention has been described by applying the video RAM, it is obvious to those skilled in the art that the same method can be applied to the normal dynamic RAM.

As described above, the present invention includes a latch stage for inputting a mode-specific control signal to the input terminal of the column address latch circuit, so that the column address is changed during the transfer operation. Wow Of Regardless of signal synchronization, the effective address is latched and the first data output from the RAM data port is effectively output, thereby improving the reliability of the video RAM.

Claims (6)

Low address strobe signal Row address strobe chain master clock and column address strobe signal ( A column address latch signal generating device for outputting a column address latch signal by a combination of column address strobe chain master clocks enabled by < RTI ID = 0.0 >)< / RTI > And a decoder unit for inputting a latch stage to be operated and an input signal of the row address strobe chain master clock and the latch stage, respectively. The apparatus of claim 1, wherein the control signal is a signal that is enabled in a transfer mode. The column address strip of claim 1 or 2, wherein the decoder unit is an external signal when the control signal is input. Column address latch signal generator, characterized in that the asynchronous operation. The transmission device of claim 1, wherein the latch stage is controlled by a signal generated by a predetermined time delay from a column enable signal in a transfer mode and controls transmission of the column address strobe chain master clock. And a latch circuit master circuit comprising a latch circuit for latching a signal output through the transmission gate. 1. A column address latch signal generator, comprising: a switching circuit operated by a predetermined control signal and inputting a column address strobe chain master clock, and a latch circuit latching a column address strobe chain master clock output through the switching circuit; And latching only the first input of the column address strobe chain master clock and ignoring subsequent inputs thereof. 6. The apparatus of claim 5, wherein the control signal is a signal generated in a transfer mode.