JPH02294742A - Data bus competition evading circuit for ice - Google Patents

Abstract

PURPOSE:To prevent a data bus from generating competition and to eliminate a buffer by shifting respective access cycles of a tester and a memory by utilizing a retry signal included in a partial CPU. CONSTITUTION:At the time of starting a memory read cycle, the CPU 1 outputs address information to an address bus 11 and then outputs a strobe signal 13. At the time of deciding the address information as an access from a memory 4, a map control part 7 outputs a retry signal 19 to the CPU 1. The CPU 1 invalidates the read data after completing the current bus cycle and generates the same bus cycle again. Since a retry cycle signal obtained by sampling the retry signal 19 is turned to an L level in the map control part 7, the memory 4 is turned to the enable state and data are outputted from the memory 4 to a data bus 12. Thus, the data bus can be prevented from generating competition and a buffer can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention This invention relates to a microprocessor (hereinafter referred to as CP
It's called IJ. ) is an in-circuit emulator (
Hereinafter referred to as ICE. ), the tester and I that occur when the data bus buffer between the tester and the CPU are deleted.
This is about a circuit to avoid contention on the CE data bus. (Next technology and problems) Next, a block diagram of a conventional ICE will be explained with reference to FIG. 4. In FIG. Memory, 4 is emulation memory (hereinafter simply referred to as memory), 5 is buffer, and 10 is CPU.CPUIO is the same type as the target CPU of the tester, and when CPUIO accesses external memory , for memory read, outputs an address signal to the address bus 1l, and at the same time sets read write 1 to signals 17 to II level.
- Set the lobe signal 13 to L level to notify the outside that the address bus 11 is valid. The external memory responds by sending data back to the data bus 12, so
C l) tJ 1 0 collects data from the data bus 12, returns the strobe signal 13 to level 11, and completes the read cycle. Similarly, when writing memory, the CPU 10 outputs address information to the address bus 11 and sends data +? to the data bus l2. It outputs a 1-level signal to the read/write signal 17, and then sets the slave signal 13 to a level to inform the outside that a memory write I/cycle error has occurred. In response to this, the external memory writes data to the specified address of the memory, and the CPU IO outputs the strobe signal l3.
Return to level 11 to complete the light cycle. Memory 2 is accessed from C P tJ 1 0, but it is accessed when C:'P[J10 is in the ICE mode, that is, in the ICE internal control state without executing the tester program. be. In other words, the memory 2 stores programs and data necessary for the cpuio to control the inside of the ICE. Memory 3 and memory 4 are also accessed from CP[J10, but the CPUIO of memories 3 and 4 is in RUN mode, that is, in a state where the tester program is executed, especially when the tester does not have memory at a specific address installed. For these reasons, it is used in place of the tester's memory. Next, a diagram of the memory 3 is shown in Figure 5. In Figure 5,
Address bus 11 and mode switching signal 1 from CPU 10
6 is added to the input of memory 3 as an address signal. By combining the input signals to the memory 3, a map signal 14, an access signal 15 and an enable signal 18 are taken out as outputs. The map signal 14 and enable signal l8 are further connected to the address and chip enable terminals of the memory 4, and have the function of locating the memory 4, which has a limited capacity, at any address in the vast address space of the CPU IO. The access signal l5 includes the map information of the memory 4 and the R U
It has a v1 function that notifies the buffer 5 whether or not to access the memory of the tester based on the mode switching signal of N mode or ICE mode. When the access signal l5 is at L level, the buffer 5 is enabled to access the tester, and data flows in the direction determined by the read/write signal 17. On the other hand, if the access signal 15 is at H level, this indicates ICE mode or emulation memory access, and no data is exchanged with the tester, so the buffer 5 is in a disabled state. Furthermore, in the RUN mode, the gate 6 is opened and the strobe signal 13 is supplied to the tester as a DS signal. By the way, since the ICE removes the CPU of the tester and operates in its place, the timing of the probe part of the ICE should be as close to the CPUIO as possible. However, in the case of a conventional ICE, C }) Due to the buffer 5 inserted between U 1 0 and the tester, the timing of the data bus will be delayed by about Ion seconds. For this reason, the tester can operate only with the CPU, but with ICE
The data bus setup time is approximately 10n when connected.
It may happen that it stops working because it takes a few seconds longer. In particular, the total number of CPUIO bus cycles is 60 to 100.
If there is only about 0 seconds, even Ion seconds will result in a large loss. Therefore, it is desirable to delete buffer 5 if possible. While CPUIO is accessing memory 2 in ICE mode, gates 1 and 6 are closed, so the DS signal is not supplied to the tester. Therefore, even if buffer 5 is not present, only the output data from memory 2 will be carried on data bus 12, so buffer 5 may be deleted. Furthermore, even when the CPUIO is accessing the memory of the tester, only data from the tester is loaded onto the data bus 12, so there is no problem even if the path buffer 5 is not provided. However, when the cpuio is reading data from the memory 4, the DS signal is supplied to the tester, so
Data is output from the tester and also from memory 4, so if buffer 5 is not present, data bus 1
2, the data of both will collide, resulting in a conflict. FIG. 6 shows the operation when the CPUIO accesses the memory 4, and shows that the buffer 5 cuts data coming from the target and prevents data conflicts on the data bus 12. In this way, in order to prevent contention on the data bus 12 while accessing memory 4, &eX cannot delete buffer 5, which makes it difficult to achieve high-speed CPU CE. ．． (C) Purpose of the Invention This invention provides that some CPUs utilize the
By staggering the access cycles of the I'J tester and memory 4, contention on the data bus is prevented.
Our goal is to be able to delete buffer 5 in Figures 4 and 6. (d) Embodiment of the Invention Next, a horizontal diagram of an embodiment of the invention is shown in FIG. FIG. 1 is a diagram corresponding to FIG. 6, and is a block diagram when accessing the memory 4. Therefore, in order to realize an actual ICE, it is necessary to add the memory 2 etc. shown in FIG. 4 to FIG. 1, but since the memory 2 etc. are not directly related to this invention, they are not shown in FIG. 1. The CPU l in FIG. 1 is almost the same as the CPUIO in FIG. 4, but differs from the CPU to in FIG. 4 in that it has a signal input terminal for the CPU I in FIG. 1. The 91-Rye terminal is a function of CPUs such as GMICRO/200, and when the CPU is executing a memory access cycle, by inputting the R1-Rye signal from the outside, the CPU completes the current memory access cycle. After that, execute the same bus cycle again. If the retried bus cycle is a read cycle, the data read in the previous cycle becomes invalid, and the data read in the retry cycle becomes valid. The memory 4 and gate 6 in FIG. 1 are the same as those in FIG. The map control section 7 corresponds to the memory 3 shown in FIG. 6, but its operation is different, and a block diagram of an embodiment of the map control section 7 is shown in FIG. Map control section 7 in Fig. 2
is the address bus 11 from the CPUI and the map control unit 7.
The retry signal I9, which is its output, is sampled at the rising edge of the strobe signal 13 of CPLI 1, and the try cycle signal 20 is input as an address, and the map signal 14, enable signal l8, and CPUL to the memory 4 are input.
The try signal 19 and mask signal 31 to l are output as data. Next, the operation when reading data from the memory 4 shown in FIG. 1 will be explained with reference to time charts 1 to 3 shown in FIG. When the CPUI starts a memory read cycle, address information is output to the address bus 11, followed by a strobe signal 13. At this point, the CPU
Since it is not known that the address accessed by No. 1 is on the tester side or the memory 4 side, the slobe signal 13 is output as it is to the tester as No. 3. Next, the map control unit 7 When the address information is determined and it is determined that the access is to the memory 4 side, the CPU 1 issues a retry signal 19.Then, after the current bus cycle is completed, the CPU invalidates the read data and repeats the same bus cycle. This time, the try signal l9 is generated inside the man-build controller 7.
is sampled and the tricycle signal 20 is at L level, so the enable signal 18 is set to L level according to the preset data. Re1/Rei signal 1 9
= 1-1, the mask signal 3 1 becomes H, the memory 4 becomes enabled, and the data in the memory 4 is output to the data bus 12. At the same time, the strobe signal 1
3 is masked by the mask signal 31, the DS signal is not output to the tester, and no data is output from the tester. In this way, the tester and the memory 4 are accessed in a time-sharing manner, and the memory 4 can be accessed without data conflicts even without the buffer 5 shown in FIG. (Effects of the cl invention) According to this invention, the buffer can be deleted without data bus contention, so that approximately 1.
This eliminates the delay time of 0.11 seconds and has the following effects. (γ) ICE can be operated at the same timing as the CPU alone, and although the CPU alone operates, the ICE
You can prevent accidents where the machine does not move by connecting it. (It is possible to realize an ICE that can follow the high-speed operation of ICPLJ.

[Brief explanation of the drawing]

FIG. 1 is a diagram of an embodiment of the present invention, FIG. 2 is a horizontal diagram of an embodiment of the map IIJ control section 7, and FIG. 3 is a time chart when reading data from the memory 4 of FIG. 1. Fourth
The figure is a block diagram of a conventional ICE, FIG. 5 is a diagram of the memory 3, and FIG. 6 is an explanatory diagram of the operation when the CP (JIO accesses the memory 4 7 times. 1... CPU , 2...Memory for ICE control, 3...Memory, 4...Emulation memory, 5...Buffer, 6...
...Gate, 7...Map control section, 11...
...address bus, 12...data bus,
13... Strobe signal, 14... Map signal, 15... Access signal, 16...
...Mode switching signal, 17...Read/write signal, 18...Enable signal, 19...
...Retry signal, 20...Re1, recycle signal, 2l...FF, 31...Mask signal.

Claims (1)

[Claims] 1. Address bus (11) and strobe signal (13) are input, map signal (14), enable signal (18)
), a map control unit (7) that outputs a retry signal (19) and a mask signal (31), and an address bus (11).
, a map signal (14), and an enable signal (18) as inputs, a memory (4) whose data terminal is connected to the data bus (12), whose address terminal is connected to the address bus (11), and whose data terminal is connected to the data bus (12). A CPU (1) that is connected to a bus (12), outputs a strobe signal (13) that becomes active when a bus cycle occurs, and receives a retry signal (19) as an input, and a strobe signal (13) and a mask signal (31). 1. A data bus contention avoidance circuit for an ICE, characterized in that it is provided with a gate (6) which receives a DS signal as an input and outputs a DS signal.