JP2850831B2 - Debug device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a debugging device, and more particularly, to a debugging device having an emulation function.

[0002]

2. Description of the Related Art Generally, a debugging device having an emulation function is used for debugging at the time of designing and developing a system to which a microprocessor is applied. These debugging devices incorporate an emulation memory that is a substitute memory for a debug target system (target system). In a system development stage, if the memory of the target system cannot be used, the emulation memory is used instead. . At this time, in consideration of the case where the emulation memory is slower than the DRAM employed in the target system, at the time of the above emulation memory access, the ready signal from the target system for controlling the end of the bus cycle is masked and the emulation memory is internally processed. The required access time is secured by using the generated ready signal.

In this type of debugging device, debugging is performed using an emulation memory built in the debugging device, and a target system is operated before and after execution of debugging. That is, the DRA in the target system
If the data stored in M is destroyed, operation using this target system becomes impossible after the end of debugging. Therefore, during emulation, the DRA
This needs to be refreshed without using M. However, in a conventional debug device of this type, which realizes refresh by extending a bus cycle using a ready signal such as CBR refresh described later,
There is a problem that the bus cycle cannot be extended during the emulation and the data stored in the DRAM is destroyed.

[0004] Target system 2 using DRAM
Referring to FIG. 4, which shows a block diagram of a conventional debugging device 1 for debugging a program, the conventional debugging device 1 outputs a bus cycle start signal BCYST to start a bus cycle, and responds to the supply of a ready signal IRDY. A microprocessor 11 for ending the cycle, an emulation memory 12 which is a substitute memory for the DRAM 22 of the target system being debugged, an OR gate O11,
And an AND gate A11.

The target system 2 includes a DRAM 21 as a main memory and a DRA for controlling writing and reading of the DRAM.
An M control circuit 22 and a ready signal output circuit 23 that outputs a ready signal are provided.

Next, the operation of the conventional debug device will be described with reference to FIG. 4. First, the microprocessor 11 operating in response to the supply of the system clock signal CLK starts the bus cycle in which the active state is at the L level. The bus cycle is started by outputting signal BCYST, and the bus cycle is ended in response to supply of ready signal IRDY. In the target system 2 equipped with the DRAM 21, the signal BCYST is received by the DRAM control circuit 22, and the DRAM control circuit 22 supplies the row address strobe signal RAS and the column address strobe signal CAS to the DRAM 21 in response to the supply of the signal BCYST. . The DRAM 21 receives the supplied signals RAS, C
At each fall of AS, a row address and a column address are respectively latched and memory access is performed. Also, DR
The AM control circuit 22 outputs a ready enable signal RD for permitting the ready signal output circuit 23 to output a ready signal.
YEN is output, and the ready signal output circuit 23 outputs the ready signal TRDY in response to the supply of the signal RDYEN.

Next, the mask signal MASK which becomes H level in the active state becomes active during the break of the microprocessor 11 or at the time of accessing the emulation memory, and in response to the activation of the mask signal MASK, the AND gate A11 becomes active. Ready signal TR
DY is masked. The OR gate O11 performs an OR operation on the output of the AND gate A11 and the ready signal ERDY output from the emulation memory 12, and outputs a ready signal IRDY to be supplied to the microprocessor 11.

As is well known, in a normal memory access of a DRAM, the RAS signal is first activated before the C signal is activated.
The AS signal is activated. CA before RAS signal
A refresh operation that automatically counts up a refresh address counter built in the device by activating the S signal is called CBR refresh.

The operation of the conventional debug device will be described with reference to FIG. 5 which is a timing chart showing the CBR refresh operation of the debug device 1 and the target system 2. The signal BCYST is synchronized with the system clock signal CLK by one clock. During this time, the bus cycle is started, and then the signal IRDY becomes active, thereby ending this one bus cycle. A period during which the signal BCYST is in the active state is called a T1 cycle, and a period until the bus cycle ends is called a T2 cycle.

In the first bus cycle shown in FIG. 5, a refresh operation is inserted in a normal memory access. DR
The AM control circuit 22 makes the signal RDYEN inactive at the start of the second T2 cycle, causes the ready signal output circuit 23 to wait for the output of the signal TRDY, and keeps the signal CAS active before the signal RAS, and
The start of the refresh operation is notified to M21. After three clocks, the refresh ends, the signal RDYEN becomes active, and the ready signal output circuit 23 outputs the signal TRDY. Normally at the time of memory access, the mask signal MAS
K is inactive, and the signal T
RDY is supplied and the bus cycle ends.

The next bus cycle is at the time of emulation memory access. As in the normal memory access, the signal RDYEN becomes inactive at the start of the second T2 cycle, the DRAM control circuit 22 declares the start of refresh, and activates the signal CAS before the signal RAS. However, since the emulation memory is being accessed, the mask signal MASK becomes active,
The signal TRDY is masked, and the signal E
RDY is selected. Since the signal ERDY is output independently of the DRAM control circuit 22, the signal IRDY is output even when the signal RDYEN is inactive, and the bus cycle ends before the refresh operation is completed. As a result, the DRAM 21 ends in the state of being refreshed, and the data is destroyed.

[0012]

The above-mentioned conventional debugging device considers the case where the emulation memory is slower than the DRAM employed in the target system. Since the ready signal from the target system for controlling the end of the cycle is masked, a refresh operation cannot be inserted by operating the ready signal of the target system, and there is a disadvantage that the data in the DRAM is destroyed.

[0013]

SUMMARY OF THE INVENTION A debugging device according to the present invention includes an emulation microprocessor for controlling a bus cycle and an emulation memory serving as a substitute memory for a main memory of a system to be debugged. A debug device, wherein the emulation microprocessor controls the end of the bus cycle in response to the supply of a first ready signal, wherein a second ready signal output by the debug target system and a second ready signal generated in the debug device are generated. The activation timing of each of the third ready signals to be activated is compared with each other to detect a predetermined timing relationship, and either or both of the second and third ready signals are selected, and the first ready signal is selected. It includes a Rede I signal selection circuit for outputting a signal It is configured.

[0014]

FIG. 4 shows an embodiment of the present invention.
Referring to FIG. 1, in which common components are denoted by common reference characters / numerals and similarly indicated by blocks, a debugging device 1A of this embodiment shown in FIG. In addition to the emulation memory 12, the activation timings of the ready signals TRDY and ERDY are compared. If the signal TRDY is later, the signal TRDY is compared with the signal ERDY if the signal ERDY is later. When the signals TRDY and ERDY are simultaneous, a ready signal selection circuit 13 for selecting these signals TRDY and ERDY as the signal IRDY is provided.

Referring to FIG. 2 showing a detailed circuit diagram of the ready signal selection circuit 13,
The emulation ready selection circuit 31 detects that the activation of the emulation ready signal ERDY is later and generates the signal UERDY, and detects that the activation of the target delay signal TRDY is later. Ready selection circuit 3 for generating signal UTRDY
2 and an output circuit 33 that takes the logical sum of the signals UERDY and UTRDY and outputs a signal IRDY.

The emulation ready selection circuit 31
NOR of signals BTRDY and SERDY (NOR)
NOR gate N for performing operation and outputting signal STRRST
31, a signal STRST supplied to the set input and a signal STRD supplied to the clock input and the signal BCYST supplied to the clock input
A flip-flop F31 for outputting Y and a signal STRD
An AND gate A31 that performs a logical product (AND) operation of Y and the signal ERDY and outputs a signal UERDY.

The target ready selection circuit 32 outputs the signal T
An inverter I31 that inverts RDY and outputs an inverted ready signal BTRDY, and an AND signal BTRDY and ERDY
An AND gate A32 that performs a D operation and outputs a signal EATRDY, and an inverted signal BBCYS by inverting the signal BCYST.
An inverter I32 for outputting T, a flip-flop F3 for receiving the signal EACY in the clock input and supplying the signal BBCYST in the reset input and outputting the signal SERDY.
2 and an AND gate A23 that performs an AND operation on the signals SERDY and TRDY and outputs a signal UTRDY.

The output circuit 33 outputs the signals UERDY, UTR
An OR gate O31 that performs an OR operation of DY and outputs a signal IRDY is provided.

Next, the operation of the ready signal selection circuit 13 according to the present embodiment will be described with reference to FIG. 2. The AND gate A32 of the target ready selection circuit 32 includes an inverted signal BTRDY of the output of the inverter I31 and a signal ERD.
A logical AND with Y is taken, and an active signal EATRDY is output while the signal ERDY is active. Flip-flop F32 outputs H-level signal SERDY at the rising edge of signal EATRDY. Signal SERD
Y is reset when the signal BBCYST becomes H level. That is, the signal SERDY is a signal that becomes active H level until the start point of the next bus cycle after the signal ERDY becomes active alone.

N of the emulation ready selection circuit 31
OR gate N31 outputs signal STRRST as a result of a NOR operation of signal BTRD and signal SERDY. The flip-flop F31 uses the signal STRRST as a set signal, outputs a signal STRDY which becomes L level when the signal BCYST falls, and supplies the signal STRDY to the AND gate A31.
The AND gate A31 outputs the signal STRDY and the signal ERDY.
And outputs a signal UERDY. Output circuit 3
The three OR gates O31 are provided with a signal UERDY and a signal UTR.
The logical sum of DY is calculated, and a signal IRDY is generated and supplied to the microprocessor 11.

Next, the operation will be described with reference to FIG.
(A) shows the operation when the signal TRDY becomes active first and the signal ERDY becomes active later.
At the rise of the second clock signal CLK, the bus cycle start signal BCYST becomes active. The flip-flop F32 is reset at the fall of the signal BCYST, and the signal SERD output from the flip-flop F32 is output.
Y goes to L level. At the rising of the second clock signal CLK, the signal BCYST becomes inactive.
Flip-flop F31 uses signal BCYST as a clock signal, holds a signal at L level at the rising edge, and its output signal STRDY attains L level. At the rising of the third clock signal CLK, first, the signal TRDY becomes active first. The signal STRRST is the signal BTR
It is the inverted value of the logical sum of DY and SERDY, and the signal SER
Since DY is at the L level, it becomes active while the signal TRDY is active. Flip-flop F31 sets output signal STRDY to H level in response to transition of set input signal STRRST to active. The signal ERDY becomes active at the rising of the fourth clock signal CLK, and the signal TRDY becomes inactive. Signal E
Since ATRDY is the logical product of the signals BTRDY and ERDY, it is active while the signal ERDY is active.
Since the flip-flop F32 holds the signal at the H level at the rise of the signal EATRDY, the output signal SERDY is output.
Holds the active state until the start of the next bus cycle in which the signal BCYST becomes active. Signal STRD
Since Y is held until the signal BCYST rises, the signal UE which is the logical product of the signals STRDY and ERDY
RDY is active while signal ERDY is active. Since the signal UTRDY is a logical product of the signals SERDY and TRDY, the signal UTRDY remains inactive. Therefore, the signal IR supplied from the output circuit 33 to the microprocessor 11
Since DY is the logical product of the signals UERDY and UTRDY,
Active while signal UERDY is active.

Next, referring to FIG. 3B which is a time chart showing the operation when signal ERDY becomes active first and signal TRDY becomes active with a delay, the bus rises at the rising edge of the first clock signal CLK. When the cycle start signal BCYST becomes active, the signal SERDY
Is reset at the fall of the signal BCYST.
The signal STRD at the rising of the second clock signal CLK
Y is reset. When the signal ERDY becomes active first at the rising of the third clock signal CLK, the signal EATRDY becomes active while the signal ERDY is active because the signal TRDY is inactive. Signal E
At the rise of ATRDY, output signal SERDY of flip-flop F32 attains H level and is held until the start of the next bus cycle. Since the signal STRRST, which is the NOR of the signals SERDY and BTRDY, remains inactive, the signal STRDY remains at the L level. Therefore, the signal UERDY does not become active. As described above, the signal UTRDY is the signal SE
Since the signal SERDY is active until the start of the next bus cycle after the activation of the signal ERDY, the signal SERDY is active while the signal TRDY is active. Therefore, the output signal IRDY is
Active while signal UTRDY is active.

Next, referring to FIG. 3C showing a time chart of the operation when the signals ERDY and TRDY are simultaneously activated, the signal BCYST becomes active at the rising edge of the first clock signal CLK. Signal SERD reset at the falling edge of BCYST
Y becomes inactive. Second clock signal CL
At the rise of K, the signal BCYST becomes inactive, and at the rise of the signal BCYST, the signal STRDY becomes inactive. At the rising of the third clock signal CLK, the signals TRDY and ERDY are simultaneously activated. Therefore, the signal EATRDY remains inactive. Therefore, the output signal SERD of the flip-flop F32 using the signal EATRDY as a clock signal
Y also remains inactive. As a result, the signal ST
RRST is active while signal TRDY is active. The output signal STRDY of the flip-flop F31 set by the signal STRRST becomes active and is held until the end of the T1 cycle of the next bus cycle. Signal EARD of AND of signals STRDY and ERDY
Y is active while signal ERDY is active. On the other hand, the signal U of the logical product of the signals SERDY and TRDY
TRDY remains inactive. Therefore, the output signal IRDY is active while the signal UERDY is active.

As described above, the signal TRDY and the signal ERDY
In response to the timing before and after each of the timings, a signal that has become active later is selected as the output ready signal IRDY.

[0025]

As described above, the debugging device of the present invention compares the activation timings of the ready signals TRDY and ERDY, detects that they are in a predetermined timing relationship, and detects any of these signals TRDY and ERDY. A ready signal selection circuit for selecting one or both of them and outputting it as a ready signal IRDY is provided, so that the ready signal ERDY in the debug device is used during normal emulation memory access, and the target system is used during extended bus cycles for refresh. Ready signal TR
Since DY is enabled, the CB can be used during emulation memory access without deteriorating the performance of the debug device.
There is an effect that R refresh can be performed normally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a debugging device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a ready signal selection circuit of the present embodiment.

FIG. 3 is a time chart illustrating an example of an operation in the debugging device according to the present embodiment;

FIG. 4 is a block diagram illustrating an example of a conventional debugging device.

FIG. 5 is a time chart showing an example of the operation of the conventional debugging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Debugger 2 Target system 11 Microprocessor 12 Emulation memory 13 Ready signal selection circuit 21 DRAM 22 DRAM control circuit 23 Ready signal output circuit 31 Emulation ready selection circuit 32 Target delay processing circuit 33 Output circuit A11, A31-A33 AND circuit F31 , F32 Flip prop I31, I32 Inverter N31 NOR circuit O11, O31 OR circuit

Claims (3)

(57) [Claims] 1. An emulation microprocessor for controlling a bus cycle and an emulation memory serving as a substitute memory for a main memory of a system to be debugged, having an emulation function for a microprocessor, wherein the emulation microprocessor has a first emulation function. A debug device for controlling the end of the bus cycle in response to the supply of a ready signal, wherein activation of a second ready signal output by the debug target system and a third ready signal generated in the debug device comprises detecting and Rede I signal selection circuit for outputting as these second, the select one or both of the third ready signal first ready signal that compares the timing is a predetermined timing relationship A debugging device, characterized in that: Wherein said Rede I signal selection circuit, the second,
2. The debugging device according to claim 1, wherein one of the third ready signals having a later activation timing or, when the activation timings are simultaneous, both are selected as the first ready signals. Wherein the Rede I signal selection circuit, target ready for the second ready signal to generate a first ready candidate signal by detecting that the activation timing later than the third ready signal A selection circuit, an emulation ready selection circuit that detects that the third ready signal is activated later than the second ready signal and generates a second ready candidate signal; 2. The debugging device according to claim 1, further comprising: a ready signal output circuit that outputs a logical sum operation result of two ready candidate signals as the first ready signal.