JPS54105902A - Communication control device - Google Patents

Communication control device

Info

Publication number
JPS54105902A
JPS54105902A JP1240678A JP1240678A JPS54105902A JP S54105902 A JPS54105902 A JP S54105902A JP 1240678 A JP1240678 A JP 1240678A JP 1240678 A JP1240678 A JP 1240678A JP S54105902 A JPS54105902 A JP S54105902A
Authority
JP
Japan
Prior art keywords
register
data
division
circuit
coincidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1240678A
Other languages
Japanese (ja)
Inventor
Kiyoyasu Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1240678A priority Critical patent/JPS54105902A/en
Publication of JPS54105902A publication Critical patent/JPS54105902A/en
Pending legal-status Critical Current

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  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE: To secure the continuous return test just through setting the original data by comparing the data drawn into the receiving register via the arithmetic circuit with the held corresponding transmitting data and carrying out the next division when a coincidence is obtained through the comparison.
CONSTITUTION: Division circuit 7 is started with application of the original data, and the division result is set to communication register 9 as the test data to be then sent to the communication system. Thus, the division is repeated via register 6 and 5. On the other hand, the data returned from the reception circuit is changed to the parallel row through parallel-series conversion register 12 to be drawn into receiving register 11. Here arithmetic circuit 8 compares the data drawn into register 11 with the corresponding receiving data to be held at register 5, and the next division is carried out at circuit 7 when a coincidence is obtained in the above comparison. In case no coincidence is obtained, the division is stopped, and the error is displayed via register 4. Thus, the continuous return test is possible for the communication system of various patterns just by setting the original data.
COPYRIGHT: (C)1979,JPO&Japio
JP1240678A 1978-02-08 1978-02-08 Communication control device Pending JPS54105902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1240678A JPS54105902A (en) 1978-02-08 1978-02-08 Communication control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1240678A JPS54105902A (en) 1978-02-08 1978-02-08 Communication control device

Publications (1)

Publication Number Publication Date
JPS54105902A true JPS54105902A (en) 1979-08-20

Family

ID=11804372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1240678A Pending JPS54105902A (en) 1978-02-08 1978-02-08 Communication control device

Country Status (1)

Country Link
JP (1) JPS54105902A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155540U (en) * 1986-03-25 1987-10-02
JPH02279039A (en) * 1989-04-20 1990-11-15 Fujitsu Ltd Internal diagnostic system for local area network controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155540U (en) * 1986-03-25 1987-10-02
JPH0450681Y2 (en) * 1986-03-25 1992-11-30
JPH02279039A (en) * 1989-04-20 1990-11-15 Fujitsu Ltd Internal diagnostic system for local area network controller

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