JPS57172515A - Pedestal clamping circuit - Google Patents

Pedestal clamping circuit

Info

Publication number
JPS57172515A
JPS57172515A JP56057562A JP5756281A JPS57172515A JP S57172515 A JPS57172515 A JP S57172515A JP 56057562 A JP56057562 A JP 56057562A JP 5756281 A JP5756281 A JP 5756281A JP S57172515 A JPS57172515 A JP S57172515A
Authority
JP
Japan
Prior art keywords
video signal
level
input
input video
invariably
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56057562A
Other languages
Japanese (ja)
Inventor
Tadashi Kojima
Shigeru Tomidokoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56057562A priority Critical patent/JPS57172515A/en
Publication of JPS57172515A publication Critical patent/JPS57172515A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10046Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10203Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter baseline correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To steady the DC level of an input video signal invariably without reference to the state of a transmission line, by fixing a pedestal level while an input system for a video signal is connected directly. CONSTITUTION:An input video signal applied to an input terminal IN21 is branched into three through a video amplifier 21 for low output impedance, and one of them is supplied to one input terminal of an adder 22. A pedestal level holds output from sample holding circuit 23 is supplied to the other input terminal of the adder 22 through an inverting amplifier 25 and then added there to the input video signal. The input video signal has variation in DC level, so the pedestal level is corrected into a level ''0'' invariably, so that a data part in the input video signal is fixed invariably in terms of direct current.
JP56057562A 1981-04-16 1981-04-16 Pedestal clamping circuit Pending JPS57172515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56057562A JPS57172515A (en) 1981-04-16 1981-04-16 Pedestal clamping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56057562A JPS57172515A (en) 1981-04-16 1981-04-16 Pedestal clamping circuit

Publications (1)

Publication Number Publication Date
JPS57172515A true JPS57172515A (en) 1982-10-23

Family

ID=13059265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56057562A Pending JPS57172515A (en) 1981-04-16 1981-04-16 Pedestal clamping circuit

Country Status (1)

Country Link
JP (1) JPS57172515A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0318038A2 (en) * 1987-11-26 1989-05-31 Sony Corporation Circuit for separating simultaneously reproduced PCM and ATF signals having at least partially overlapping frequency bands
EP0320022A2 (en) * 1987-12-11 1989-06-14 Sanyo Electric Co., Ltd. DC Restoration circuit for restoring and compensating for low frequency component lost in digital signal transmission system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0318038A2 (en) * 1987-11-26 1989-05-31 Sony Corporation Circuit for separating simultaneously reproduced PCM and ATF signals having at least partially overlapping frequency bands
EP0320022A2 (en) * 1987-12-11 1989-06-14 Sanyo Electric Co., Ltd. DC Restoration circuit for restoring and compensating for low frequency component lost in digital signal transmission system

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