JPS5574620A - Noise suppression system for data bus - Google Patents

Noise suppression system for data bus

Info

Publication number
JPS5574620A
JPS5574620A JP14932978A JP14932978A JPS5574620A JP S5574620 A JPS5574620 A JP S5574620A JP 14932978 A JP14932978 A JP 14932978A JP 14932978 A JP14932978 A JP 14932978A JP S5574620 A JPS5574620 A JP S5574620A
Authority
JP
Japan
Prior art keywords
clp
lines
data bus
circuit
low level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14932978A
Other languages
Japanese (ja)
Other versions
JPS589446B2 (en
Inventor
Yoshiji Fukae
Tomohide Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP53149329A priority Critical patent/JPS589446B2/en
Publication of JPS5574620A publication Critical patent/JPS5574620A/en
Publication of JPS589446B2 publication Critical patent/JPS589446B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Prevention Of Errors In Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Noise Elimination (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To reject the noise on the data bus, by keeping the tag line which is made active with the drive circuit, at the active level potential compulsively for the time not in excess of the continuity time of signal over the entire lines.
CONSTITUTION: The processor 1 and the main memories 21, 22... are connected to the data bus consisting of the tag line 32 and the data lines (not shown). The reception circuit R and the drive circuit D connected to the tag lines of each memory are provided with the low level clamp circuits CLP1, CLP2. After the low level active input signal is incoming to the input of the reception circuit R, the clamp CLP1 clamps the tag lines at low level for the set time of the monostable circuit MM1. The clamp circuit CLP2 acts similarly and similar operation is made at other memories, it is stable to the noise from the data lines.
COPYRIGHT: (C)1980,JPO&Japio
JP53149329A 1978-11-30 1978-11-30 Data bus noise suppression method Expired JPS589446B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53149329A JPS589446B2 (en) 1978-11-30 1978-11-30 Data bus noise suppression method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53149329A JPS589446B2 (en) 1978-11-30 1978-11-30 Data bus noise suppression method

Publications (2)

Publication Number Publication Date
JPS5574620A true JPS5574620A (en) 1980-06-05
JPS589446B2 JPS589446B2 (en) 1983-02-21

Family

ID=15472722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53149329A Expired JPS589446B2 (en) 1978-11-30 1978-11-30 Data bus noise suppression method

Country Status (1)

Country Link
JP (1) JPS589446B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230473A (en) * 1984-04-28 1985-11-15 ホリ−株式会社 Suspension type scaffold apparatus
JPS62133251A (en) * 1985-12-03 1987-06-16 三井建設株式会社 Moving suspension scaffold

Also Published As

Publication number Publication date
JPS589446B2 (en) 1983-02-21

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