JPS6453651A - By-pass device - Google Patents

By-pass device

Info

Publication number
JPS6453651A
JPS6453651A JP21097787A JP21097787A JPS6453651A JP S6453651 A JPS6453651 A JP S6453651A JP 21097787 A JP21097787 A JP 21097787A JP 21097787 A JP21097787 A JP 21097787A JP S6453651 A JPS6453651 A JP S6453651A
Authority
JP
Japan
Prior art keywords
data
time
pass
delaying
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21097787A
Other languages
Japanese (ja)
Other versions
JPH0687563B2 (en
Inventor
Koyo Oyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21097787A priority Critical patent/JPH0687563B2/en
Publication of JPS6453651A publication Critical patent/JPS6453651A/en
Publication of JPH0687563B2 publication Critical patent/JPH0687563B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To assure the continuity of data and to execute the by-pass without delaying, by providing a second by-pass route not accompanied by the delaying. CONSTITUTION:At a time t0, a first by-pass route 2 is connected to a ring- shaped bus 8, and at a time t1, the delaying of data D1 is executed. At a time tN+1, the data D1 are outputted to the ring-shaped bus 8 through the delaying for the prescribed number of words and simultaneously, a flag pattern continuous counter 6 counts a contrinuous receiving detectingsignal N-2 times. At a time tN+2, data D2 are outputted to the bus 8, and on the other hand, the counter 6 counts N-1 times. At time tN+3, the counter 6 counts N times, a by- pass switching signal is outputted from the counter 6 and a by-pass route is switched to a second by-pass route 3. Thereafter, the output is executed from data D3 to the bus 8 without delay.
JP21097787A 1987-08-24 1987-08-24 Bypass device Expired - Lifetime JPH0687563B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21097787A JPH0687563B2 (en) 1987-08-24 1987-08-24 Bypass device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21097787A JPH0687563B2 (en) 1987-08-24 1987-08-24 Bypass device

Publications (2)

Publication Number Publication Date
JPS6453651A true JPS6453651A (en) 1989-03-01
JPH0687563B2 JPH0687563B2 (en) 1994-11-02

Family

ID=16598262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21097787A Expired - Lifetime JPH0687563B2 (en) 1987-08-24 1987-08-24 Bypass device

Country Status (1)

Country Link
JP (1) JPH0687563B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0433438A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd Transmission line changeover system for local area network
US7880806B2 (en) 2005-04-14 2011-02-01 Sony Corporation Imaging operation controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0433438A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd Transmission line changeover system for local area network
US7880806B2 (en) 2005-04-14 2011-02-01 Sony Corporation Imaging operation controller

Also Published As

Publication number Publication date
JPH0687563B2 (en) 1994-11-02

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