JPS5760758A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5760758A
JPS5760758A JP13517780A JP13517780A JPS5760758A JP S5760758 A JPS5760758 A JP S5760758A JP 13517780 A JP13517780 A JP 13517780A JP 13517780 A JP13517780 A JP 13517780A JP S5760758 A JPS5760758 A JP S5760758A
Authority
JP
Japan
Prior art keywords
data transmission
clock signal
priority determining
priority
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13517780A
Other languages
Japanese (ja)
Other versions
JPS6348463B2 (en
Inventor
Takashi Okonogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP13517780A priority Critical patent/JPS5760758A/en
Publication of JPS5760758A publication Critical patent/JPS5760758A/en
Publication of JPS6348463B2 publication Critical patent/JPS6348463B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To make a data transmission bus efficient, by setting clock intervals to the 1/n of a time when even a terminal equipment connected finally can obtain the data transmission right, and by causing every (n-1)th clock signal to correspond to n-number respective priority determining lines, in case that data is transferred in order of priority. CONSTITUTION:Plural terminal equipments T1-Ti are connected in series by priority determining signal lines 41 and 42, and data is transmitted to a data transmission bus line 2 in order of priority synchronously with the clock signal from a clock signal line 3 from a bus control part 1. Clock intervals for this data transmission are set to the 1/n of intervals when even the terminal equipment Ti connected finally can obtain the data transmission right. N-number priority determining signal lines 41 and 42 are provided, and every (n-1)th clock signal is caused to correspond to respective priority determining signal lines 41 and 42, thus improving the use efficiency of the data transmission bus 2.
JP13517780A 1980-09-30 1980-09-30 Data transfer system Granted JPS5760758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13517780A JPS5760758A (en) 1980-09-30 1980-09-30 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13517780A JPS5760758A (en) 1980-09-30 1980-09-30 Data transfer system

Publications (2)

Publication Number Publication Date
JPS5760758A true JPS5760758A (en) 1982-04-12
JPS6348463B2 JPS6348463B2 (en) 1988-09-29

Family

ID=15145628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13517780A Granted JPS5760758A (en) 1980-09-30 1980-09-30 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5760758A (en)

Also Published As

Publication number Publication date
JPS6348463B2 (en) 1988-09-29

Similar Documents

Publication Publication Date Title
EP0112560A3 (en) A signalling input/output processing module for a telecommunication system
DE3177087D1 (en) Data processing system with a plurality of input/output buses
JPS5760758A (en) Data transfer system
KR880001020B1 (en) Interface unit for a modular telecommunication system
JPS57135538A (en) Series data transmission system
JPS5725027A (en) Data transmission controlling system of plural controllers
JPS5443429A (en) Multiple series input process system
JPS5396605A (en) Data transmission system
JPS55127607A (en) Free-program type process controller
JPS5734234A (en) Extension of data bus
JPS57138240A (en) Hairpin network
JPS5643850A (en) Intermultiplexer communication control system
EP0067431A3 (en) Network with a number of optical signal transmission lines interconnectable by optical mixers, and arrangement for bus access control of a number of devices using a bus in a network constructed as a passive bus system by means of at least one optical mixer, especially for multicalculator systems
JPS56143040A (en) Keyboard controlling system
JPS53131706A (en) Automatic telephone exchange system
JPS5289344A (en) Data collecting and transmitting system
JPS5799844A (en) Serial multiplex data transfer system
JPS6462046A (en) Multiple transmission equipment
JPS5336108A (en) Circuit connection system
JPS57133735A (en) Data transmission device
JPS53108249A (en) Input/output interface system
JPS56105504A (en) Control device
JPS56119564A (en) Key telephone system
JPS544313A (en) Speed control system of alternating current motor
JPS549384A (en) Centralized monitoring system