JPS5725027A - Data transmission controlling system of plural controllers - Google Patents

Data transmission controlling system of plural controllers

Info

Publication number
JPS5725027A
JPS5725027A JP9874580A JP9874580A JPS5725027A JP S5725027 A JPS5725027 A JP S5725027A JP 9874580 A JP9874580 A JP 9874580A JP 9874580 A JP9874580 A JP 9874580A JP S5725027 A JPS5725027 A JP S5725027A
Authority
JP
Japan
Prior art keywords
subsidiary
line
transmission request
signal line
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9874580A
Other languages
Japanese (ja)
Inventor
Mitsunobu Isobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9874580A priority Critical patent/JPS5725027A/en
Publication of JPS5725027A publication Critical patent/JPS5725027A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To decrease the number of control lines for securing a transmitting circuit, by coupling a main controller and plural subsidiary controllers to a common bus by control lines of 3 kinds such as clock, transmission request and transmission permission, and executing a time division multiplex control. CONSTITUTION:A main controller 201 and N sets of subsidiary controller groups 202-204 are connected by control lines of 3 kinds such as a clock signal line 205, a transmission request line 206 and a transmission permission line 207, as well as a data signal line 208. In order to detect whether a transmission request from a subsidiary device exists or not, the device 201 sends out N pieces of pulse trains to the subsidiary device group through the signal line 205. Each subsidiary device receives and counts the pulse train, and sends back an answer to the device 201 as to whether the transmission request exists or not, through the request line 206, by a clock timing which has coincided with its own device number. The device 201 checks an ordinal number of a pulse train of the transmission request which is sent back, stores a number of the request device, and sends out a transmission permission pulse to the permission line 207 by a timing of a device number to be answered, of each pulse on the signal line 205, in accordance with a prescribed priority rank, by which the transmitting circuit is secured.
JP9874580A 1980-07-21 1980-07-21 Data transmission controlling system of plural controllers Pending JPS5725027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9874580A JPS5725027A (en) 1980-07-21 1980-07-21 Data transmission controlling system of plural controllers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9874580A JPS5725027A (en) 1980-07-21 1980-07-21 Data transmission controlling system of plural controllers

Publications (1)

Publication Number Publication Date
JPS5725027A true JPS5725027A (en) 1982-02-09

Family

ID=14228003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9874580A Pending JPS5725027A (en) 1980-07-21 1980-07-21 Data transmission controlling system of plural controllers

Country Status (1)

Country Link
JP (1) JPS5725027A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024664A (en) * 1983-03-29 1985-02-07 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Bus interface unit
JPS62134747A (en) * 1985-12-02 1987-06-17 バロ−ス・コ−ポレ−シヨン Data processing system
JPS62139065A (en) * 1985-12-13 1987-06-22 Fuji Electric Co Ltd Bus arbitration system
JPS62226258A (en) * 1986-03-28 1987-10-05 Nec Corp Bus control system
JP2012064021A (en) * 2010-09-16 2012-03-29 Ricoh Co Ltd Communication system, master device and slave device, and communication method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024664A (en) * 1983-03-29 1985-02-07 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Bus interface unit
JPS62134747A (en) * 1985-12-02 1987-06-17 バロ−ス・コ−ポレ−シヨン Data processing system
JPS62139065A (en) * 1985-12-13 1987-06-22 Fuji Electric Co Ltd Bus arbitration system
JPS62226258A (en) * 1986-03-28 1987-10-05 Nec Corp Bus control system
JP2012064021A (en) * 2010-09-16 2012-03-29 Ricoh Co Ltd Communication system, master device and slave device, and communication method

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