JPS62226258A - Bus control system - Google Patents

Abstract

PURPOSE:To attain the bus using right with a simple constitution by using a single bus use request signal line, the system clock and the system reset signal. CONSTITUTION:Plural bus use requesters 12 share a single bus use request signal line 21. Each requester 12 checks whether the line 21 is busy or not when receiving a bus use request and sets the line 21 under a busy state through a control part 22 as long as the line 21 is not busy. Here the timing allocated to all requesters 12 by the system reset signal and the system clock used to secure the system synchronization is utilized when the part 22 checks the using state of the line 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system in which there are a plurality of bus use request sources using a common bus, and particularly to a method for controlling the right to use a common bus.

[Conventional technology]

Conventionally, a system using a common bus has a common bus (including a data bus, an address bus, etc.) 11, as shown in FIG. each connected. Bus use request source 1
2 and the bus control unit 13 are connected by a bus use request signal line 14 and a bus use permission signal line 15.

In this way, in a conventional system that uses a common bus, in order to acquire the right to use the bus, each bus request source 12 has to
It includes a bus use request signal line 14 and a bus use permission signal line (hereinafter referred to as an acknowledge signal line). The bus control unit 13 controls the bus usage right by managing a plurality of bus usage request signals and returning an acknowledge signal.

[Problem that the invention seeks to solve]

As the number of bus request sources increases, the number of signal lines increases, and in systems packaged for each bus request source, the priority of bus use requests is usually uniquely determined by the mounting slot. There is a drawback.

An object of the present invention is to eliminate the above-mentioned drawbacks and to control bus usage rights with a simple configuration.

Moreover, it is an object of the present invention to provide a bus control method in which the priority of bus use requests is not fixed.

[Means to solve the problem]

According to the present invention, in a system in which there are a plurality of bus use request sources using a common bus, the plurality of bus use request sources share only one bus use request signal line, and the bus use request source When a bus use request is generated for each bus use request source, each of the bus use requests ".1
<Comprising a control unit that checks whether the signal line is in use, and if not in use, sets the bus use request signal line in use.

The control unit uses timing separately allocated to all bus use request sources by a system clock and a system reset signal for synchronizing the system as the timing to check the usage status of the bus use request signal line. A bus control method is obtained which is characterized by the following.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a bus control system according to an embodiment of the present invention is applied to a system in which there are a plurality of bus request sources 12 using a common bus 11. In this example, 1
A plurality of bus use request sources 12 share the bus use request signal line 21, which only exists. Each of the bus use request sources 12 checks whether or not the bus use request signal line 21 is in use when a bus use request is generated in each bus use request source 12, and if the bus use request signal line 21 is not in use, A control unit 2 comprising a control unit 22 that puts the use request signal line 21 in use.
The timing at which 2 checks the usage status of the bus use request signal line is the system clock for synchronizing the system and the system reset signal. The timing is assigned separately to all the bus use request sources 12 by the system clock and system reset signal for synchronizing the system. use.

Next, the operation of this embodiment will be explained with reference to FIG.

The system clock 31 is supplied to a plurality of bus use request sources 12, and from the time when the system reset signal 2 turns from on to off, every l clock cycle/lz, Sl,
S2. ..., Sn and a logical state are defined. It is assumed that each bus use request source 12 has been assigned a state number to itself in advance by a switch or the like, and that the value of n is also known. n takes a value greater than or equal to the total number of bus use request sources 12, and the same state number cannot be assigned to two or more bus use request sources 12. For example, stay 1
- When a bus use request is generated, the bus use request source 12, which is assigned the number S2, waits until the system clock 31 reaches the 82nd state, and checks the state of the bus use request signal line 21 in the immediately previous state (Sl).

That is, if the state at point (a) is off, the bus use request signal line 21 is turned on in the S2 state, that is, at point (b), and the right to use the bus is obtained. Also, divide S3 state υ
The requested bus use request source 12 similarly checks the status of the bus use request signal line 21 at point (b), but at point (b), the bus use signal line 21 has already been set by another bus use request source 12. Since it is on, it waits until the 9th 83rd state is reached.

Since the bus use request signal line 21 is off at point (e), which is the state immediately before point (d), which is the next 83 states, the bus request signal line 21 is turned off at point (d), which is the ffi, S3 state. The use request signal line 21 is turned on to obtain the right to use the bus. Bus usage rights are distributed according to the above logic.

〔Effect of the invention〕

As explained above, the present invention can control bus usage rights in one way.
This can be realized with a simple configuration using the main bus use request signal line and the system clock and system reset signals that are absolutely necessary for the system. Therefore, not only is there no restriction on the mounting position of the cage, etc., but also the priority of bus requests is smoothed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bus control system according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a block diagram of a conventional bus control system. It is. 11... Common bus, 12... Bus use request source, 21
...Bus use request signal line, 22...Control unit, 31.
...System clock, 32...System reset signal. Figure 1 Busui replacement safety book 1z

Claims (1)

[Claims] 1. In a system in which a plurality of bus request sources using a common bus exist, the plurality of bus request sources share only one bus request signal line, and each of the bus request sources , When a bus use request is issued to each bus use request source, it is checked whether the bus use request signal line is in use or not, and if it is not in use, it is determined that the bus use request signal line is in use. The controller includes a control unit that checks the usage status of the bus use request signal line, and uses a system clock and system reset signal for synchronizing the system to determine the timing for checking the usage of the bus use request signal line for all bus use request sources. A bus control method characterized by the use of separately allocated timing.