JPS6348463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method in which a plurality of terminal devices are connected in series by a data transfer inquiry signal line and data is transferred in the order of connection.

FIG. 1 is a block diagram of an example of a conventional data transfer system of this type. In FIG. 1, 1 is a bus control unit, 2 is a data transfer bus, 3 is a clock signal line, 4 is a data transfer inquiry signal line connecting multiple terminal devices in series, T ₁ , T ₂ . . . T _i is a terminal equipment, l ₁ ,
l ₂ ...l _i is a logic circuit provided in each terminal device.

A block diagram of an example of the logic circuit is shown in FIG. In FIG. 2, 1, 2, 3, and 4 are the same as in FIG. 1, 11 is a bus request control unit, 12 is a data transfer inquiry signal processing unit, 13 is a bus driver,
5 is a bus request signal input terminal, and 16 is a data input terminal.

The data transfer inquiry signal from the bus control unit is applied to the data transfer inquiry signal processing unit 12,
In one terminal device, if a bus request signal is applied to the input terminal 15, the data transfer inquiry signal processing unit 12 is activated in synchronization with the first clock signal.
It is determined that there is a transfer request, and the data transfer inquiry signal line 4 is disconnected to prohibit data transfer from the subsequent terminal device, and the determination information is sent to the bus request control section 11. A requesting signal is generated, and the data applied to the bus driver 13 is transferred to the data transfer bus 2 via the bus driver 13 in response to the next clock signal.

In this way, the logic circuit determines the presence or absence of a data transfer request for each terminal device in the order in which the terminal devices are connected in response to the data transfer inquiry signal and the bus request signal, and transfers data only to the terminal device that has a data transfer request. This circuit makes it possible to transfer data to all subsequent terminal devices.

In this data transfer method in which a plurality of terminal devices are connected in series via the data transfer inquiry signal line 4 and data is transferred in the order in which they are connected in synchronization with a clock signal, the interval between the clock signals is determined by the bus controller 1.
The time required for the data transfer inquiry signal applied to the data transfer inquiry signal line 4 to arrive from the first terminal device T ₁ to the last terminal device T _i must be longer. That is, if the interval between the clock signals is C, then the interval C is t×i, where t is the time required for one terminal device to receive the data transfer inquiry signal and determine whether there is data to be transferred. It is assumed that the data transfer inquiry signal is greater than the sum of the time d during which the data transfer inquiry signal propagates through the data transfer inquiry signal line 4, that is, C≧t×i+d.

However, when one terminal device captures the data transfer inquiry signal using the first clock signal, it transfers the data using the next clock signal, but the data transfer time in devices using this type of data transfer method generally depends on the clock signal. is much shorter than the interval C.

FIG. 3 is a diagram showing an example of the time relationship in which each terminal device synchronizes with a clock signal and transfers data after receiving a data transfer inquiry signal _. When the data transfer inquiry signal is received and it is determined that there is a data transfer request, the data transfer inquiry signal is cut off for all terminal devices connected after terminal device T ₂ , and data transfer is prohibited.
Only _T1 prepares for data transfer within the clock signal interval C, transfers data for a time corresponding to the shaded area shown in FIG. 3 in synchronization with the second clock signal, and at the same time sends a data transfer inquiry signal. The data is transmitted to the terminal device T ₂ , and the data of the terminal device T ₂ is transferred in synchronization with the third clock signal as described above. Therefore, the data transfer bus 2 is not used during the time between the data transfer time of the terminal device T ₁ and the data transfer time of the terminal device T ₂ , so that the time usage efficiency of the data transfer bus 2 is reduced. There was a problem with it being bad.

The present invention aims to eliminate such problems and improve the efficiency of use of the data transfer bus 2.

That is, n data transfer inquiry signal lines connecting a plurality of terminal devices T ₁ to T _i in series are provided, and the interval C of the clock signals is set to 1/n, so that a clock signal with a clock signal interval of C/n is generated. The n data inquiry signal lines are sequentially made to correspond to every n-1 data line, and one of the n data transfer inquiry signal lines is connected in synchronization with the first clock signal in the terminal device having the transfer data. When receiving the data transfer inquiry signal, the terminal device prepares for data transfer within the time interval C, and synchronizes with the n+1 clock signal and transfers the data within the time interval C/n of the clock signal. The subsequent adjacent terminal device receives the data transfer inquiry signal from another data transfer inquiry signal line in synchronization with the second clock signal, and transfers the data in the same time relationship as above. In this way, the data transfer bus can be used effectively in terms of time by allowing the n terminal devices to sequentially receive the data transfer inquiry signal from the n data transfer inquiry signal lines and perform data transfer. This is how it was done.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of the data transfer method of the present invention. In order to facilitate understanding of the content of the present invention, the block diagram is a block diagram in the case where two data transfer inquiry signal lines are provided. It is.

In FIG. 4, 1 is a bus control unit, 2 is a data transfer bus, 3 is a clock signal line, 4a, 4b are data transfer inquiry signal lines, T ₁ , T ₂ . . . T _i is a terminal device L ₁ ,
L ₂ ...L _i is a logic circuit provided in each terminal device. FIG. 5 is a block diagram of one embodiment of the logic circuit, in which 10 is an n-phase clock generator, the number of phases is the same as the number of data transfer inquiry signal lines, and in this embodiment there are two phases. 11a and 11b are bus request control units, and 12a and 12b are data transfer inquiry signal processing units. The a and b of both parts correspond to the data transfer inquiry signal lines 4a and 4b. 13 is a bus driver, 14 is an OR circuit, 15 is a bus request signal input terminal, and 16 is a data input terminal. Note 21
22a is a bus request signal, and 22a is a reference clock signal (CLK) from the clock signal line 3, which is set to 1/n of the clock signal interval C in the conventional embodiment, and in this embodiment is set to C/2. It is. 22b is generated by the n-phase clock generator 10, and the interval is CLK.
The clock signal (CLK-
1) and 22c are clock signals (CLK-2) whose phase is advanced by the time interval of CLK and which has the same time interval C as CLK-1. Also, 23a,
23b is a bus requesting signal, 24a and 24b are data transfer right acquisition signals, and 25a and 25b are bus use right signals.

FIG. 6 is a diagram showing the time relationship of each signal of each part of the logic circuit in the two terminal devices of this embodiment.

This embodiment will be described below with reference to FIGS. 4, 5, and 6. The two data transfer inquiry signal lines 4a and 4b from the bus control unit 1 are always kept at the logic value "1", and the data transfer inquiry signal processing units 12a and 12b of the logic circuit of each terminal device, respectively.
are connected in series via.

On the other hand, the reference clock signal 22a (CLK) from the clock signal line 3 causes the n-phase clock generator 10 to generate the CLK-1 and CLK-2 and also output the CLK itself. In the first terminal device requesting data transfer, the bus request signal 21 with a logical value of "1" is applied to the signal input terminal 15.
, the bus request control unit 11a outputs the bus request signal 23a to the data transfer inquiry signal processing unit 1 in synchronization with the clock signal CLK-1.
2a and outputs the data transfer right acquisition signal 24a, the logic value of the data transfer inquiry signal line output from the data transfer inquiry signal processing unit 12a is set to "0" to control the data transfer operation of the subsequent terminal device. prohibit. The data transfer right acquisition signal 24a is applied to the bus request control section 11a, which generates a bus use right signal 25a in response to the next clock signal CLK-1, and drives the bus driver 13 via the OR circuit 14. Data input from the data input terminal 16 is transferred to the data transfer bus 2 within the time interval of the reference clock CLK.

During this time, the bus request signal 21 is also being applied to the second bus request control section 11b, but at the same time, the bus requesting signal 23a is also being applied to the second bus request control section 11b.
1b operates in synchronization with the clock signal CLK-2, the bus requesting signal 23b is not output, and the data transfer inquiry signal processing unit 12b does not operate, so the logic value applied to the data transfer inquiry signal line 4b is 1'' signal is transmitted as is to the adjacent second terminal device. Next, assuming that the second terminal device is also requesting data transfer, the data transfer inquiry signal line 4a connected to the second terminal device has a logical value of "0" during the interval C of the clock signal CLK-1. ”, but the data transfer inquiry signal line 4b has a logical value of “1”.

Therefore, the bus request signal 21 of the second terminal device is applied to the bus request control sections 11a and 11b, but the bus request control section 11b to which the clock signal CLK-2 is applied first outputs the bus request signal 23b. do. Since the logical value of the data transfer inquiry signal line 4b connected to the data transfer inquiry signal processing unit 12b to which the signal 23b is applied is "1", the data transfer right acquisition signal 24b is outputted in the same manner as above, The bus use right signal 25 is applied to the bus request control unit 11b, and the next clock signal CLK-2 causes the bus use right signal 25 to be applied to the bus request control unit 11b.
b is generated, drives the bus driver 13 via the OR circuit 14, and after data transfer from the first terminal device,
The data of the second terminal device is immediately transferred. During this time, the data transfer inquiry signal line 4b is kept at the logic value "0" until just before the start of data transfer, but the data transfer inquiry signal line 4a is returned to the logic value "1" by the clock signal CLK-1. The third terminal device performs data transfer processing through the signal line 4a, and can transfer data immediately after the second device transfers data.

The embodiment described above is a case where two data transfer inquiry signal lines are provided, but depending on the relationship between the number of terminal devices connected in series, the processing time of the data transfer inquiry signal, and the time required for data transfer. Therefore, any number of data transfer inquiry signal lines can be provided.

As described in detail above, the present invention provides a data transfer method in which a plurality of terminal devices are connected in series using a data transfer inquiry signal line, and data is transferred in the order in which they are connected in synchronization with a clock signal. By providing n (n≧2) busses, it is possible to expect the effect of providing a data transfer system that improves the usage efficiency of the data transfer bus.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of a conventional data transfer method, Fig. 2 is a block diagram of a conventional logic circuit, and Fig. 3 is a diagram showing the relationship between data transfer inquiry signal processing and data transfer time in the conventional method. , FIG. 4 is a block diagram of an embodiment of the present invention, FIG. 5 is a block diagram of the logic circuit shown in FIG. 4, and FIG. 6 is a diagram showing the time relationship of signals in each part of the logic circuit of the present invention. It is. 1...Bus control unit, 2...Data transfer bus, 3
... Clock signal line, 4, 4a, 4b ... Data transfer inquiry signal line, 10 ... N-phase clock generation section, 11, 11a, 11b ... Bus request control section,
12, 12a, 12b...Data transfer inquiry signal processing unit, 13...Bus driver, 14...OR circuit, 15...Bus request signal input terminal, 16...Data input terminal, _{T1-Ti ...} Terminal Equipment, l ₁ ~ l _i ……
Logic circuit of conventional transfer method, L ₁ to L _i ...Logic circuit of transfer method of the present invention, 21 ... Bus request signal, 2
2a...Reference clock signal (CLK), 22b...
Clock signal (CLK-1), 22c... Clock signal (CLK-2), 23a, 23b... Bus requesting signal, 24a, 24b... Data transfer right acquisition signal, 25a, 25b... Bus use right signal.

Claims (1)

[Scope of Claims] 1. A bus control unit and a plurality of terminal devices are connected in parallel by a data bus and a clock signal line, and connected in series by a data transfer inquiry signal line, A reference clock signal is sent from the control unit to each of the terminal devices, a data transfer inquiry signal is applied to the first terminal device, and data transfer and data transfer inquiry are performed for each terminal device in the order of connection in synchronization with the reference clock signal. In a data transfer method in which a signal is sent to a subsequent terminal device, n (n≧2) data transfer inquiry signal lines are provided between the bus control unit and the plurality of terminal devices, and the reference clock signal line is connected to the reference clock. The data transfer inquiry signal is sequentially output from a plurality of terminal devices and reaches the last connected terminal device, and the data transfer inquiry signal is received at the terminal device,
1/1 of the time required to complete preparations for data transfer
n, and each terminal device generates n-phase clock signals having an interval n times the interval of the reference clock signal, and sequentially generates the n-phase clock signal as the n data transfer inquiry signal. In response to n data transfer inquiry signals sent to the line, data transfer is performed sequentially within the interval of the reference clock signals in synchronization with the n+1 reference clock signal for each inquiry signal. A data transfer method characterized by: