JPS5734234A - Extension of data bus - Google Patents

Abstract

PURPOSE:To obtain a data bus extension device with a simple logic circuit without ineffective access time by lowering the frequency of a synchronizing clock signal temporally only in the access time. CONSTITUTION:A basic module 1 is equipped with a CPU2, a memory device 3, a peripheral control 4, and a data bus extension device 5 and the devices are connected each other through a data bus, a bus control signal line group 7 and a synchronizing clock signal line 8. An extension module 9 is equipped with a peripheral control 10 and a data bus extension device 11 and the devices are connected each other through a data bus 6, a bus control signal line group 13 and a clock signal line 14. The modules 1 and 9 are connected through a connection cable 15. When a signal to start the device 3 is sent from the device 10, a clock signal mask circuit attached to the device 5 masks the pulses of a synchronizing clock signal from the CPU2 only by the number of pulses corresponding to the data transmission delay time to lower the frequency of the clock signal temporally. Thus, the ineffective access time is removed with the simple circuit configuration mentioned above.