JPS55121553A - Priority control system of electronic computer system - Google Patents

Priority control system of electronic computer system

Info

Publication number
JPS55121553A
JPS55121553A JP2949879A JP2949879A JPS55121553A JP S55121553 A JPS55121553 A JP S55121553A JP 2949879 A JP2949879 A JP 2949879A JP 2949879 A JP2949879 A JP 2949879A JP S55121553 A JPS55121553 A JP S55121553A
Authority
JP
Japan
Prior art keywords
priority
unit
service request
bus
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2949879A
Other languages
Japanese (ja)
Inventor
Nobuhiko Yamagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2949879A priority Critical patent/JPS55121553A/en
Publication of JPS55121553A publication Critical patent/JPS55121553A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make higher the priority of a unit, which is disallowed to use a bus for a long time after sending a service request, according to its latency time, by providing a system with flexibility by making it possible to set free the bus service priority among various unit without deciding on it unconditionally.
CONSTITUTION: Timer unit 12, provided inside priority decision circuit A, is supplied with a bus service request signal from priority control circuit 6 of various units 4 via control signal line 8. Unit 12 counts the elapse time since the bus service request signal and transfers information on it to priority correcting circuit 14 via data path 13 while transferring the existence of a bus service request from various unit 4 to priority decision circuit 16 via signal line 15. On the basis of information on the priority determined by circuit 14 and the elapse time from unit 12, circuit 16 sends a bus service request signal and then finds one of the units with the highest priority and to output its discrimination code while allowing it to use the bus by transferring a trigger signal to the unit.
COPYRIGHT: (C)1980,JPO&Japio
JP2949879A 1979-03-14 1979-03-14 Priority control system of electronic computer system Pending JPS55121553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2949879A JPS55121553A (en) 1979-03-14 1979-03-14 Priority control system of electronic computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2949879A JPS55121553A (en) 1979-03-14 1979-03-14 Priority control system of electronic computer system

Publications (1)

Publication Number Publication Date
JPS55121553A true JPS55121553A (en) 1980-09-18

Family

ID=12277734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2949879A Pending JPS55121553A (en) 1979-03-14 1979-03-14 Priority control system of electronic computer system

Country Status (1)

Country Link
JP (1) JPS55121553A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02110651A (en) * 1988-10-19 1990-04-23 Pfu Ltd Bus priority changing processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02110651A (en) * 1988-10-19 1990-04-23 Pfu Ltd Bus priority changing processing system

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