KR20070081981A - Interface method and apparatus in cpuless system - Google Patents

Abstract

A method and a device for performing interface in a system with no CPU are provided to interface an external AP and the system with no CPU at a fast transfer rate while reducing complexity and generally apply to the system with no CPU. A host-slave block(401) controls the interface to access an internal block by using a signal from multiplexing a control signal, an address, and data received from the AP. An interface part(440) receives the control signal, the address, and the data for interfacing between the AP and the host-slave block. The host-slave block includes a control path engine(410) transmitting an enable signal for a read/write signal to the internal block by receiving a chip select bar signal, a write enable bar signal, and a size signal, an address path engine(420) transmitting the data according to the information to the internal block by discriminating whether the information received from the address or data information, and a data path engine(430) including a transmission FIFO(First Input First Output) buffer(431).

Description

Interface method and device in a system without a central processing unit {INTERFACE METHOD AND APPARATUS IN CPULESS SYSTEM}

1 is a block diagram illustrating an SRAM interface device according to the prior art.

Figure 2 is a block diagram showing an SPI interface device according to the prior art

Figure 3 is a block diagram showing an I2C interface device according to the prior art

4 is a block diagram showing an interface device according to a preferred embodiment of the present invention.

5A and 5B are timing diagrams illustrating a single transmission operation in the interface device of the present invention.

6A and 6B are timing diagrams illustrating a burst transfer operation in the interface device of the present invention.

7 is a flowchart illustrating an interface method according to a preferred embodiment of the present invention.

The present invention relates to an interface method and apparatus in a communication system, and more particularly, to an interface method and apparatus in a system without a central processing unit (CPU).

In general, the interface between chips in a system without a CPU is mainly a serial interface such as a serial peripheral interface (SPI) or an inter-IC (I2C) or an interface such as a FIFO / SRAM. I use it.

1 is a diagram illustrating an SRAM interface device, which is an interface made for memory access. Referring to FIG. 1, when an application processor (AP) 110 receives an interrupt request signal (IRQ), an application processor (AP) 110 reads / writes internally using CSB, WEB, and OEB. The signal and the pad control signal are determined, and a selection signal is generated using an address. In the case of data, the AP 110 receives the data from the AP 110 at the time of writing and transmits the data to the internal design block (not shown), and receives the data from the design block at the time of reading. To send. At this time, the time taken to transmit one halfword is determined by a slower operating system among the CPUless system 101 and the AP 110.

The SRAM interface device has a very clearly defined timing or standard for each signal, and thus is useful for a relatively simple implementation and high-speed data transmission. It is also versatile enough to be applied to a System On Chip (SoC chip) that includes almost all CPUs. However, there is a disadvantage in that many pins must be used for transmitting an address and data.

2 is a block diagram illustrating an SPI interface. Referring to FIG. 2, in the case of the SPI interface, only three pins for CSB, DATA_EN, and DATA transmission are used, which is useful for transmitting a data stream requiring a performance of 10Mbps or less. However, since it is generally used for stream transmission, a lot of design effort is required to manufacture a controller 203 for configuring a system 201 without a CPU using the same.

3 is a block diagram illustrating an I 2 C interface. Referring to FIG. 3, in the case of I2C, it has a simple interface specification capable of bidirectional communication using two pins of SCL and SDA, so it is easy to manufacture a controller 303 of a system without CPU 301, but the speed of the interface itself is Is only suitable for data transmission because maximum 400Kbps is supported.

In the I2C interface, since an address phase part and a data phase part are basically divided, a host controller 303 can be easily produced without a large change, but a supported data format (Data) Since format) is 8 bits, it must be divided into 2 times in order to transfer the address or data beyond 8 bits. In addition, to recognize this, a separate hardware block must be implemented. Accordingly, there is a problem that the complexity of the system increases.

Accordingly, an object of the present invention is to provide an interface method and apparatus that can reduce the complexity in a system without a CPU.

Another object of the present invention is to provide an interface method and apparatus having a higher high data rate while reducing complexity in a system without a CPU.

It is another object of the present invention to provide an interface method and apparatus that can be used universally in a system without a CPU.

In order to achieve the above, the present invention provides an interface device with an external application processor (AP) in a system without a central processing unit, and includes a control signal, an address, and data transmitted from the AP for access to an internal block. And a host-slave block for controlling an interface using the multiplexed signal, and an interface unit for controlling the interface for the interface between the AP and the host-slave block.

The control signal includes a chip select bar (CSB) indicating whether the host-slave block operates, a write enable signal (Writing Enable Bar: WEB) for distinguishing a write / read operation, and the internal block. And a size signal indicating the transmission mode between the AP and the AP, and an address selection signal ADDR_SEL specifying an address of the multiplexed information between the inner block and the AP.

The host-slave block includes a control path engine that receives the CSB, WEB, and SIZE signals and transmits a write / read signal and an enable signal relating to operation of the internal block, and whether the information transmitted from the AP is address information. An address path engine that transmits data according to the information to the inner block by distinguishing whether it is data information, and a transmission first-in, first-out to transmit and receive addresses and data to and from the inner block, and to store data of a predetermined burst size during a read operation. And a data path engine having a buffer (Tx First Input First Output Buffer).

The present invention for achieving the above-described method in the interface method with an external application processor (AP) in a system without a central processing unit, the process of determining whether the write / read operation when the interface from the AP to the internal block And a step of selecting a burst mode or a burst mode after determining whether the operation is performed, and in a read mode and a burst mode, after decoding an address received from the AP, in advance in a data read interval set in a corresponding internal block. And receiving data from the corresponding block as much as the size of the determined buffer and storing the data in the internal buffer.

DETAILED DESCRIPTION Hereinafter, detailed descriptions of preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the same components in the figures represent the same numerals wherever possible. Specific details are set forth in the following description, which is provided to aid a more general understanding of the invention. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention is configured by applying the advantages of the SRAM, SPI, I2C controller of the host slave block when connecting the interface between the chip in a system without a CPU, it is configured using the interface using fewer pins. The interface of the present invention is not composed of hardware blocks separately to reduce the complexity and to enable higher speed transmission. To this end, the address phase and data portions are multiplexed and burst operations are easily supported. In the case of a burst read operation, data is transmitted while increasing an address according to a predetermined signal.

Next, the interface device according to the present invention will be described and the interface method will be described with reference to the accompanying drawings.

4 is a block diagram illustrating an interface device 400 according to a preferred embodiment of the present invention. For convenience of description, an application processor (AP) is omitted. Referring to FIG. 4, the interface device 400 of the present invention is divided into a host-slave block 401, which is a control unit, and an interface portion 440 between the host-slave block 401 and the host-slave block 401. The interface portion 440 is an interface between the AP and the host-slave block 401.

The host-slave block 401 includes a control path engine 410, an address path engine 420, and a data path engine 430. The control path engine 410 inputs a chip select signal (CSB) 441, a writing enable signal (WEB) 443, and a size signal 445 as a control signal. In this way, a write / read operation signal 403 and an enable signal 405 related to use are generated. The CSB 441 is a signal related to whether the interface between chips is used. If the signal is '0', it means that the CSB 441 is not used. The WEB 443 is a signal for controlling whether the write and read operations are performed, and in the case of '0', the WEB 443 indicates a write operation. The size signal 445 indicates a transmission unit between the host and the AP, and Size [1: 0] indicates a transmission unit using two bits. That is, the transmission unit varies according to the magnitude signal 445. Thus, the transmission unit according to the magnitude signal is shown in Table 1 below. In the present invention, whether or not the burst operation (Burst Operation) is determined according to the transmission unit according to the magnitude signal (445).

In the present system, a basic transmission unit is called a halfword, and one halfword means 16 bits. In addition, one halfword transmission in the present system is referred to as single transfer, and a plurality of halfwords is referred to as burst transfer. Referring to Table 1, it can be seen that when the magnitude signal is '00', it is single transmission in one half word, and in other cases, it is burst transmission in a plurality of hard words.

Accordingly, the control path engine 410 of the present invention receives the control signals (CSB, WEB) transmitted from the host and performs write / read access to the I / O pad control and the internal register. It sends out a signal to determine. In addition, the address path engine 420 transmits the information about the transmission unit.

The address path engine 420 distinguishes whether the information received through the S1 interface by the address select signal ADDR_SEL 447 is address information or data information. In this case, the ADDR_SEL 447 indicates address information when '0' is 1 bit and data information when '1'. The S1 line is an interface capable of transmitting and receiving addresses and data. Accordingly, the address path engine 420 receives and decodes the address received through the S1 interface, generates a selection signal for the corresponding internal block, and automatically generates an address according to SIZE [1: 0]. Increase. The SIZE [1: 0] is informed by the control path engine 410 through the C1 signal.

The data path engine 430 generates an address by the address path engine 420 and transmits and receives an address and data to a corresponding internal block. The data path engine 430 includes a Tx First Input First Output Buffer 431 to store data read from each internal block according to a predetermined burst size during a read operation. Overall control for this is configured to be transmitted by the control signals (CSB, WEB, SIZE) of the AP. Here, the address signal ADDR [15: 0] 407 is a signal representing an address, and is composed of 16 bits. WDATA [15: 0] 408 is data transmitted in a write operation and is composed of 16 bits. RDATA [15: 0] (409) is data transmitted in a read operation and stored in the transmission unit in the Tx FIFO 431. And is transmitted to the AP through the S1 interface. Detailed operation thereof will be described in detail with reference to FIG. 7, and will be omitted herein.

Next, the operation performed in the interface device 400 of the present invention will be described using the following timing chart.

5A and 5B are timing diagrams illustrating a single transfer operation in the interface device of the present invention, and show write and read operations, respectively.

Referring to FIG. 5A, since the CSB 441, the WEB 443, and the ADDR_SEL 447 are all '0' in the T1 section, the interface device 400 of FIG. do. Therefore, in the T1 section, the address is transmitted to the corresponding inner block in a single transmission unit, and in the T2 section, the data corresponding to the inner block is written in the single transmission unit in the data transmission section. Referring to FIG. 5B, since the CSB 441 and the ADDR_SEL 447 are '0' and the WEB 443 is '1' in the T1 section, the address phase portion is represented by the read operation in the section. Then, the data phase is stored in the Tx FIFO 431 as a single transmission unit in the T2 section and transmitted to the AP.

6A and 6B are timing diagrams illustrating a burst transfer operation in the interface device of the present invention, and show write and read operations, respectively. In this example, it is assumed that the burst operation operates with 4 half words.

Referring to FIG. 6A, since the CSB 441, the WEB 443, and the ADDR_SEL 447 are all '0' in the T1 section, the address phase portion is represented by the write operation in the section. However, since the magnitude signal 445 is operated in four halfwords, four halfwords are written in the corresponding internal block in the T2 section, which is a data phase portion. In the read operation as shown in FIG. 6B, it is recognized that four halfwords are operated by the size signal 445 in the read operation in the T1 section, which is an address phase portion, similar to the write operation. Read operation is performed by incrementing the address of data three times by 2 so as to store the data in the Tx FIFO 431. The reason why the address is increased by '2' is because the address is changed in units of 8 bits. In this way, 8 and 16 halfwords generate addresses in the same way.

Next, the interface method of the present invention will be described.

7 is a flowchart illustrating an interface method according to a preferred embodiment of the present invention. In the interface method of the present invention, the host-slave block 401 receives a control signal of the CSB 441, the WEB 443, and the ADDR_SEL 447 received from the interface unit 440 to receive a signal for a write or read operation. Create and access the inner block with the next incoming data.

Referring to FIG. 7, the host-slave block 401 is maintained in an idle state as in step 701. Then, when receiving the control signals of the CSB 441, WEB 443, and ADDR_SEL 447 received through the interface unit 440 for access from each AP, the host-slave block 401 takes precedence in step 703. Check if it is a read operation. As described above, the read operation is determined by the WEB 443 signal. In the case of a read operation, the control path engine 410 notifies the access by transmitting the write signal 403 and the enable signal 405 to the corresponding inner block. If it is the read operation in step 703, it is checked in burst transfer mode in step 705. Whether or not the burst is transmitted is determined by SIZE [1: 0] 445. The transmission mode determined by SIZE [1: 0] is shown in Table 1.

When the transmission mode is the burst mode, the address path engine 420 decodes the address received through the S1 interface in step 707. The data path engine 430 then transmits the decoded data ADDR [15: 0] 407 to the inner block in step 709 and receives data in the data phase interval from the inner block. The received data is stored in the Tx FIFO 431 of the data path engine 430. Then check whether the size value is '0'. This is because the transmission mode is a burst mode, so that data is stored in the Tx FIFO 431 from the corresponding inner block in burst units. Accordingly, the size value represents the size of the Tx FIFO 430 according to the burst transmission mode.

If the magnitude value is not '0', it is determined that all burst information is not stored in the Tx FIFO 430. In step 712, the burst value is decreased and the data address is automatically increased. When receiving the related control signal, steps 707 to 709 are repeatedly performed. This process is repeated until the size value becomes '0'. If all burst information is stored in the Tx FIFO 430 in step 711, the flow proceeds to step 715 to transmit burst information to the corresponding AP. Then, when the control signal associated with the data phase portion is received in step 715, the operation of sending data stored in the Tx FIFO 431 to the AP is simultaneously performed.

If the transmission mode is a single unit of transmission in step 705, the host-slave block 401 decodes the received address and stores the data received from the corresponding inner block in the Tx FIFO 431. Then, at step 715, the stored data is sent to the AP at the time when the control signal associated with the data phase section is received, or the data for write operation is transferred therein.

In the case of a write operation in step 703, the host-slave block 401 checks whether a burst is transmitted in step 717. Accordingly, in the burst transmission mode, the address path engine 420 attempts to patch data by decoding the address received through the S1 interface in step 719. Thereafter, in step 721, an internal access operation corresponding to the corresponding inner block is performed. Thereafter, when a control signal related to the data phase portion is received, the data to be written to is transferred to the corresponding inner block, and then the size value is checked as '0' in step 723. If the size value is not '0', the controller proceeds to step 724 to decrease the size value by one, automatically increases the address of the next data, and then the control signal related to the data phase portion is again performed in step 719. Perform step 721. This process is repeated until the size value becomes '0'.

In a single transmission mode in step 717, the host-slave block 401 decodes the address received in step 727 to perform a data patch operation. Thereafter, in step 729, an internal access operation appropriate to the corresponding inner block is performed.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention is not only easy to design because of low design complexity when developing dedicated interface hardware logic, but also because it uses a general purpose input / output port (GPIO) without dedicated interface hardware logic. It does not require any hardware logic and can communicate with any AP. In addition, the use of Tx FIFO can greatly improve the performance of the read operation of the AP.

Claims (4)

In an interface device with an external application processor (AP) in a system without a central processing unit, A host-slave block for controlling an interface by using a control signal transmitted from the AP and a signal multiplexed with data for access to an internal block; And an interface unit for the control signal and the interface unit for the interface between the AP and the host-slave block. The method of claim 2, wherein the control signal, A chip select signal (CSB) indicating whether the host-slave block is operated; A write enable signal (Writing Enable Bar: WEB) for distinguishing a write / read operation; A size signal indicating the transmission mode between the inner block and the AP; And an address selection signal (ADDR_SEL) for designating an address of the multiplexed information between the inner block and the AP. The method of claim 2, wherein the host-slave block, A control path engine for receiving the CSB, WEB, and SIZE signals and transmitting a write / read signal and an enable signal relating to operation of the internal block; An address path engine for distinguishing whether the information transmitted from the AP is address information or data information and transmitting data according to the information to a corresponding inner block; And a data path engine having a Tx First Input First Output Buffer for transmitting and receiving an address and data in a corresponding internal block and storing data of a predetermined burst size during a read operation. Interface device. In an interface method with an external application processor (AP) in a system without a central processing unit, Determining whether a write / read operation is performed at the interface from the AP to an internal block; Selecting whether the transmission unit is a single mode or a burst mode after the operation is determined; In the read mode and the burst mode, a process of decoding an address received from the AP and receiving data from the block as much as a predetermined buffer size in a data read interval set in the corresponding inner block is stored in the internal buffer. Interface method characterized in that.

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