KR101517835B1 - Processor, system and recording medium including ipc driver for inter-processor communication - Google Patents

Abstract

A processor, system, and recording medium including an IPC driver for inter-processor communication are disclosed. The processor includes an application, an IPC driver, and a device driver. The IPC driver stores information about a plurality of data packets in an IPC channel of one of a plurality of IPC channels to provide an application with a transmission path for a plurality of data packets. The device driver writes a plurality of data packets to the inter-processor communication device based on information on the plurality of data packets. It is possible to improve the data transfer rate by supporting the burst transfer between the processors.

Burst transmission, interprocessor communication

Description

TECHNICAL FIELD [0001] The present invention relates to a processor, a system, and a recording medium including an IP address driver for inter-processor communication.

The present invention relates to inter-processor communication (IPC) technology, and more particularly, to an IPC driver providing a plurality of IPC channels for inter-processor communication, a processor and a system including the same.

For inter-processor communication (IPC), there is a need for a means for connecting processors to transfer data, and an interface is one that performs this function. Typically, a serial interface such as a universal asynchronous receiver transmitter (UART), a serial peripheral interface (SPI), or a universal serial bus (USB) is used as an interface for IPC.

Such a conventional serial interface converts parallel data to serial data and transmits it, so that only one bit of data between processors is transmitted in one clock. As a result, the serial interface has a limitation in data transmission speed. For example, IPC using SPI has a data transfer rate of about 16 Mbps, IPC using UART has a data transfer rate of about 1.5 Mbps, and IPC using high-speed UART has a data transfer rate of about 5 Mbps I have. In addition, IPC using full-speed USB has a data transfer rate of up to 12 Mbps and actually has a data transfer rate of about 6 Mbps due to the high packet overhead required for the USB protocol.

A communication method using a dual port random access memory (DPRAM) has been developed in order to overcome the limitation of the data transmission speed of the system utilizing the serial interface.

In a system utilizing DPRAM, each processor requires a separate dynamic random access memory (DRAM) for storing application data and a separate flash memory for storing application executable code. As a result, the size of the system utilizing the DPRAM increases, and the data processing speed deteriorates due to the memory access latency. Also, due to the limitation of the capacity of the DPRAM, there is a problem that the data transmission speed is lowered when large capacity data is transmitted between the processors.

In order to solve the above problems, it is an object of the present invention to provide a processor capable of improving communication speed between processors.

It is another object of the present invention to provide a system capable of improving the communication speed between processors.

It is still another object of the present invention to provide a computer-readable recording medium on which an inter-processor communication (IPC) driver capable of improving inter-processor communication speed is recorded.

According to an aspect of the present invention, a processor includes at least one application, an IPC driver, and a device driver.

The application transmits and receives a plurality of data packets through inter-processor communication. The IPC driver stores information on the plurality of data packets in any one of a plurality of IPC channels to provide a transmission path for the plurality of data packets to the application . The device driver writes the plurality of data packets to the inter-processor communication device based on information on the plurality of data packets stored in the one IPC channel.

In one embodiment, the IPC driver includes an application programming interface (IPC API) provided to the application and requested to transmit the plurality of data packets, a plurality of data packets And an IPC thread for providing the device driver with information on the plurality of data packets stored in any one of the IPC channels, . The one IPC channel may store pointers and lengths of the plurality of data packets.

In one embodiment, the one of the IPC channels comprises a data packet transmission queue storing pointers and lengths of a first plurality of data packets transmitted from the application to the inter-processor communication device, And a data packet reception queue for storing pointers and lengths of a second plurality of data packets transmitted to the application. The IPC thread requests to stop the data packet transmission to the data packet reception queue through the device driver when the number of the second plurality of data packets storing pointers and lengths in the data packet reception queue is equal to or greater than the stop threshold And if the number of the second plurality of data packets storing pointers and lengths in the data packet reception queue is less than a resume threshold after requesting the suspension of the data packet transmission, Requesting the resumption of data packet transmission.

In one embodiment, the IPC API includes a data packet transmission function for storing information on the plurality of data packets in any one of the IPC channels, a data packet transmission function for storing the plurality of data packets A channel open function for providing a handle of one of the IPC channels to the application and a channel close function for canceling a handle of one of the IPC channels provided to the application, .

In one embodiment, the application comprises a first application for transmitting and receiving a first plurality of data packets and a second application for transmitting and receiving a second plurality of data packets, Storing information on the first plurality of data packets of the first application on a first IPC channel and storing information on the second plurality of data packets of the second application on a second one of the plurality of IPC channels Can be stored.

In one embodiment, the device driver includes a data packet write function for writing the plurality of data packets to the inter-processor communication device, a data packet read function for reading the plurality of data packets from the inter-processor communication device, A message writing function that writes a message to the inter-processor communication device, and a device API that includes a message read function to read the message from the inter-processor communication device.

According to another aspect of the present invention, there is provided a system according to an embodiment of the present invention includes a plurality of processors and an inter-processor communication device.

Each of the plurality of processors comprising: one or more applications for transmitting and receiving a plurality of data packets through interprocessor communication; a plurality of inter-processor communication channels (IPC) for providing a transmission path for the plurality of data packets to the application; An IPC driver for storing pointers and lengths for the plurality of data packets on any one of the IPC channels, and an IPC driver for, based on the pointers and lengths for the plurality of data packets stored in the one IPC channel And a device driver for writing the plurality of data packets to the interprocessor communication device. Wherein the inter-processor communication device is selectively accessed by the plurality of processors and stores the plurality of data packets received from the device driver included in each of the plurality of processors, And data transmission information for the stored plurality of data packets.

In one embodiment, the inter-processor communication device further comprises a plurality of ports coupled to the plurality of processors, a plurality of ports selectively accessed by the plurality of processors through the plurality of ports, And a mailbox area connected to the plurality of ports, the mailbox area storing the command and the data transmission information.

In one embodiment, the one channel in which the plurality of data packets are stored includes a plurality of buffers, and each of the plurality of buffers may store any one of the plurality of data packets.

In one embodiment, the mailbox area includes a command storage area for storing the command, a channel index storage area for storing information about locations in the shared storage area of the plurality of data packets, And a number-of-packets storage area for storing information on the number of packets.

In one embodiment, the inter-processor communication device may further include a semaphore area storing information on ownership of the shared storage area. The inter-processor communication device may further include a plurality of dedicated storage areas, which are respectively accessed by the plurality of processors through the plurality of ports, and store the code and data of the application.

In one embodiment, the inter-processor communication device may be a dynamic random access memory (DRAM).

In one embodiment, the IPC driver includes an application programming interface (IPC API) provided to the application and requested to transmit the plurality of data packets, a plurality of data packets And a plurality of IPC channels for storing the pointers and lengths for the plurality of data packets stored in any one of the IPC channels, Lt; RTI ID = 0.0 > IPC < / RTI > Wherein the one IPC channel comprises a data packet transmission queue for storing pointers and lengths of a first plurality of data packets transmitted from the application to the inter-processor communication device, And a data packet reception queue for storing pointers and lengths of a second plurality of data packets.

In one embodiment, the application comprises a first application for transmitting and receiving a first plurality of data packets and a second application for transmitting and receiving a second plurality of data packets, 1 pointers and lengths for the first plurality of data packets of the first application on a first IPC channel and storing the pointers and lengths of the second plurality of data of the second application on a second one of the plurality of IPC channels And may store pointers and lengths for packets.

According to another aspect of the present invention, there is provided a computer-readable recording medium on which an IPC driver is recorded, including an inter-processor communication (API) application programming interface (API) IPC channels and IPC threads.

The IPC API is provided to a plurality of applications, and is requested to transmit a plurality of data packets from each of the plurality of applications. The plurality of IPC channels storing pointers and lengths of the plurality of data packets to provide at least one transmission path for the plurality of data packets to each of the plurality of applications. The IPC thread writes the plurality of data packets to the inter-processor communication device through a device driver based on pointers and lengths for the plurality of data packets stored in the plurality of IPC channels.

In one embodiment, each of the plurality of IPC channels may store pointers and lengths for the plurality of data packets of a corresponding one of the plurality of applications.

The computer-readable recording medium on which the processor, the system and the inter-processor communication (IPC) driver are recorded according to the embodiments of the present invention can provide one or more IPC channels per application / .

In addition, the computer-readable recording medium in which the inter-processor processor, the system and the IPC driver are recorded in the embodiments of the present invention minimizes the data packet copy operation, thereby further improving the data transfer rate.

In addition, the computer-readable recording medium in which the inter-processor processor, the system and the IPC driver are recorded in the embodiments of the present invention can prevent the data packet overflow of the channel of the IPC channel and the corresponding shared storage area , It is possible to support stable data packet transmission while maintaining the data transmission speed.

Also, in the embodiments of the present invention, a computer-readable recording medium in which an inter-processor processor, a system and an IPC driver are recorded can support burst transfer between processors to further improve data transfer speed.

In addition, in the embodiments of the present invention, a computer-readable recording medium in which an inter-processor processor, a system and an IPC driver are recorded provides a dedicated storage area for each processor, thereby reducing the number of memories required for the system, have.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a system according to an embodiment of the present invention.

Referring to FIG. 1, a system 100 includes a first processor 200, a second processor 300, and an inter-processor communication device 400. 1 illustrates a system 100 including two processors 200 and 300 connected to an inter-processor communication device 400, it is contemplated that the inter-processor communication device 400 may include three or more processors Lt; / RTI >

The first processor 200 and the second processor 300 are connected to the inter-processor communication device 400, respectively. The first processor 200 may access the inter-processor communication device 400 through the first port of the inter-processor communication device 400 and the second processor 300 may access the inter-processor communication device 400 through the first port of the inter- Lt; RTI ID = 0.0 > 400 < / RTI > In one embodiment, the first processor 200 and the second processor 200 may be coupled to the first port and the second port, respectively, via a bus. In another embodiment, the first processor 200 and the second processor 200 may be directly connected to the first port and the second port, respectively, through a plurality of signal lines without a separate arbitration device. For example, the first processor 200 and the first port may be connected via 16 or 32 data signal lines, and a plurality of address / control signal lines may be connected between the first processor 200 and the first port Can be connected.

According to an embodiment, the first processor 200 may be a modem processor and the second processor 300 may be an application processor or a multimedia processor. According to an embodiment, the first processor 200 and the second processor 300 may be implemented as separate chips, and the first processor 200 and the second processor 300 may be implemented as a single chip. have.

The inter-processor communication device 400 includes a shared storage area in which data packets transmitted between the first processor 200 and the second processor 300 are stored and a shared storage area in which data is transmitted between the first processor 200 and the second processor 300 And a mailbox area for storing the received message. The shared storage area is selectively accessed by the first processor 200 or the second processor 300. For example, the second processor 300 may not access the shared storage area while the first processor 200 has ownership of the shared storage area. The mail box area stores a first mail box for storing a message transmitted from the first processor 200 to the second processor 300 and a second mail box for storing a message transmitted from the second processor 300 to the first processor 200 Lt; RTI ID = 0.0 > mailbox. ≪ / RTI > When the first processor 200 writes a message in the first mailbox, the second processor 300 receives the first interrupt signal INT1 and recognizes that the message is written in the first mailbox. Also, when the second processor 300 writes a message in the second mailbox, the first processor 200 receives the second interrupt signal INT2 and recognizes that the message is written in the second mailbox .

For example, when data packets are transmitted from the first processor 200 to the second processor 300, the first processor 200 transmits ownership of the shared storage area through a message transmission using the mailbox area Can be obtained. The first processor 200 may write the data packets to the shared storage area and write a data transfer command to the first mailbox to inform the second processor 300 that the data packets have been written. In addition, the first processor 200 writes information such as the position, the number of packets, and the like in which the written data packets are stored together with the data transfer command in the first mailbox, The data packets can be read without further analysis. In addition, the first processor 200 transmits the data packets to the inter-processor communication device 400 in parallel through a plurality of signal lines connected to the first port, and the second processor 300 transmits the data packets in parallel to the inter- By receiving the data packets in parallel to the inter-processor communication device 400 through a plurality of signal lines, the data transmission speed between the first processor 200 and the second processor 300 is improved. In addition, the inter-processor communication device 400 writes a plurality of data packets to the shared storage area while the first processor 200 owns the shared storage area, and the second processor 300 writes the ownership And supports burst transfer which can read a plurality of data packets from the shared storage area during its lifetime. Accordingly, the data transfer rate can be further improved by reducing the overhead of ownership exchange.

FIG. 2A is a block diagram illustrating an example of modules executing in a processor included in the system of FIG. 1, and FIG. 2B is a block diagram illustrating another example of modules executing in a processor included in the system of FIG.

Referring to FIG. 2A, a processor 200a includes a device driver 210, an IPC driver 220, and an application 230. In one embodiment, each of device driver 210, IPC driver 220, and application 230 may be implemented in dedicated hardware. In another embodiment, the device driver 210, the IPC driver 220, and the application 230, respectively, may be implemented in software running on general purpose hardware. According to the embodiment, the device driver 210 and the IPC driver 220 may each be registered in the kernel 240 as a kernel driver. In one embodiment, the device driver 210 and the IPC driver 220 may each be implemented as separate kernel drivers. In another embodiment, the device driver 210 and the IPC driver 220 may be implemented as a single kernel driver.

The processor 200a of FIG. 2A may be the first processor 200 of FIG. 1 or the second processor 300 of FIG. For example, each of the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 includes at least one application 230 requesting data transmission, an IPC managing an IPC channel for the application 230, Driver 220 and the IPC driver 220 to the inter-processor communication device 400 of FIG. 1 or to read from the inter-processor communication device 400 of FIG. 1 ).

The device driver 210 provides a device application program interface (API) to the IPC driver 220. When the IPC driver 220 requests the device driver 210 to write or read a data packet or a message through the device API, the device driver 210 transmits a data packet or a message to the inter-processor communication device 400 of FIG. Or reads from the inter-processor communication device 400 of Fig. According to an embodiment, the device driver 210 may be implemented as a library.

The IPC driver 220 may provide an IPC API to the application 230 and perform a function of connecting the application 230 and the device driver 210 by calling the device API of the device driver 210. [ For example, when the application 230 calls the function of the IPC driver 220 provided in the IPC API directly or through the kernel 240, and the IPC driver 220 calls the function of the device driver 210 provided in the device API By calling the function, the data packet of the application 230 can be written to the inter-processor communication device 400 of FIG.

The IPC driver 220 may include a plurality of IPC channels and may provide at least one IPC channel for each application 230. Accordingly, the data packets of each of the applications 230 are written to the inter-processor communication device 400 of FIG. 1 through the IPC channel corresponding to the application 230, The data packet is transmitted to the application 230 through the corresponding IPC channel, thereby supporting independent data transmission for each application 230, thereby improving the data transmission speed of the system 100 of FIG.

The application 230 may be an application that requires data communication with an application executed by the second processor 300 of FIG. 1 when executed by the first processor 200 of FIG. For example, application 230 may be a process that provides modem functionality to demodulate data and provide it to applications running on second processor 300 of FIG.

Referring to FIG. 2B, the processor 200b includes a device driver 210, an IPC driver 220, a first application 230, and a second application 250. In one embodiment, the device driver 210, the IPC driver 220, the first application 230, and the second application 250, respectively, may be implemented with dedicated hardware. In another embodiment, the device driver 210, the IPC driver 220, the first application 230, and the second application 250, respectively, may be implemented as software running on general purpose hardware. The processor 200b of Fig. 2b executes two applications 230 and 250 that require data transfer, unlike the processor 200a of Fig. 2a. In FIG. 2A, an example in which the processor 200a executes one application 230 is shown, and in FIG. 2B, an example in which the processor 200b executes two applications 230 and 250 is shown. However, The first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 may each execute three or more applications that require data transfer.

The IPC driver 220 may include a plurality of IPC channels and may provide at least one IPC channel to each of the first and second applications 230 and 250. For example, the first application 230 may transmit data packets over the first IPC channel and the second application 250 may transmit data packets over the second IPC channel and the third IPC channel. The first application 230 and the second application 250 write data packets to and from the inter-processor communication device 400 of FIG. 1 through different IPC channels or by reading from the inter-processor communication device 400 of FIG. 1 The data transmission rate of the system 100 of FIG. 1 can be improved by transmitting data packets independently for each of the applications 230 and 250.

FIG. 3 is a block diagram showing the device driver shown in FIG. 2A or FIG. 2B, and FIG. 4 is a diagram showing an example of the device API shown in FIG.

Referring to FIG. 3, the device driver 210 includes a device API 211. In one embodiment, the device API 211 may be provided to the IPC driver 220 of FIG. 2A or 2B. In another embodiment, the device API 211 may be provided in the application 230 of FIG. 2A or the first and second applications 230, 250 of FIG. 2B. According to an embodiment, the device driver 210 may be implemented as a library.

Referring to FIG. 4, the device API 211a may include message transmission related functions, data transmission related functions, and other functions. For example, the device API 211a may include a message writing function, a message reading function, a data packet writing function, a data packet reading function, an initialization function, an ownership verification function, an error verification function, a channel address search function, The message write function is a function to write a message to a mailbox area of the inter-processor communication device 400 of FIG. 1, the message read function is a function to read a message from the mailbox area, 1 is a function of writing one or more data packets to a shared storage area of the inter-processor communication device 400 of FIG. 1, the data packet reading function is a function of reading one or more data packets from the shared storage area, Function is a function for initializing the device driver 210. The ownership confirmation function is a function for accessing the inter-processor communication device 400 of FIG. 1 to check which processor owns the ownership of the shared storage area, The error checking function may be used to code the last generated device driver 210 error code or message And the channel address search function is a function that returns an address corresponding to a channel of the shared storage area provided as a parameter. The IPC driver 220 or the application 230 can access the inter-processor communication device 400 of FIG. 1 through the API of the device driver 210 as described above.

5 is a block diagram showing the IPC driver shown in FIG. 2A or 2B, FIG. 6 is a diagram showing an example of the IPC API shown in FIG. 5, FIG. 7 is a diagram showing an example of the IPC channel shown in FIG. 5 Fig.

Referring to FIG. 5, the IPC driver 220 includes an IPC API 221, a plurality of IPC channels 223, and an IPC thread 222.

The IPC API 221 may be provided to the application 230 of FIG. 2A or the first and second applications 230 and 250 of FIG. 2B and may be provided to the application 230 of FIG. 2 applications 230 and 250 may transmit data packets by calling functions of the IPC API 221. [ For example, if the application 230 of FIG. 2A calls the function of the IPC API 221 directly or through the kernel 240 of FIG. 2A, and the IPC driver 220 calls the function of the device API of FIG. 3 The data packet of application 230 may be written to inter-processor communication device 400 of FIG.

The plurality of IPC channels 223 may be data packets transmitted to the inter-processor communication device 400 of FIG. 1 in the application 230 of FIG. 2A or the first and second applications 230 and 250 of FIG. The interprocessor communication apparatus 400 of FIG. 1 may temporarily store pointers of the data packets and may transmit data to the application 230 of FIG. 2A or to the first and second applications 230 and 250 of FIG. Packets or pointers of the data packets. In addition, the plurality of IPC channels 223 may provide one or more IPC channels 223 to each of the applications 230, 250. Accordingly, the data transmission rate of the system 100 of FIG. 1 can be improved by independently transmitting data packets through the different IPC channels 223 for each of the applications 230 and 250.

The IPC thread 222 may manage a plurality of IPC channels 223. According to an embodiment, the IPC thread 222 may have a single thread and may have more than two threads. For example, when the application 230 of FIG. 2A calls the IPC API 221 to write pointers to data packets or data packets to the corresponding IPC channel 223 and requests transmission of the data packets, The IPC thread 222 may call the data packet write function of the device API 211 of FIG. 3 based on the data packets written to the IPC channel 223 or pointers to the data packets. In one embodiment, the IPC thread 222 calls the message read function of the device API 211 of FIG. 3 when the interrupt signal INT1, INT2 is generated in the inter-processor communication device 400 of FIG. 1 .

Referring to FIG. 6, the IPC API 221a may include data transfer related functions and other functions. For example, the IPC API 221a may include a data packet transmission function, a data packet reception function, a channel open function, a channel close function, a configuration change function, and the like.

The data packet transmission function stores in the IPC channel 223 one or more data packets of the application 230 or a pointer to the one or more data packets. In one embodiment, the data packet transmission function may provide a transmission event to the IPC thread 222, and the IPC thread 222 may send a transmission event to the IPC thread 222 based on pointers to data packets or data packets stored in the IPC channel 223 The device driver 210 may write the data packets to the inter-processor communication device 400 of FIG. The data packet receive function provides the application 230 with one or more data packets stored in the IPC channel 223 or a pointer to the one or more data packets. In one embodiment, the IPC thread 222 may read data packets from the inter-processor communication device 400 of FIG. 1 through the device driver 210 and the IPC thread 222 may read the data packets or the data And may store pointers of packets in the IPC channel 223. The IPC thread 222 provides a receive event to the application 230 and the application 230 receives the data packets stored in the IPC channel 223 or pointers to the data packets by calling the data packet receive function . In one embodiment, the data packets or pointers to the data packets may be provided to the application 230 by calling the function of the application 230 that the data packet receive function registers with the IPC driver 220.

The channel open function returns a handle of the IPC channel 223. In one embodiment, the IPC driver 220 may assign the corresponding IPC channel 223 to a memory, for example, a dedicated storage area of the inter-processor communication device 400 of FIG. 1, when the channel open function is called have. In another embodiment, the IPC driver 220 may allocate a plurality of IPC channels 223 when initialized and return a handle of the unused IPC channel 223 when the channel open function is called. The channel close function releases the handle of the IPC channel 223. In one embodiment, the IPC driver 220 may release the IPC channel 223 in memory when the channel close function is called. In another embodiment, the IPC driver 220 may change only flags indicating whether to use or not when the channel close function is called. The setting change function changes the setting value of the IPC driver 220. [ For example, the configuration change function may change the number of IPC channels 223, the number of buffers of the IPC channel 223, and the like.

Referring to FIG. 7, the IPC channel 223a includes a data packet transmission queue 224 and a data packet reception queue 225. The data packet transmission queue 224 includes a first transmission buffer 2241, a second transmission buffer 2242 and a third transmission buffer 2243. The data packet reception queue 225 includes a first reception buffer 2251, A second reception buffer 2252, and a third reception buffer 2253.

The data packet transmit queue 224 and the data packet receive queue 225 may each operate as a first-in first-out (FIFO). To the inter-processor communication apparatus 400 of FIG. 1 through the device driver 210 in the application 230, to the first transmission buffer 2241, the second transmission buffer 2242, and the third transmission buffer 2243, respectively. Information on one data packet, i.e., the pointer of the data packet and the length of the data packet can be stored. 1 to the application 230 through the device driver 210 in the inter-processor communication device 400 of FIG. 1 to the first reception buffer 2251, the second reception buffer 2252 and the third reception buffer 2253 Information on one data packet to be transmitted, that is, the pointer of the data packet and the length of the data packet can be stored.

As such, data packets are not stored in the data packet transmission queue 224 and the data packet reception queue 225 of the IPC channel 223a, and the pointers and / or lengths of the data packets are stored, The copy operation may not be performed. Accordingly, the data transmission rate of the system 100 of FIG. 1 can be improved.

8 is a block diagram illustrating an inter-processor communication device included in the system of FIG.

8, the inter-processor communication device 400a includes a first port 431, a second port 432, a first dedicated storage area 411, a second dedicated storage area 413 and 414, An area 412, a semaphore area 421, and mailbox areas 422 and 423.

The first port 431 is coupled to the first processor 200 of FIG. 1 and the second port 432 is coupled to the second processor 300 of FIG. Also, the first port 431 is connected to the first dedicated storage area 411 and the shared storage area 412 in the inter-processor communication device 400a, and the second port 432 is connected to the inter-processor communication device 400a (413, 414) and the shared storage area (412) within the first dedicated storage area (413, 414). Accordingly, the first processor 200 of FIG. 1 can access the first dedicated storage area 411 and the shared storage area 412 via the first port 431, and the second processor 300 May access the second dedicated storage area 413, 414 and the shared storage area 412 through the second port 432. [

The first dedicated storage area 411 is connected to the first processor 200 of FIG. 1 through a first port 431 and stores code and / or data of an application executed by the first processor 200 of FIG. 1 Can be stored. The second dedicated storage area 413 and 414 are connected to the second processor 300 of FIG. 1 through a second port 432 and are coupled to the code of the program executed by the second processor 300 of FIG. 1 and / Data can be stored. Accordingly, the first dedicated storage area 411 for the first processor 200 of FIG. 1 replaces the additional memory for storing the code and / or data of the program executed by the first processor 200 of FIG. And the second dedicated storage area 413, 414 for the second processor 300 of FIG. 1 is an additional memory for storing the code and / or data of the program executed by the second processor 300 of FIG. 1 By replacing, the number of memory devices required in the whole system can be reduced, and power consumption can be reduced.

The shared storage area 412 is selectively connected to either the first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 via the first port 431 or the second port 432. That is, only one processor having ownership of the shared storage area 412 among the first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 can access the shared storage area 412. The shared storage area 412 may store a plurality of data packets transmitted between the first processor 200 of FIG. 1 and the second processor 300 of FIG. According to an embodiment, the shared storage area 412 can be divided into a plurality of channels, and each of the plurality of channels can be divided into a plurality of buffers. One data packet may be stored in each of the plurality of buffers. The shared storage area 412 is divided into a plurality of channels and data packets are written to and read from the respective channels according to the application executed in the first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 , The first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 may not perform a complicated process of analyzing the header of each of the data packets. Accordingly, the data transmission rate of the system 100 of FIG. 1 can be further improved.

In one embodiment, the first dedicated storage area 411, the second dedicated storage area 413, 414 and the shared storage area 412 may each be one or more memory banks, and the inter-processor communication device 400a, May be a dynamic random access memory (DRAM). For example, the first dedicated storage area 411 includes a first memory bank BANK A and the second dedicated storage areas 413 and 414 include third and fourth memory banks BANK C and BANK D ), And the shared storage area 412 may include a second memory bank (BANK B), and each of the first to fourth memory banks (BANK A, BANK B, BANK C, and BANK D) And a plurality of memory cells arranged in a matrix of columns, each of the plurality of memory cells being a dynamic random access memory cell consisting of one access transistor and a storage capacitor. For example, each of the first to fourth memory banks BANK A, BANK B, BANK C, and BANK D may have a memory capacity of 16 MB, 64 MB, 128 MB, 256 MB, and 512 MB.

In accordance with an embodiment, the inter-processor communication device 400a may communicate the shared storage area 412 to the first processor 200 in response to control signals received from the first processor 200 of FIG. 1 or the second processor 300 of FIG. And an access path forming part for selectively connecting to the port 431 or the second port 432. In one embodiment, the access path forming unit includes a path determining unit for generating a path determining signal by logically combining the control signals, and a path determining unit for determining whether or not the path determining signal is input through the first port 431 or the second port 432 Row and column address multiplexers for selecting one of the row and column addresses to be applied to a row decoder and a column decoder connected to the shared storage area 412, First and second global multiplexers for selectively coupling the global input / output line pair of region 412 to a first data input / output line pair or a second data input / output line pair, and first and second global multiplexers, And first and second input / output circuits provided between the second ports 431 and 432, respectively.

Semaphore area 421 may store information about ownership of shared storage area 412. In one embodiment, the first processor 200 of FIG. 1 has ownership of the shared storage area 412 when a particular bit of the semaphore area 421 is a logic " 1 " The second processor 300 of FIG. 1 may have ownership of the shared storage area 412 if it is a logic " 0 ". In another embodiment, a particular bit in the semaphore area 421 may only indicate whether or not any processor occupies the shared storage area 412. According to an embodiment, if the shared storage area 412 includes a plurality of banks, the semaphore area 421 may store a plurality of bits.

The mailbox areas 422 and 423 store messages transmitted between the first processor 200 of FIG. 1 and the second processor 300 of FIG. For example, messages transmitted between the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 may include messages relating to ownership of the shared storage area 412, messages relating to data transfer, And the channel state of the second channel 412. In addition, when the transmitted message is a message related to data transmission, the transmitted message includes a command indicating that the transmitted message is a message related to data transmission and data transmission information indicating information on currently transmitted data packets . ≪ / RTI > In one embodiment, the mailbox areas 422 and 423 include a first mailbox 422 for storing messages sent from the first processor 200 of FIG. 1 to the second processor 300 of FIG. 1, 1 for storing a message sent from the second processor 300 of FIG. 1 to the first processor 200 of FIG. When a message is written to the first mailbox 422, the first interrupt signal INT1 is transmitted to the second processor 300 of FIG. 1 and the message is written to the second mailbox 423, The second interrupt signal INT2 is transmitted to the first processor 200. [ When the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 respectively receive the first interrupt signal INT1 and the second interrupt signal INT2, the first processor 200 and the second processor 300 of FIG. The second processor 300 of FIG. 1 reads the messages stored in the first mailbox 422 and the second mailbox 423, respectively.

In one embodiment, when the second interrupt signal INT2 is sent to the first processor 200 of FIG. 1, the kernel 240 of FIG. 2A may call the registered interrupt handler. For example, the IPC driver 220 of FIG. 2A may register the interrupt handler for the second interrupt signal INT2 in the kernel 240 of FIG. 2A, and the kernel 240 of FIG. When the signal INT2 is received, the interrupt handler can be called. When the IPC driver 220 of FIG. 2A learns that a message has been written to the second mailbox 423 through the interrupt handler, the IPC thread 222 of FIG. 5 reads the message of the device API 211 of FIG. 3 Function, the message written in the second mailbox 423 can be read.

According to the embodiment, the semaphore area 421 and the mailbox areas 422 and 423 may be implemented as an internal register 420 of the inter-processor communication device 400a. In one embodiment, semaphore area 421 and mailbox areas 422 and 423 may each be implemented as separate registers. In another embodiment, semaphore area 421 and mailbox areas 422 and 423 may be implemented as a single register. In one embodiment, the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 access the semaphore area 421 and the mailbox area 422 in a similar manner to accessing the shared storage area 412 , And 423 can be accessed. For example, a row address corresponding to any row of the shared storage area 412 may be assigned to the semaphore area 421 and the mailbox areas 422 and 423. That is, the semaphore area 421 and the mailbox areas 422 and 423 may be enabled instead of the row of the shared storage area 412 when an address between a specific address, for example, 1FFF800h to 1FFFFFFh is applied. According to the embodiment, the inter-processor communication device 400a further includes a register access circuit for preventing access to the memory cells corresponding to the specific address and for enabling the semaphore area 421 and the mailbox areas 422 and 423 .

For example, when data is transmitted from the first processor 200 of FIG. 1 to the second processor 300 of FIG. 1, the first processor 200 of FIG. 1 utilizes the mailbox areas 422 and 423 It is possible to acquire ownership of the shared storage area 412 through message transmission. 1 writes data packets to the channel of the shared storage area 412 and writes the data transfer command and the data transfer information in the first mailbox 422, 2 processor 300 may read the data packets without further analysis of the data packets based on the data transfer command and the data transfer information. In addition, the inter-processor data transfer rate can be improved through the burst transfer which can minimize the ownership exchange between the first processor 200 of FIG. 1 and the second processor 300 of FIG.

9 is a block diagram illustrating a shared storage area included in the inter-processor communication device of FIG.

Referring to FIG. 9, the shared storage area 412 includes a plurality of channels CH1, CH2, and CHN. Each of the plurality of channels CH1, CH2 and CHN includes first buffers TX_BUF11, TX_BUF12, TX_BUF13, TX_BUF1L, TX_BUF21, TX_BUF22, TX_BUF23, TX_BUF2L, TX_BUFN1, TX_BUFN2, TX_BUFN3, TX_BUFNL and second buffers RX_BUF11, RX_BUF12, RX_BUF13, RX_BUF1M, RX_BUF21, RX_BUF22, RX_BUF23, RX_BUF2M, RX_BUFN1, RX_BUFN2, RX_BUFN3, RX_BUFNM.

The number and size of the first buffers (TX_BUF11, TX_BUF12, TX_BUF13, TX_BUF1L, TX_BUF21, TX_BUF22, TX_BUF23, TX_BUF2L, TX_BUFN1, TX_BUFN2, TX_BUFN3, TX_BUFNL) included in each of the plurality of channels CH1, CH2, The number and size of the second buffers RX_BUF11, RX_BUF12, RX_BUF13, RX_BUF1M, RX_BUF21, RX_BUF22, RX_BUF23, RX_BUF2M, RX_BUFN1, RX_BUFN2, RX_BUFN3, RX_BUFNM may be variously changed according to the embodiment. The number and size of the plurality of channels (CH1, CH2, CHN) may also be variously changed according to the embodiment.

Each of the plurality of channels (CH1, CH2, CHN) stores a plurality of data packets. According to an embodiment of the present invention, a channel (CH 1, CH 2, CH 3) in which a plurality of data packets transmitted or received by the application is stored according to an application executed in the first processor 200 of FIG. 1 or the second processor 300 of FIG. CHN) can be determined. In other words, since a position where a plurality of data packets are stored is determined, the processor that transmits the plurality of data packets does not need to add a header such as a location stored in each data packet, designation of an application to be received , The processor that receives the plurality of data packets does not need to perform processing such as analyzing each data packet to identify a specified application. Thus, processing for interprocessor communication can be implemented simply.

In one embodiment, the plurality of channels (CH1, CH2, CHN) of the shared storage area 412 may correspond to a plurality of IPC channels 223 of the IPC driver 200 of FIG. For example, the first channel CH1 of the shared storage area 412 corresponds to the first channel IPC CH1 of the IPC driver 200 of FIG. 5, and the second channel CH1 of the shared storage area 412 corresponds to the first channel CH2 may correspond to the second channel (IPC CH2) of the IPC driver 200 of FIG. In this case, a plurality of data packets stored in the shared storage area 412 from the first channel (IPC CH1) of the IPC driver 200 of FIG. 5 may be written to the first channel CH1, A plurality of data packets stored in the shared storage area 412 from the second channel (IPC CH2) of the driver 200 can be written to the second channel (CH2). When a plurality of data packets stored in the first channel CH1 are read out, the first channel (IPC CH1) of the IPC driver 200 of FIG. 5 stores the plurality of data packets or the pointer of the plurality of data packets Can be stored. In one embodiment, a first application running in the first processor 200 of FIG. 1 may specify a first IPC channel by opening an IPC channel, A second application executed in the second processor 300 of FIG. 2 may also be designated to correspond to any one of the channels CH1, CH2, CHN, Lt; RTI ID = 0.0 > IPC < / RTI > Accordingly, the plurality of data packets transmitted in the first application can be received by the second application without analyzing a separate data packet, and the plurality of data packets transmitted in the second application can be received in a separate data packet Can be received by the first application without being analyzed.

The shared storage area 412 includes a plurality of channels CH1, CH2, CHN, and the IPC driver executing in each processor includes a plurality of IPC channels, so that the corresponding IPC Service-parallel communication of an application or an application that efficiently transmits data packets through a channel and a corresponding channel of the shared storage area 412 is possible. In addition, one or more IPC channels and one or more channels of the shared storage area 412 may be designated for each service of an application or an application, so that a data packet can be transmitted without extracting a header of the data packet and analyzing the extracted header The data transmission speed of the system can be improved.

FIG. 10 is a block diagram illustrating a channel included in the shared storage area of FIG. 9, and FIG. 11 is a diagram illustrating a data packet stored in a buffer included in the channel of FIG.

Referring to FIG. 10, the channel CH1 includes first buffers TX_BUF11, TX_BUF12, TX_BUF13, and TX_BUF1L and second buffers RX_BUF11, RX_BUF12, RX_BUF13, and RX_BUF1M.

The first buffers TX_BUF11, TX_BUF12, TX_BUF13 and TX_BUF1L may be buffers in which a plurality of data packets transmitted from the first processor 200 of FIG. 1 to the second processor 300 of FIG. 1 are stored, The buffers RX_BUF11, RX_BUF12, RX_BUF13, and RX_BUF1M may be buffers in which a plurality of data packets transmitted from the second processor 300 of FIG. 1 to the first processor 200 of FIG. 1 are stored. That is, the location where a plurality of data packets are stored is determined according to the transmission direction, so that an algorithm for processing for inter-processor communication can be implemented more simply.

The sizes of the first buffers TX_BUF11, TX_BUF12, TX_BUF13 and TX_BUF1L and the second buffers RX_BUF11, RX_BUF12, RX_BUF13 and RX_BUF1M can be fixed and the maximum size of each data packet 450 May be less than or equal to the size of each buffer. For example, the maximum size of the data packet 450 may be 2K + 4 bytes, and the size of the buffer may also be 2K + 4 bytes. By fixing the size of each buffer, each processor can easily grasp the address of the buffer in which any data packet 450 is stored. That is, even when a plurality of data packets are stored in the first buffers TX_BUF11, TX_BUF12, TX_BUF13, TX_BUF1L or the second buffers RX_BUF11, RX_BUF12, RX_BUF13, RX_BUF1M, Since the starting point of the stored position is the starting point of each buffer, the position of any data packet can be easily known.

Referring to FIG. 11, the data packet 450 may include a header PCK_SZ and a data area PCK_DATA. In one embodiment, the header (PCK_SZ) can have a fixed size, and the data area (PCK_DATA) can have a variable size. For example, the size of the header PCK_SZ may be 4 bytes, the size of the data area PCK_DATA may be equal to the size of the valid data, and the maximum size may be 2K bytes. In one embodiment, the size of the entire packet data or the valid data may be stored in the header (PCK_SZ). Valid data can be stored in the data area PCK_DATA. In one embodiment, only the size of the entire packet data or valid data can be stored in the header (PCK_SZ) without storing information on designation of a separate destination processor, designation of a target application, designation of an objective service, and the like. Accordingly, the algorithm for processing the data packet 450 can be implemented more simply.

FIG. 12 is a block diagram showing a mail box included in the inter-processor communication apparatus of FIG. 2, and FIG. 13 is a diagram showing an example of commands stored in the command storage area included in the mail box of FIG.

Referring to FIG. 12, the mailbox 422 includes a command storage area 441, a channel index storage area 442, and a packet number storage area 443. For example, the mailbox 422 of FIG. 12 may be a first mailbox 422 of FIG. 2 in which a message sent from the first processor 200 of FIG. 1 to the second processor 300 of FIG. 1 is stored. . According to the embodiment, the mailbox 422 may further include a separate storage area in addition to the command storage area 441, the channel index storage area 442, and the packet number storage area 443.

The command storage area 441 is an area where a command indicating the type of a message transmitted between processors is stored. Depending on the type of message, the message may only include the command and may include the command and additional information.

12 and 13, the command stored in the command storage area 441 includes a command for requesting ownership, a command for releasing ownership, a command for holding a transfer pending, a command for resuming transmission, a command for transmission completion, a command for channel status, , A request cancellation command, and an error command.

For example, the ownership request command is a command that requests a processor to request ownership of the shared storage area by another processor, and the ownership release command is a command informing that the ownership has been released in response to the ownership request command, The hold command is stored in the data packet queue of the processor that receives the data packets, that is, the data packet queue 225 of the IPC channel 223a of FIG. 7, The resume transmission command is a command requesting to resume the suspended data transmission in response to the transmission suspend command, and the transmission complete command indicates that writing of data packets to be transmitted in the processor to the shared storage area is completed And the channel The TA command is a command to inform the status of each channel of the shared storage area, and the transmission completion and ownership request command releases ownership of the shared storage area after reading of the written data packets with completion of writing of data packets The request cancellation command is a command for canceling the transmitted command, and the error command is a command for notifying that an error has occurred during inter-processor communication. In Fig. 13, nine commands are described. However, according to the embodiment, other commands than the above commands may be used, or some of the commands may be used. In one embodiment, the command storage area 441 may have a capacity of 8 bits.

A message transmitted between processors may further include additional information depending on the type of message, i.e., a command. For example, in the case of a message including the transmission complete command, the message may include the index of the channel in which the data packets are written together with the transmission completion command and / or the number of data packets.

The channel index storage area 442 may store an index of a channel included in the shared storage area. For example, when a first processor transmits a plurality of data packets to a second processor, the first processor writes the plurality of data packets to a particular channel of the shared storage area, and the first processor stores a command The transmission completion command is written in the area 441 and the index for the specific channel in which the plurality of data packets are written in the channel index storage area 442 can be written. The second processor may know the locations, i.e., addresses, of the plurality of data packets stored based on the index for the particular channel. Further, in one embodiment, the IPC driver running on the second processor may know the location where the plurality of data packets are stored based on the index for the particular channel stored in the channel index storage area 442. [ Accordingly, the IPC driver may not perform a separate analysis to designate the associated IPC channel and application after reading the plurality of data packets. In one embodiment, the channel index storage area 442 may store an index for one channel. In another embodiment, each bit of the channel index storage area 442 is associated with a corresponding channel, and may indicate whether a plurality of data packets are stored in the corresponding channel according to the value of each bit.

The number-of-packets storage area 443 may store the number of the plurality of data packets written in the channel. For example, when the first processor transmits a plurality of data packets to the second processor, the first processor writes the plurality of data packets to a specific channel of the shared storage area, and the command storage area 441 Write the index of the specific channel in the channel index storage area 442 and write the number of the plurality of data packets in the packet number storage area 443. The second processor may not perform processing for extracting a header of each of the plurality of data packets and analyzing an associated IPC channel, an associated application, a number of packets, and the like. Thus, the processing for inter-processor communication can be simply implemented, and the data transmission speed of the system can be improved.

14 is a flow chart illustrating how a message is transferred from a first processor to a second processor included in the system of FIG.

1, 8, and 14, when a message including command and data transmission information or a message including only a command is transmitted from the first processor 200 to the second processor 300, The controller 200 writes the command and / or data transmission information in the first mailbox 422 (step S110). In one embodiment, the IPC driver running on the first processor 200 can write a message to the first mailbox 422 by calling the message writing function of the device API. The inter-processor communication device 400 generates a first interrupt signal INT1 when a message written to or stored in the first mailbox 422 is changed (step S130). The second processor 300 receives the first interrupt signal INT1 from the inter-processor communication device 400 (step S150). When the second processor 300 receives the first interrupt signal INT1, the second processor 300 reads the message stored in the first mailbox 422 (step S170). In one embodiment, the kernel executing in the second processor 300 calls the interrupt handler of the IPC driver corresponding to the first interrupt signal INT1, and the IPC driver calls the message read function of the device API, The message stored in the mailbox 422 can be read.

FIG. 15 is a flowchart illustrating a method for a first processor included in the system of FIG. 1 to acquire ownership of a shared storage area included in the inter-processor communication apparatus of FIG.

Referring to FIGS. 1, 8 and 15, the first processor 200 reads the ownership of the shared storage area 412 stored in the semaphore area 421, thereby obtaining ownership of the shared storage area 412 (Step S211). In one embodiment, the IPC driver running in the first processor 200 may read the ownership information stored in the semaphore region 421 by calling the device API's ownership validation function. If the first processor 200 has ownership of the shared storage area 412 (step S213: YES), the first processor 200 does not need to further process the ownership of the shared storage area 412 .

If the second processor 300 has ownership of the shared storage area 412 (step S213: NO), the first processor 200 writes the ownership request command to the first mailbox 422 S215). In one embodiment, the IPC driver running on the first processor 200 writes the ownership request command to the first mailbox 422 by calling the message writing function of the device API with a parameter representing the ownership request command .

When the ownership request command is written in the first mailbox 422, the inter-processor communication device 400 or 400a generates a first interrupt signal INT1 indicating that a message has been written in the first mailbox 422 Step S217). When the second processor 300 receives the first interrupt signal INT1 (step S219), the second processor 300 reads the ownership request command from the first mailbox 422 (step S221). In one embodiment, the kernel executed in the second processor 300 calls the interrupt handler of the IPC driver corresponding to the first interrupt signal INT1, and the IPC driver executed in the second processor 300 calls the device API To read the ownership request command stored in the first mailbox 422 by calling the message read function of the first mailbox 422. [

The second processor 300, which is requested to transfer ownership from the first processor 200, writes the ownership release command in the second mailbox 423 as a response to the ownership request command (step S223). In one embodiment, the IPC driver running on the second processor 300 writes the ownership release command to the second mailbox 423 by calling the message write function of the device API with a parameter indicating the ownership release command .

In one embodiment, the second processor 300 may access the semaphore area 421 to change information about ownership stored in the semaphore area 421. [ According to an embodiment, when the second processor 300 needs to continuously access the shared storage area 412, the second processor 300 writes a command to disable ownership in the second mailbox 423 , The first processor 200 writes a request cancellation command to the first mailbox 422 after waiting for a certain period of time or the first processor 200 writes the ownership request command to the first mailbox 422 without any message transmission, Can be rewritten. In another embodiment, the second processor 300 that has received the deallocation command may forcibly stop access to the shared storage area 412 and send the deallocation command to the first processor 200 .

When the ownership release command is written in the second mailbox 423, the inter-processor communication device 400 or 400a generates a second interrupt signal INT2 indicating that the message has been written in the second mailbox 423 Step S225). When the first processor 200 receives the second interrupt signal INT2 (step S227), the first processor 200 reads the ownership release command from the second mailbox 423 (step S229). In one embodiment, the kernel executed in the first processor 200 calls the interrupt handler of the IPC driver corresponding to the second interrupt signal INT2, and the IPC driver, which is executed in the first processor 200, Can read the ownership release command stored in the second mailbox 423 by calling the message read function of the second mailbox 423. In one embodiment, the first processor 200 may access the semaphore area 421 to change information about ownership stored in the semaphore area 421. [ Accordingly, the first processor 200 can acquire ownership of the shared storage area 412. [

16 is a flowchart showing a method of transferring data between processors in the system of FIG.

Referring to FIGS. 1 to 16, the first processor 200 acquires ownership of the shared storage area 412 through the method shown in FIG. 15 (step S310). After the first processor 200 acquires the ownership, that is, access to the shared storage area 412, the first processor 200 writes the data packets in the shared storage area 412 (step S620). For example, when data communication is performed between the first application 230 of the first processor 200 and the second application of the second processor 300, the first application 230 of the first processor 200, The second application of the second processor 300 may use the channel open function of the first IPC API 221 to use the first IPC channel IPC CH1 and the second application of the second processor 300 may call the channel open function of the second IPC API 221 A second IPC channel can be used. In addition, the first application 230 of the first processor 200 may call the data packet transmission function of the first IPC API 221 to write the data packets to the shared storage area 412. When the data packet transmission function of the first IPC API 221 is called, information on the data packets, i.e., pointers and lengths of the data packets, are stored in the first IPC channel (IPC CH1) (222) accesses the shared storage area (412) by calling the data packet writing function of the first device API (211) based on the information about the data packets stored in the first IPC channel (IPC CH1) Can be written. For example, the data packets may be stored in a first channel (CH1) corresponding to a first IPC channel (IPC CH1) of the shared storage area 412.

After the first processor 200 writes the data packets to the shared storage area 412, the first processor 200 sends a message indicating that there is data in the first mailbox 422, i.e., a data transfer command and data The transmission information is written (step S330). That is, the first processor 200 writes the data transfer command in the command storage area 441, writes the index of the channel in which the data packets are written in the channel index storage area 442, ) Of the data packets. For example, the first IPC thread 222 of the first processor 200 calls the message write function of the first device API 211 to send the data transfer command to the first mailbox 422, (CH1), and the number of data packets.

When the data transfer command and the data transfer information are written in the first mailbox 422, the inter-processor communication device 400 generates the first interrupt signal INT1 (step S340). When the second processor 300 receives the first interrupt signal INT1 from the inter-processor communication device 400 in step S350, the second processor 300 receives the data transfer command and the data transfer command from the first mailbox 422, And reads the data transmission information (step S360). That is, the second processor 300 reads the data transfer command from the command storage area 441, reads the index of the channel in which the data packets are written from the channel index storage area 442, 443). ≪ / RTI > For example, when the second processor 300 receives the first interrupt signal INT1, the second IPC thread of the second processor 300 calls the message read function of the second device API to call the first mailbox 422 to read the data transfer command and the data transfer information.

Based on the index of the channel and the number of data packets, the second processor 300 reads the data packets from the shared storage area 412 (step S370). For example, the second IPC thread may use the index of the first channel CH1 read from the channel index storage area 442 and the number of the data packets read from the packet number storage area 443 as parameters, By reading the data packet read function of the API, the data packets stored in the first channel (CH1) can be read out. In one embodiment, the second device API may copy the data packets stored in the shared storage area 412 to the second dedicated storage area 413, 414 when reading the data packets. The second IPC thread of the second processor 300 may also store information about the data packets stored in the second dedicated storage area 413 and 414 in the second IPC channel of the second processor 300, 2 dedicated storage areas 413 and 414, as shown in FIG. Also, the second application may receive pointers and lengths of the second IPC channel through the data packet reception function of the second IPC API. The second application may process the data packets using the provided pointers and the lengths. For example, the second application may output an image corresponding to the data packets through a display or output a voice corresponding to the data packets through a speaker. The second application may release the space for the data packets in the second dedicated storage area (413, 414) when it is no longer necessary to access the data packets.

In this manner, the second processor 300 receives the information on the data packets through the first mailbox 422, and transmits the data packets to the designated application without any processing on the data packets. Data packets. Further, by performing inter-processor data communication through a plurality of IPC channels and a plurality of channels of the shared storage area, one or more IPC channels and one or more channels of the shared storage area can be dedicated for each application or application service, The transmission speed can be further improved.

17 is a diagram showing operations of modules in data transmission and reception in a processor included in the system of FIG.

Referring to FIG. 17, the processor 200 executes the device driver 210, the IPC driver 220, and the application 230. 17 shows a system in which only one processor 200 is connected to the inter-processor communication device 400 for convenience of explanation, however, the inter-processor communication device 400 is further connected to one or more processors, 200). ≪ / RTI >

The IPC API 221 of the IPC driver 220 uses the pointer of the data packet stored in the first application buffer 511 allocated by the application 230 as a parameter to transmit the data packet from the processor 200 to another processor. Call the data packet transmission function. For example, the application 230 may allocate a first application buffer 511 to the first dedicated storage area 411 of FIG. The IPC driver 220 may store the pointer of the data packet in the first IPC buffer 513, that is, the pointer of the first application buffer 511. [ For example, the first IPC buffer 513 may be the first transmit buffer 2241 of the data packet transmit queue 224 of FIG. 7, and the IPC driver 220 may transmit the data packet transmit queue 224 of FIG. The length of the data packet and / or the pointer of the data packet may be stored in the first transmission buffer 2241 of FIG. The IPC driver 220 stores the pointer of the data packet so that when the data packet is transmitted from the application 230 to the IPC driver 220, the copy operation for the data packet is not performed, The transmission / reception processing speed can be improved.

The IPC driver 220 calls the data packet write function of the device API 211 of the device driver 230 with the pointer of the data packet stored in the first IPC buffer 513 as a parameter. The device driver 230 writes the data packet to the first buffer 517 of the inter-processor communication device 400. For example, the device driver 230 may copy the data packet stored in the first dedicated storage area 411 of FIG. 8 to the shared storage area 412 of FIG. For example, the first buffer 517 of the inter-processor communication device 400 may be the first buffer TX_BUF11 of the first channel CH1 of FIG. The other processor reads the data packet stored in the shared storage area 412 of the inter-processor communication device 400 so that the data packet can be transferred from the application 230 of the processor 200 to the application of the other processor have.

The device driver 230 reads the data packet stored in the second buffer 521 of the inter-processor communication device 400. In this case, For example, the second buffer 521 of the inter-processor communication device 400 may be the second buffer RX_BUF11 of the first channel CH1 of FIG. For example, the IPC thread 222 of the IPC driver 220 may allocate a second IPC buffer 525, which is a storage space for the data packet, to the second dedicated storage areas 413 and 414 of FIG. 8, The data packet read function of the device API 211 of the driver 230 can be called. The device driver 230 may copy the data packet stored in the shared storage area 412 of FIG. 8 to the second IPC buffer 525, that is, the second dedicated storage area 413 and 414 of FIG. The IPC driver 220 also receives a pointer to the data packet (a pointer to the second IPC buffer 525) and / or a pointer to the data packet in the first receive buffer 2251 of the data packet receive queue 225 of FIG. You can store the length.

The IPC driver 220 transfers the pointer of the data packet to the application 230. For example, the IPC driver 220 may send a pointer to the data packet stored in the first receive buffer 2251 of the data packet receive queue 225 of FIG. 7, that is, a pointer of the second IPC buffer 525, ). In one embodiment, the application 230 calls the data packet receive function of the IPC API 221 of the IPC driver 220, and the IPC driver 220 receives the pointer of the data packet as the return value of the data packet receive function To the application (230). In another embodiment, the application 230 calls the data packet receive function of the IPC API 221 of the IPC driver 220 with the function pointer as a parameter, and the IPC driver 220 calls the function of the application 230 And send a pointer to the data packet to the application 230 by calling. In another embodiment, the IPC driver 220 may send a pointer to the data packet to the application 230 by sending an event or message to the application 230. The data packet may be transmitted from the application of the other processor to the application of the processor 200. [ As described above, when the IPC driver 220 transmits the pointer of the data packet to the application 230, when the data packet is transmitted from the IPC driver 220 to the application 230, ) Operation is not performed, so that the data packet transmission / reception processing speed can be improved.

Hereinafter, an overflow prevention function for controlling data packet transmission for each channel of the IPC channel and the corresponding shared storage area in the system 100 of FIG. 1 will be described.

FIG. 18A is a diagram showing a transmission stop operation when data packets are transmitted in the system of FIG. 1, and FIG. 18B is a diagram showing a transmission restart operation when data packets are transmitted in the system of FIG.

18A, the third to fifth data packets PCK3 and PCK4 to be transmitted to the second processor 300 are transmitted to the data packet transmission queue 224a of the first IPC driver 220 of the first processor 200, And the first and second data packets received from the first processor 200 are stored in the data packet reception queue 325a of the second IPC driver 320 of the second processor 300, (PCK1, PCK2) are stored (step S400). The first processor 200 obtains ownership of the shared storage area 412 of FIG. 8 to transmit the third to fifth data packets PCK3, PCK4, PCK5 to the second processor 300 S410). For example, the first IPC driver 220 may write the ownership request command to the first mailbox 422a by calling the message writing function of the first device driver 210 provided in the device API, The driver 320 can read the ownership request command stored in the first mailbox 422a by calling the message read function of the second device driver 310 provided in the device API. Also, the second IPC driver 320 may write a command for releasing ownership to the second mailbox 423a by calling the message write function of the second device driver 310, and the first IPC driver 220 may write It is possible to read the ownership release command stored in the second mailbox 423a by calling the message read function of the first device driver 210. [

The first processor 200 acquiring ownership of the shared storage area 412 of FIG. 8 transmits the third to fifth data packets PCK3, PCK4 and PCK5 to the second processor 300 (step S420 ). For example, the first IPC driver 220 calls the data packet writing function of the first device driver 210 to write the third to fifth data packets (CH1a) to the channel CH1a of the shared storage area 412 (PCK3, PCK4, PCK5) can be written. The first IPC driver 220 calls the message write function of the first device driver 210 to transmit the transfer complete command and the third to fifth data packets PCK3, PCK4, PCK5 to the first mailbox 422b It is possible to write the data transmission information for the data. The data transmission information may include the index of the channel CH1a storing the third to fifth data packets PCK3, PCK4 and PCK5 and the number of the third to fifth data packets PCK3, PCK4 and PCK5 have. The second IPC driver 320 may read the transmission completion command and the data transmission information stored in the first mailbox 422a by calling the message reading function of the second device driver 310. [ The second IPC driver 320 calls the data packet read function of the second device driver 310 based on the data transmission information to transmit the third to fifth data packets PCK3, PCK4, PCK5). When the second processor 300 receives the third to fifth data packets PCK3, PCK4 and PCK5, the data packet reception queue 325b of the second IPC driver 320 receives the first to fifth data packets (PCK1, PCK2, PCK3, PCK4, PCK5) can be stored. If data packets or pointers of data packets exceeding the number of reception buffers are stored in the data packet reception queue 325b of the second IPC driver 320, data packets may be lost or data packet reception may be delayed. To prevent this, when data packets or pointers to data packets exceeding the stop threshold are stored in the data packet reception queue 325b, the data packet transmission through the channel CH1a corresponding to the data packet reception queue 325b is suspended .

The pointers of the first to fifth data packets PCK1, PCK2, PCK3, PCK4 and PCK5 exceeding the stop threshold are stored in the data packet reception queue 325b, 200 to suspend the transmission of the data packet to the channel CH1a (step S430). For example, the stop threshold of the data packet receive queue 325b may be four. When the pointers of the five data packets PCK1, PCK2, PCK3, PCK4 and PCK5 are stored in the data packet reception queue 325b and the stop threshold is exceeded, the second IPC driver 320 transmits the second device driver 310 to write the transmission hold command and the index of the channel CH1a in the second mailbox 423b. The first IPC driver 220 may read the index of the transmission hold command and the channel CH1a stored in the second mailbox 423b by calling the message read function of the first device driver 210. [ Accordingly, the first processor 200 can be requested to suspend the transmission of the data packet to the channel CH1a corresponding to the data packet reception queue 325b, and the second processor The first processor 200 transmits the sixth and seventh data packets PCK6 and PCK7 even if pointers to the sixth and seventh data packets PCK6 and PCK7 to be transmitted to the first processor 200 are stored You can pause.

18B, the first to third data packets PCK1, PCK2, PCK3, PCK4 and PCK5 of the first to fifth data packets PCK1, PCK2, PCK3, PCK4 and PCK5 in the data packet reception queue 325b of FIG. PCK3 are transferred to and removed from the corresponding application, the data packet reception queue 325c may store pointers to the fourth and fifth data packets PCK4 and PCK5. The second processor 300 may request the first processor 200 to resume the transmission of data packets to the channel CH1a if the pointers of data packets below the resume threshold are stored in the data packet reception queue 325c (Step S440). For example, the resume threshold of the data packet receive queue 325c may be two. The second IPC driver 320 calls the message write function of the second device driver 310 when the pointers of the two data packets PCK4 and PCK5 are stored in the data packet reception queue 325b and are below the resume threshold , The transmission resume command and the index of the channel CH1a can be written in the second mailbox 423c. The first IPC driver 220 may call the message read function of the first device driver 210 to read the transfer resume command stored in the second mailbox 423c and the index of the channel CH1a. Accordingly, the first processor 200 may be requested to resume transmission of data packets to the channel CH1a corresponding to the data packet reception queue 325c.

The first processor 200 requesting the resumption of the data packet transmission to the channel CH1a transmits the sixth and seventh data packets PCK6 and PCK7 of the data packet reception queue 224c shown in FIG. To the processor 300 (step S450). For example, the first IPC driver 220 calls the data packet write function of the first device driver 210 to write the sixth and seventh data packets (CH1b) in the channel CH1b of the shared storage area 412 of FIG. 8 (PCK6, PCK7) can be written. The first IPC driver 220 may call the message write function of the first device driver 210 to write the transmission complete command, the index of the channel CH1b, and the number of data packets in the first mailbox 422c . The second IPC driver 320 calls the message reading function of the second device driver 310 to read the transmission completion command stored in the first mailbox 422a and the index of the channel CH1b and the number of data packets . The second IPC driver 320 calls the data packet read function of the second device driver 310 based on the index of the channel CH1b and the number of data packets, And receive data packets PCK6 and PCK7. In addition, pointers of the fourth to seventh data packets PCK4, PCK5, PCK6 and PCK7 may be stored in the data packet reception queue 325d.

By controlling the data packet transmission for each channel of the IPC channel and the corresponding shared storage area, it is possible to prevent data packet overflow of the channel of the IPC channel and the corresponding shared storage area, And can support stable data packet transmission.

Hereinafter, the transmission of a single mode data packet and the burst mode data packet transmission in the system 100 of FIG. 1 will be described.

FIG. 19A is a diagram showing a data packet transmission method in a single mode in the system of FIG. 1, and FIG. 19B is a diagram showing a data packet transmission method in a burst mode in the system of FIG.

19A, the first to third data packets PCK1 and PCK2 to be transmitted to the second processor 300 are transmitted to the data packet transmission queue 224e of the first IPC driver 220 of the first processor 200, , PCK3) are stored (step S500). The first processor 200 obtains ownership of the shared storage area 412 of FIG. 8 to transmit the first to third data packets PCK1, PCK2, PCK3 to the second processor 300 S510). For example, the first IPC driver 220 may write the ownership request command to the first mailbox 422e by calling the message writing function of the first device driver 210 provided in the device API, The driver 320 can read the ownership request command stored in the first mailbox 422e by calling the message read function of the second device driver 310 provided in the device API. Also, the second IPC driver 320 can write the ownership release command in the second mailbox 423e by calling the message write function of the second device driver 310, and the first IPC driver 220 1 device driver 210 to read the ownership release command stored in the second mailbox 423e.

In the single mode, the first processor 200 acquiring ownership of the shared storage area 412 of FIG. 8 transmits the first data packet PCK1 to the second processor 300 (step S520). For example, the first IPC driver 220 calls the data packet write function of the first device driver 210 to write the first data packet PCK1 in the channel CH1c of the shared storage area 412 in FIG. 8 Can be written. The first IPC driver 220 may call the message write function of the first device driver 210 to write the transfer complete command and the data transfer information for the first data packet PCK1 in the first mailbox 422f have. The data transmission information may include an index of a channel CH1c in which the first data packet PCK1 is stored. In one embodiment, the data transmission information may further include a data packet number, and in a single mode, the value of the data packet number may be one. The second IPC driver 320 may read the transmission completion command and the data transmission information stored in the first mailbox 422f by calling the message reading function of the second device driver 310. [ The second IPC driver 320 can receive the first data packet PCK1 stored in the channel CH1c by calling the data packet read function of the second device driver 310 based on the data transmission information. When the second processor 300 receives the first data packet PCK1, the pointers of the second and third data packets PCK2 and PCK3 are transmitted to the data packet transmission queue 224f of the first IPC driver 220 And the pointer of the first data packet PCK1 may be stored in the data packet reception queue 325f of the second IPC driver 320. [

In the single mode, the first processor 200 that has transmitted the first data packet PCK1 reacquires ownership of the shared storage area 412 of FIG. 8 to transmit the second data packet PCK2 S530). The first processor 200 having acquired the ownership transmits the second data packet PCK2 to the second processor 300 (step S540). In addition, the first processor 200 that has transmitted the second data packet PCK2 obtains the ownership again to transmit the third data packet PCK3 (step S550). The first processor 200 having acquired the ownership transmits the third data packet PCK3 to the second processor 300 (step S560).

As described above, in the single mode, whenever one data packet is transmitted between processors, communication for exchange of ownership is required. The system according to an embodiment of the present invention supports data packet transmission in a burst mode in addition to data packet transmission in the single mode.

19B, the first to third data packets PCK1 and PCK2 to be transmitted to the second processor 300 are transmitted to the data packet transmission queue 224i of the first IPC driver 220 of the first processor 200, , PCK3) are stored (step S600). The first processor 200 obtains ownership of the shared storage area 412 of FIG. 8 to transmit the first to third data packets PCK1, PCK2, PCK3 to the second processor 300 S610). For example, the first IPC driver 220 may write the ownership request command to the first mailbox 422i by calling the message writing function of the first device driver 210 provided in the device API, The driver 320 may read the ownership request command stored in the first mailbox 422i by calling the message read function of the second device driver 310 provided in the device API. Also, the second IPC driver 320 can write the ownership release command to the second mailbox 423i by calling the message write function of the second device driver 310, and the first IPC driver 220 1 device driver 210 to read the ownership release command stored in the second mailbox 423i.

In the burst mode, the first processor 200 acquiring ownership of the shared storage area 412 of FIG. 8 transmits the first to third data packets PCK1, PCK2 and PCK3 to the second processor 300 (Step S620). For example, the first IPC driver 220 may call the data packet write function of the first device driver 210 to write the first to third data packets < RTI ID = 0.0 > (PCK1, PCK2, PCK3) can be written. The first IPC driver 220 calls the message write function of the first device driver 210 to send the transfer complete command and the first to third data packets PCK1, PCK2, PCK3 to the first mailbox 422j It is possible to write the data transmission information for the data. The data transmission information may include an index of the channel CH1i and the number of data packets. The second IPC driver 320 may read the transmission completion command and the data transmission information stored in the first mailbox 422j by calling the message reading function of the second device driver 310. [ The second IPC driver 320 calls the data packet reading function of the second device driver 310 based on the data transmission information to transmit the first to third data packets PCK1, PCK2, PCK3).

As such, in burst mode, communication for ownership exchange can be performed less than once and multiple data packets can be transferred from one processor to another at a time. Accordingly, it is possible to transmit a large amount of data without the overhead of ownership exchange through such burst transmission, and to improve the data transmission speed of the system.

20 is a diagram showing a data transfer rate of the system of FIG. 1 in the single mode and the burst mode.

Referring to FIG. 20, it can be seen that the data transfer rates 720 and 730 in the burst mode are higher than the data transfer rate 710 in the single mode. 20 shows the data transfer rate of the system 100 of FIG. 1 when the operating frequency of the first processor 200 of FIG. 1 is about 282 MHz and the operating frequency of the second processor 300 of FIG. 1 is about 533 MHz. An example is shown. For example, in a single mode, when a data packet of 1024 bytes is transmitted, the data transmission speed is about 1.4 Mbps. When transmitting a 1500 byte data packet, the data transmission speed is about 2.3 Mbps. When transmitting, the data transmission rate may be about 3.0 Mbps. For example, in burst mode, when bursting 10 data packets, that is 10 data packets without acquiring additional ownership after acquiring ownership once, when transmitting a 1024 Byte data packet, the data transfer rate is about 13.7 Mbps . When the data packet of 1500 bytes is transmitted, the data transmission speed is about 21.7 Mbps. When the data packet of 2048 bytes is transmitted, the data transmission speed may be about 26.7 Mbps. Also, for example, in the burst mode, when transmitting 20 data packets with burst transfer, that is, after acquiring ownership once, without additional ownership acquisition, when the data packet of 1024 Byte is transmitted, the data transfer rate is about 20.0 Mbps, and a data packet of 1500 bytes is transmitted at a data transmission speed of about 28.7 Mbps. When a data packet of 2048 bytes is transmitted, a data transmission speed may be about 36.7 Mbps. As shown in FIG. 20, the data transmission rate of the system can be improved through burst transmission.

21 is a block diagram illustrating a system in accordance with an embodiment of the present invention.

21, a system 900 includes a first processor 910, a second processor 920, an inter-processor communication device 930, an antenna 940, a flash memory 950, a liquid crystal display 960, A speaker 970, an input device 980, and a bus 990. In one embodiment, the system 900 may be a portable device. For example, the system 900 may be a personal digital assistant (PDA), a portable multimedia player (PMP), a mobile phone, a smart phone, a mobile TV, a navigation device, .

The first processor 910 and the second processor 920 are connected to the inter-processor communication device 930, respectively. 21 shows a system 900 that includes two processors 910 and 920 connected to an inter-processor communication device 930, respectively, but in accordance with an embodiment, the inter-processor communication device 930 may include three or more processors Lt; / RTI >

In one embodiment, the first processor 910 demodulates and provides the communication signal received from the antenna 940 to the second processor 920, modulates the data received from the second processor 920, ) To the outside via a modem. For example, the first processor 910 may be a modem processor supporting communication such as GSM, GPRS, WCDMA, HSxPA, and the like. In addition, the second processor may be an application processor or a multimedia processor in which applications providing an Internet browser, a three-dimensional map, a game, a moving picture, and the like are executed. The inter-processor communication device 930 includes a shared storage area for data transfer between the first processor 910 and the second processor 920, a first storage area for data transmission between the first processor 910 and the second processor 920, A dedicated storage area, a code of a program executed in the second processor 920, and a second dedicated storage area in which data is stored. In one embodiment, the inter-processor communication device 930 may be a dynamic random access memory (DRAM). According to an embodiment, the first processor 910, the second processor 920, and the inter-processor communication device 930 may be implemented as separate chips and may be implemented as a single chip.

In one embodiment, the first processor 910 may not be coupled to a separate storage device in addition to the inter-processor communication device 930. That is, the code and data of the program executed in the first processor 910 may be stored in the first dedicated storage area of the inter-processor communication device 930. [ For example, the code of the program executed by the first processor 910 may be transferred from the flash memory 950 or the file system (not shown) connected to the second processor 920 at the time of system boot to the second processor 920 via the second processor 920 And may be stored in the first dedicated storage area. In this case, the second processor 920 may access the first dedicated storage area at the time of booting the system, and may not access the first dedicated storage area after booting is completed. As such, system 900 can be reduced in size by not including a separate storage device for first processor 910.

The second processor 920 may be coupled to the flash memory 950. The flash memory 950 may store the boot code of the second processor 920 or the boot code of the first processor 910 and the second processor 920. The application code and / or data of the second processor 920 may be stored in the second dedicated storage area of the inter-processor communication device 930. Accordingly, the system 900 does not include a separate DRAM for application data storage of the second processor 920, so that the size of the system 900 can be further reduced.

The second processor 920 may also be connected to the liquid crystal display 960, the speaker 970 and the input device 980 via a bus 990. The second processor 920 is connected to the liquid crystal display 930 and the second processor 930 based on the communication data provided through the first processor 910 and the inter-processor communication device 930 and / / RTI > and / or audio data to the speaker 970. In this way,

As described above, the system 900 according to an embodiment of the present invention includes the inter-processor communication device 930 having a dedicated storage area and a shared storage area, thereby reducing the size of the entire system and reducing power consumption . In addition, the inter-processor communication device 930 can transmit data through the shared storage area and transmit the message through the mailbox, thereby efficiently performing data transmission. In addition, the inter-processor communication device 930 may support burst transmission to further improve the data transfer rate.

As described above, the processor, the system, and the computer readable recording medium on which the IPC driver is recorded according to the embodiments of the present invention provide one or more channels of IPC channels and shared storage areas per application / service, Can be efficiently performed. In addition, a computer-readable recording medium on which a processor, a system and an IPC driver are recorded according to embodiments of the present invention minimizes a data packet copying operation and minimizes a data packet overflow of an IPC channel and a channel of a corresponding shared storage area it is possible to prevent overflow of data packets and to support stable data packet transmission while maintaining a data transmission rate. In addition, the processor, system, and computer readable recording medium on which the IPC driver is written according to embodiments of the present invention can support burst transmission, thereby further improving the data transfer rate by reducing the overhead of ownership exchange.

The present invention can be usefully used in any system including a plurality of processors. Particularly, the present invention is more useful for portable devices such as a personal digital assistant (PDA), a portable multimedia player (PMP), a mobile phone, a smart phone, a mobile TV, a navigation device, Lt; / RTI >

While the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood.

1 is a block diagram illustrating a system according to an embodiment of the present invention.

FIG. 2A is a block diagram illustrating an example of modules executing in a processor included in the system of FIG. 1, and FIG. 2B is a block diagram illustrating another example of modules executing in a processor included in the system of FIG.

FIG. 3 is a block diagram showing the device driver shown in FIG. 2A or FIG. 2B, and FIG. 4 is a diagram showing an example of the device API shown in FIG.

5 is a block diagram showing the IPC driver shown in FIG. 2A or 2B, FIG. 6 is a diagram showing an example of the IPC API shown in FIG. 5, FIG. 7 is a diagram showing an example of the IPC channel shown in FIG. 5 Fig.

8 is a block diagram illustrating an inter-processor communication device included in the system of FIG.

9 is a block diagram illustrating a shared storage area included in the inter-processor communication device of FIG.

FIG. 10 is a block diagram illustrating a channel included in the shared storage area of FIG. 9, and FIG. 11 is a diagram illustrating a data packet stored in a buffer included in the channel of FIG.

FIG. 12 is a block diagram showing a mail box included in the inter-processor communication apparatus of FIG. 2, and FIG. 13 is a diagram showing an example of commands stored in the command storage area included in the mail box of FIG.

14 is a flow chart illustrating how a message is transferred from a first processor to a second processor included in the system of FIG.

FIG. 15 is a flowchart illustrating a method for a first processor included in the system of FIG. 1 to acquire ownership of a shared storage area included in the inter-processor communication apparatus of FIG.

16 is a flowchart showing a method of transferring data between processors in the system of FIG.

17 is a diagram showing operations of modules in data transmission and reception in a processor included in the system of FIG.

FIG. 18A is a diagram showing a transmission stop operation when data packets are transmitted in the system of FIG. 1, and FIG. 18B is a diagram showing a transmission restart operation when data packets are transmitted in the system of FIG.

FIG. 19A is a diagram showing a data packet transmission method in a single mode in the system of FIG. 1, and FIG. 19B is a diagram showing a data packet transmission method in a burst mode in the system of FIG.

20 is a diagram showing a data transfer rate of the system of FIG. 1 in the single mode and the burst mode.

21 is a block diagram illustrating a system in accordance with an embodiment of the present invention.

Description of the Related Art

100, 900: System

200, 200a, 200b, 300, 910, 920:

400, 400a, 930: interprocessor communication device

412: Shared Storage

Claims (20)

One or more applications for transmitting and receiving a plurality of data packets through inter-processor communication; An IPC driver for storing information on the plurality of data packets in any one of a plurality of IPC channels to provide a transmission path for the plurality of data packets to the application; And And a device driver for writing the plurality of data packets to the inter-processor communication device based on the information on the plurality of data packets stored in the one IPC channel, Wherein the application comprises a first application for transmitting and receiving the plurality of data packets and a second application for transmitting and receiving the plurality of data packets, Wherein the IPC driver stores information on the plurality of data packets of the first application on a first one of the plurality of IPC channels and transmits the second IPC channel to the second one of the plurality of IPC channels, And stores information about the plurality of data packets of the application. The IPC driver according to claim 1, An IPC API (application programming interface) provided to the application and requested to transmit the plurality of data packets; The plurality of IPC channels including any one of the IPC channels storing information on the plurality of data packets requested to be transmitted through the IPC API; And And an IPC thread for providing the device driver with information on the plurality of data packets stored in any one of the IPC channels. delete 3. The method of claim 2, wherein the one of the IPC channels comprises: A data packet transmission queue for storing pointers and lengths of a first plurality of data packets transmitted from the application to the inter-processor communication device; And And a data packet reception queue for storing pointers and lengths of a second plurality of data packets transmitted from the inter-processor communication device to the application. 5. The method of claim 4, Requesting the device driver to suspend transmission of a data packet to the data packet reception queue if the number of the second plurality of data packets storing pointers and lengths in the data packet reception queue is equal to or greater than a suspend threshold, If the number of the second plurality of data packets storing pointers and lengths in the data packet reception queue is less than or equal to the resume threshold after requesting the suspension of the data packet transmission, Requesting the resumption of transmission. delete delete delete One or more applications for transmitting and receiving a plurality of data packets through inter-processor communications, one or more applications for transmitting data packets to one of the plurality of inter-processor communication (IPC) channels to provide a transmission path for the plurality of data packets to the application An IPC driver for storing pointers and lengths for the plurality of data packets; and an IPC driver for storing the plurality of data packets in the interprocessor communication device based on pointers and lengths for the plurality of data packets stored in the one IPC channel. A plurality of processors each including a device driver for writing data packets of data; And Storing the plurality of data packets selectively received by the plurality of processors and received from the device driver included in each of the plurality of processors, and receiving commands transmitted between the plurality of processors and the stored plurality The interprocessor communication device storing data transmission information for the data packets of the interprocessor, Wherein the application comprises a first application for transmitting and receiving the plurality of data packets and a second application for transmitting and receiving the plurality of data packets, Wherein the IPC driver stores information on the plurality of data packets of the first application on a first one of the plurality of IPC channels and transmits the second IPC channel to the second one of the plurality of IPC channels, And stores information about the plurality of data packets of the application. 10. The inter-processor communication device according to claim 9, A plurality of ports coupled to the plurality of processors; A shared storage area that is selectively accessed by the plurality of processors through the plurality of ports and stores the plurality of data packets in one of the plurality of channels; And And a mailbox area connected to the plurality of ports and storing the command and the data transmission information. 11. The method of claim 10, Wherein the one of the plurality of data packets includes a plurality of buffers, Wherein each of the plurality of buffers stores any one of the plurality of data packets. 11. The information processing apparatus according to claim 10, A command storage area for storing the command; A channel index storage area for storing information on locations in the shared storage area of the plurality of data packets; And And a packet number storage area for storing information on the number of the plurality of data packets. 11. The inter-processor communication device according to claim 10, Further comprising a semaphore area for storing information about ownership of the shared storage area. delete delete delete delete delete delete delete

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