KR20090128605A - Inter-processor communication device having burst transfer function, system including the inter-processor communication device, and device driver for operating the inter-processor communication device - Google Patents

Abstract

PURPOSE: An inter-processor communication system capable of performing burst transfer, a system including the same, and a device driver for executing the same are provided to reduce the number of memories needed for the system by offering an exclusive storage region to each processor. CONSTITUTION: A first port(431) is connected to a first processor. A second port(432) is connected to a second processor. A share storage region(412) is selectively accessed by the first or second processor through the first or second port. The share storage region stores a plurality of data packets transferred between the first processor and the second processor. Mailbox regions(422,423) store a command and data transfer information for the data packets, which are transferred between the first processor and the second processor.

Description

INTER-PROCESSOR COMMUNICATION DEVICE HAVING BURST TRANSFER FUNCTION, SYSTEM INCLUDING THE INTER-PROCESSOR COMMUNICATION DEVICE, AND DEVICE DRIVER FOR OPERATING THE INTER-PROCESSOR COMMUNICATION DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inter-processor communication (IPC) technology, and more particularly, to a system including an interprocessor communication device capable of burst transmission, an interprocessor communication device, and a device for driving an interprocessor communication device. It's about the driver.

Inter-processor communication (IPC) requires a means for connecting data by connecting processors, and performing such a function is an interface. Typically, a serial interface such as a universal asynchronous receiver transmitter (UART), a serial peripheral interface (SPI), a universal serial bus (USB), or the like is used as an interface for the IPC.

Since the conventional serial interface converts parallel data into serial data, only one bit of data between processors is transmitted in one clock. Accordingly, the serial interface has a limitation of the data transfer rate. For example, an IPC using SPI has a data transfer rate of about 16 Mbps, an IPC using UART has a data transfer rate of about 1.5 Mbps, and a data transfer rate of about 5 Mbps even with an IPC using a high-speed UART. Have In addition, IPC using full-speed USB has a data transfer rate of up to 12 Mbps, and actually a data transfer rate of about 6 Mbps because of the high packet overhead required for the USB protocol.

In order to overcome the limitation of the data transfer rate of the system using the serial interface, a communication method using dual port random access memory (DPRAM) has been developed.

In a system utilizing DPRAM, each processor requires a separate dynamic random access memory (DRAM) for storing application data and a separate flash memory for storing application execution code. Accordingly, the size of the system utilizing the DPRAM is increased, and the data processing speed is deteriorated due to the memory access latency. In addition, due to the limitation of DPRAM capacity, there is a problem in that the data transfer rate is lowered when transferring large amounts of data between processors.

In order to solve the above problems, an object of the present invention is to provide an inter-processor communication apparatus that can improve the data transmission speed through burst transmission.

Another object of the present invention is to provide a system including the interprocessor communication apparatus.

It is still another object of the present invention to provide a device driver for driving the interprocessor communication apparatus.

In order to achieve the above object of the present invention, an interprocessor communication apparatus according to an embodiment of the present invention includes a first port, a second port, a shared storage area, and a mailbox area.

The first port is connected to a first processor and the second port is connected to a second processor. The shared storage area is selectively accessed by the first processor or the second processor through the first port or the second port, and stores a plurality of data packets transmitted between the first processor and the second processor. Save it. The mailbox area is connected to the first port and the second port, and stores a command transmitted between the first processor and the second processor and data transmission information for the plurality of data packets.

In one embodiment, the shared storage area may include a plurality of channels, and the plurality of data packets may be stored in any one of the plurality of channels. In one embodiment, the one channel in which the plurality of data packets are stored may include a plurality of buffers, and each of the plurality of buffers may store one of the plurality of data packets. In another embodiment, the one channel in which the plurality of data packets are stored includes a plurality of first buffers and a plurality of second buffers, wherein the plurality of first buffers are configured from the first processor to the second processor. A data packet of any one of a first plurality of data packets transmitted to the second plurality of buffers, wherein the plurality of second buffers of the second plurality of data packets transmitted from the second processor to the first processor Data packets can be stored.

In one embodiment, the mailbox area is a command storage area for storing the command, a channel index storage area for storing information about a location within the shared storage area of the plurality of data packets, and the plurality of data packets. It may include a packet number storage area for storing information about the number.

In one embodiment, the mailbox area is a first command sent from the first processor to the second processor and a first for first plurality of data packets sent from the first processor to the second processor. A first mailbox for storing data transmission information, a second command transmitted from the second processor to the first processor, and a second plurality of data packets transmitted from the second processor to the first processor; It may include a second mailbox for storing the second data transmission information.

In one embodiment, the command may be any one of a ownership request command, a release ownership command, a transfer pending command, a transfer resume command, a transfer complete command, or a transfer complete and ownership request command. The data transmission information may include an index of a channel in which the plurality of data packets are stored, and the number of the plurality of data packets.

In an embodiment, the interprocessor communication device may further include a semaphore area that stores information about ownership of the shared storage area. The interprocessor communication device further includes a first dedicated storage area accessed by the first processor through the first port, and a second dedicated storage area accessed by the second processor through the second port. It may include.

In one embodiment, the shared storage region includes a plurality of memory cells arranged in a matrix of rows and columns, each of the plurality of memory cells being a dynamic random access memory (DRAM) cell consisting of one access transistor and a storage capacitor. Can be.

In order to achieve the above object of the present invention, a system according to an embodiment of the present invention includes a first processor, a second processor and an interprocessor communication device.

The first processor executes a first application to perform a first task. The second processor executes a second application for performing a second task. The interprocessor communication device stores a plurality of data packets that are selectively accessed by the first processor or the second processor and are transmitted between the first processor and the second processor, and wherein the first processor and the first processor are stored. A command transmitted between two processors and data transmission information for the plurality of data packets are stored.

In one embodiment, each of the first processor and the second processor writes the plurality of data packets for each channel to the interprocessor communication device, and reads the plurality of data packets for each channel from the interprocessor communication device. The device driver may be further configured to write the command and the data transmission information into the interprocessor communication device and to read the command and the data transmission information from the interprocessor communication device.

In one embodiment, the device driver may be configured to write the plurality of data packets to the first application or the second application, to read the plurality of data packets, to write the command and the data transmission information, and An application programming interface (API) for reading the command and the data transmission information may be provided. The API may include: a data packet write function for writing the plurality of data packets to the interprocessor communication device; a data packet read function for reading the plurality of data packets from the interprocessor communication device; A message writing function for writing a command and the data transmission information, and a message reading function for reading the command and the data transmission information from the interprocessor communication device.

In an embodiment, the interprocessor communication device may include a first port connected to the first processor, a second port connected to the second processor, the first processor or the second port through the first port or the second port; A shared storage region selectively accessed by the second processor and storing the plurality of data packets for each channel, and connected to the first port and the second port and storing the command and the data transmission information It may include a box area. The shared storage area may include a plurality of channels, and the plurality of data packets may be stored in any one of the plurality of channels.

In an embodiment, the interprocessor communication device may include a first dedicated storage area that is accessed by the first processor through the first port and stores code and data of the first application, and the second port. The second processor may further include a second dedicated storage area that is accessed by the second processor and stores code and data of the second application.

In one embodiment, the interprocessor communication device may be a dynamic random access memory (DRAM).

In order to achieve the above object of the present invention, a device driver recorded on a computer-readable recording medium according to an embodiment of the present invention writes a plurality of data packets transmitted between processors in a shared storage area. A data packet writing function, a data packet reading function for reading the plurality of data packets from the shared storage area, a command transmitted between processors in a mailbox area, and writing data transmission information for the plurality of data packets A message writing function and a message reading function for reading the command and the data transmission information from the mailbox area are provided.

The interprocessor communication apparatus, system, and device driver according to the embodiments of the present invention as described above may improve the data transmission speed by supporting burst transmission between processors.

In addition, in embodiments of the present invention, the interprocessor communication apparatus, system, and device driver may provide a dedicated storage area for each processor, thereby reducing the number of memories required by the system and reducing the system size.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. .

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating a system according to an embodiment of the present invention.

Referring to FIG. 1, the system 100 includes a first processor 200, a second processor 300, and an interprocessor communication device 400. Although FIG. 1 illustrates a system 100 including two processors 200 and 300 respectively connected to an interprocessor communication device 400, those of ordinary skill in the art will appreciate interprocessor communication. It will be appreciated that three or more processors may be connected to the device 400.

The first processor 200 and the second processor 300 are respectively connected to the interprocessor communication device 400. The first processor 200 can access the interprocessor communication device 400 through the first port of the interprocessor communication device 400, and the second processor 300 is the second of the interprocessor communication device 400. The interprocessor communication device 400 may be accessed through the port. In one embodiment, the first processor 200 and the second processor 200 may be connected to the first port and the second port, respectively, via a bus. In another embodiment, the first processor 200 and the second processor 200 may be directly connected to the first port and the second port, respectively, through a plurality of signal lines without a separate arbitration device. For example, the first processor 200 and the first port may be connected through 16 or 32 data signal lines, and a plurality of address / control signal lines may be connected between the first processor 200 and the first port. Can be connected. According to an embodiment, the first processor 200 may be a modem processor, and the second processor 300 may be an application processor or a multimedia processor. According to an embodiment, the first processor 200 and the second processor 300 may be implemented as separate chips, respectively, and the first processor 200 and the second processor 300 may be implemented as one chip. have.

The interprocessor communication device 400 may transmit a shared storage area in which data packets transmitted between the first processor 200 and the second processor 300 are stored and between the first processor 200 and the second processor 300. It contains a mailbox area for storing messages. The shared storage area is selectively accessed by the first processor 200 or the second processor 300. For example, the second processor 300 may not access the shared storage area while the first processor 200 has ownership of the shared storage area. The mailbox area stores a first mailbox for storing a message transmitted from the first processor 200 to the second processor 300 and a message transmitted from the second processor 300 to the first processor 200. It may include a second mailbox for. When the first processor 200 writes a message in the first mailbox, the second processor 300 may receive the first interrupt signal INT1 to know that the message is written in the first mailbox. In addition, when the second processor 300 writes a message in the second mailbox, the first processor 200 may receive the second interrupt signal INT2 to know that the message is written in the second mailbox. .

For example, when data is transmitted from the first processor 200 to the second processor 300, the first processor 200 acquires ownership of the shared storage area through message transmission using the mailbox area. can do. The first processor 200 may write data packets to the shared storage area and write a data transfer command to the first mailbox to inform the second processor 300 that the data packets are written. In addition, the first processor 200 writes information, such as a location, number of packets, and the like, in which the written data packets are stored, together with the data transfer command, to the first mailbox, whereby the second processor 300 receives the data packets. The data packets may be read without further analysis. In addition, the first processor 200 transmits the data packets in parallel to the interprocessor communication device 400 through a plurality of signal lines connected to the first port, and the second processor 300 is connected to the second port. By receiving the data packets in parallel to the interprocessor communication device 400 through a plurality of signal lines, the data transmission speed between the first processor 200 and the second processor 300 is improved. In addition, the interprocessor communication device 400 writes a plurality of data packets to the shared storage area while the first processor 200 has ownership of the shared storage area, and the second processor 300 acquires the ownership. Support burst transfer that can read multiple data packets from the shared storage area while the device is in operation. Accordingly, the data transfer rate can be further improved by reducing the overhead of ownership exchange.

FIG. 2 is a block diagram illustrating an interprocessor communication device included in the system of FIG. 1.

Referring to FIG. 2, the interprocessor communication device 400a includes a first port 431, a second port 432, a first dedicated storage area 411, a second dedicated storage area 413 and 414, and shared storage. Region 412, semaphore region 421, and mailbox regions 422, 423.

The first port 431 is connected to the first processor 200 of FIG. 1, and the second port 432 is connected to the second processor 300 of FIG. 1. In addition, the first port 431 is connected to the first dedicated storage area 411 and the shared storage area 412 in the interprocessor communication device 400a, and the second port 432 is connected to the interprocessor communication device 400a. Are connected to the second dedicated storage area 413, 414 and the shared storage area 412. Accordingly, the first processor 200 of FIG. 1 may access the first dedicated storage area 411 and the shared storage area 412 through the first port 431 and the second processor 300 of FIG. 1. ) May access the second dedicated storage areas 413 and 414 and the shared storage area 412 through the second port 432.

The first dedicated storage area 411 is connected to the first processor 200 of FIG. 1 through the first port 431, and stores code and / or data of an application executed in the first processor 200 of FIG. 1. Can be stored. The second dedicated storage regions 413, 414 are connected to the second processor 300 of FIG. 1 through the second port 432 and / or code of a program executed in the second processor 300 of FIG. Data can be saved. Accordingly, the first dedicated storage area 411 for the first processor 200 of FIG. 1 replaces additional memory for storing code and / or data of a program executed by the first processor 200 of FIG. 1. In addition, second dedicated storage areas 413 and 414 for the second processor 300 of FIG. 1 may provide additional memory for storing code and / or data of a program executed by the second processor 300 of FIG. 1. By substituting, the number of memory devices required in the whole system can be reduced and power consumption can be reduced.

The shared storage area 412 is selectively connected to the first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 through the first port 431 or the second port 432. That is, only one processor having ownership of the shared storage area 412 among the first processor 200 or the second processor 300 of FIG. 1 may access the shared storage area 412. The shared storage area 412 may store a plurality of data packets transmitted between the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1. According to an embodiment, the shared storage area 412 may be divided into a plurality of channels, and each of the plurality of channels may be divided into a plurality of buffers. One data packet may be stored in each of the plurality of buffers. The shared storage area 412 is divided into a plurality of channels, and data packets are written to and read from each channel according to an application executed by the first processor 200 or the second processor 300 of FIG. 1. The first processor 200 of FIG. 1 or the second processor 300 of FIG. 1 may not perform a complicated process of analyzing a header of each of the data packets.

In one embodiment, the first dedicated storage area 411, the second dedicated storage area 413, 414, and the shared storage area 412 may each be one or more memory banks, and the interprocessor communication device 400a May be a dynamic random access memory (DRAM). For example, the first dedicated storage area 411 includes a first memory bank BANK A, and the second dedicated storage areas 413 and 414 include third and fourth memory banks BANK C and BANK D. ), And the shared storage area 412 may include a second memory bank BANK B, and each of the first to fourth memory banks BANK A, BANK B, BANK C, and BANK D may have a row. The memory cells may include a plurality of memory cells arranged in an over-column matrix, and each of the plurality of memory cells may be a dynamic random access memory cell including one access transistor and a storage capacitor. For example, each of the first to fourth memory banks BANK A, BANK B, BANK C, and BANK D may have memory capacities of 16MB, 64MB, 128MB, 256MB, and 512MB.

According to an embodiment, the interprocessor communication device 400a may access the shared storage area 412 in response to control signals received from the first processor 200 of FIG. 1 or the second processor 300 of FIG. 1. An access path forming unit may be selectively connected to the port 431 or the second port 432. In one embodiment, the access path forming unit is a path determining unit for logically combining the control signals to generate a path determination signal, applied through a first port 431 or a second port 432 in response to the path determination signal. Row and column address multiplexers which select one row and column address among the row and column addresses to be applied to the row decoder and the column decoder connected to the shared storage area 412, and the shared storage in response to the path determination signal. First and second global multiplexers selectively connecting the global input / output line pair in the region 412 to the first data input / output line pair or the second data input / output line pair, and the first and second global multiplexers and the first and second global multiplexers. The first and second input / output circuits may be disposed between the second ports 431 and 432, respectively.

The semaphore area 421 may store information about ownership of the shared storage area 412. In one embodiment, when the specific bit of semaphore area 421 is logic “1”, the first processor 200 of FIG. 1 has ownership of the shared storage area 412, and the specific bit of semaphore area 421 In the case of logic “0”, the second processor 300 of FIG. 1 may have ownership of the shared storage area 412. According to an embodiment, when the shared storage area 412 includes a plurality of banks, the semaphore area 421 may store a plurality of bits.

The mailbox areas 422 and 423 store messages transmitted between the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1. For example, a message transmitted between the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 may include a message about ownership of the shared storage area 412, a message about data transmission, and a shared storage area. It may be any one of the messages regarding the channel state of 412. In addition, when the transmitted message is a message about data transmission, the transmitted message is a data transmission information indicating a command indicating that the transmitted message is a message about data transmission and information on currently transmitted data packets. It may include. In one embodiment, the mailbox areas 422 and 423 include a first mailbox 422 and a diagram for storing messages sent from the first processor 200 of FIG. 1 to the second processor 300 of FIG. It may include a second mailbox 423 for storing a message transmitted from the second processor 300 of the first to the first processor 200 of FIG. When the message is written to the first mailbox 422, the first interrupt signal INT1 is transmitted to the second processor 300 of FIG. 1, and when the message is written to the second mailbox 423, The second interrupt signal INT2 is transmitted to the first processor 200. When the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 receive the first interrupt signal INT1 and the second interrupt signal INT2, respectively, the first processor 200 and FIG. The second processor 300 of FIG. 1 reads messages stored in the first mailbox 422 and the second mailbox 423, respectively.

According to an embodiment, the semaphore region 421 and the mailbox regions 422, 423 may be implemented as internal registers of the interprocessor communication device 400a. In one embodiment, semaphore region 421 and mailbox regions 422 and 423 may each be implemented as separate registers. In another embodiment, the semaphore area 421 and the mailbox area 422, 423 may be implemented with one register. In one embodiment, the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1 are the semaphore area 421 and the mailbox area 422 in a manner similar to that of accessing the shared storage area 412. , 423). For example, a row address corresponding to any row of the shared storage area 412 may be assigned to the semaphore area 421 and the mailbox area 422, 423. That is, when a specific address, for example, an address between 1FFF800h and 1FFFFFFh is applied, the semaphore area 421 and the mailbox areas 422 and 423 may be enabled instead of the row of the shared storage area 412. According to an embodiment, the interprocessor communication device 400a further includes a register access circuit for preventing access of the memory cells corresponding to the specific address and enabling the semaphore area 421 and the mailbox areas 422 and 423. It may include.

For example, when data is transmitted from the first processor 200 of FIG. 1 to the second processor 300 of FIG. 1, the first processor 200 of FIG. 1 utilizes the mailbox areas 422 and 423. Ownership of the shared storage area 412 can be obtained by sending a message. The first processor 200 of FIG. 1 writes data packets to a channel of the shared storage area 412 and writes the data transfer command and the data transfer information to the first mailbox 422, thereby providing the first processor of FIG. The processor 300 may read the data packets based on the data transmission command and the data transmission information without further analyzing the data packets. In addition, data transmission speed between processors may be improved through burst transmission that may minimize ownership exchange between the first processor 200 of FIG. 1 and the second processor 300 of FIG. 1.

3 is a block diagram illustrating a shared storage area included in the interprocessor communication device of FIG. 2.

Referring to FIG. 3, the shared storage area 412a includes a plurality of channels CH1, CH2, and CHN. Each of the plurality of channels CH1, CH2, and CHN includes first buffers TX_BUF1, TX_BUF2, TX_BUF2, TX_BUFN and second buffers RX_BUF1, RX_BUF2, RX_BUF2, and RX_BUFN. The number of first buffers TX_BUF1, TX_BUF2, TX_BUF2, TX_BUFN and the number of second buffers RX_BUF1, RX_BUF2, RX_BUF2, and RX_BUFN included in each of the plurality of channels CH1, CH2, and CHN are embodiments. The size of each of the first buffers TX_BUF1, TX_BUF2, TX_BUF2, TX_BUFN and the second buffers RX_BUF1, RX_BUF2, RX_BUF2, and RX_BUFN may also vary. The number and size of the plurality of channels CH1, CH2, and CHN may also vary in some embodiments.

A plurality of data packets are stored in each of the plurality of channels CH1, CH2, and CHN. According to an embodiment, a channel in which a plurality of data packets transmitted or received by the application may be determined according to an application executed in the first processor 200 of FIG. 1 or the second processor 300 of FIG. 1. That is, since a location where a plurality of data packets are stored is determined, the processor for transmitting the plurality of data packets does not need to add a header such as a location stored in each data packet, a designation of a receiving application, and the like. The processor for receiving the plurality of data packets does not need to analyze each data packet to confirm a designated application. Accordingly, the process for interprocessor communication can be simply implemented.

In one embodiment, each of the plurality of channels CH1, CH2, CHN includes first buffers for storing data packets transmitted from the first processor 200 of FIG. 1 to the second processor 300 of FIG. TX_BUF1, TX_BUF2, TX_BUF2, TX_BUFN) and second buffers RX_BUF1, RX_BUF2, RX_BUF2, and RX_BUFN, which store data packets transmitted from the second processor 300 of FIG. 1 to the first processor 200 of FIG. It may include. That is, since the location where the plurality of data packets are stored is determined according to the transmission direction, an algorithm for processing for inter-processor communication can be more simply implemented. According to an embodiment, the sizes of the first buffers TX_BUF1, TX_BUF2, TX_BUF2, TX_BUFN and the second buffers RX_BUF1, RX_BUF2, RX_BUF2, RX_BUFN may be fixed, and the maximum size of each data packet may be It may be less than or equal to the size. By fixing the size of each buffer, each processor can easily grasp the address of the buffer in which any packet is stored. For example, the maximum size of a packet may be 2 KB, and the size of the buffer may also be 2 KB. According to an embodiment, each packet may include a header of a fixed size in which the entire valid packet or the size of the valid data is stored and a data area in which the valid data is stored.

4 is a block diagram illustrating a mailbox included in the interprocessor communication device of FIG. 2.

Referring to FIG. 4, the mailbox 422a includes a command storage area 441, a channel index storage area 442, and a packet number storage area 443. For example, the mail box 422a of FIG. 4 is the first mailbox 422 of FIG. 2 in which a message transmitted from the first processor 200 of FIG. 1 to the second processor 300 of FIG. 1 is stored. Can be.

The command storage area 441 is an area in which a command indicating a type of message is stored. Depending on the type of message, the message may include only the command and may include the command and additional information. For example, the command stored in the command storage area 441 may be any one command among the commands shown in Table 1 below.

For example, as shown in Table 1, the command storage area 441 includes an ownership request command, an ownership release command, a transfer pending command, a transfer resume command, a transfer complete command, a channel status command, a transfer complete and ownership request command, and a request. Cancel commands, error commands, and the like may be stored. The ownership request command is a command for requesting ownership of a shared storage area by another processor, the release command is a command indicating that the ownership is released in response to the ownership request command, and the transfer pending command is data. A data packet of a predetermined level or more is stored in a data queue of a processor receiving the packets, and the processor requesting the suspension of the data transmission to the processor transmitting the data packets, and the resume transmission command stops the data transmission stopped in response to the suspension transmission command. Command to request resumption, the transfer completion command is a command indicating that the processor has completed writing data packets to be transmitted to the shared storage area, and a channel status command indicates a status of each channel of the shared storage area. The transfer completion and ownership request commands are commands for requesting to release ownership of the shared storage area after reading the written data packets together with completion of writing the data packets, and the cancel request command cancels the transmitted command. Command, and an error command is a command for informing that an error has occurred during interprocessor communication. Although nine commands are described in Table 1, those skilled in the art will understand that other commands may be used in addition to the above commands, or some of the commands may be used. In one embodiment, the command storage area 441 may have a capacity of 8 bits.

The message transmitted between the processors may further include additional information according to the type of message, that is, the command. For example, in the case of a message including the transmission completion command, the message may include an index of a channel in which data packets are written and / or the number of data packets together with the transmission completion command.

The channel index storage area 442 may store an index of a channel included in the shared storage area. For example, when a first processor sends a plurality of data packets to a second processor, the first processor writes the plurality of data packets to a specific channel of the shared storage area, and the first processor stores a command. The transfer completion command may be written in an area 441, and an index for the specific channel in which the plurality of data packets are written may be written in a channel index storage area 442. The second processor may know a location, that is, addresses, in which the plurality of data packets are stored, based on an index for the specific channel. Further, in one embodiment, when the channels of the shared storage area are associated with an application running on the second processor, the device driver for the interprocessor communication device running on the second processor reads the plurality of data packets. After that, no separate analysis can be done to specify the associated application. In an embodiment, the index for one channel may be stored in the channel index storage area 442. In another embodiment, each bit of the channel index storage area 442 may be associated with a corresponding channel and indicate whether a plurality of data packets are stored in the corresponding channel according to the value of each bit.

The packet number storage area 443 may store the number of data packets written in the channel. For example, when the first processor transmits a plurality of data packets to the second processor, the first processor writes the plurality of data packets in a specific channel of the shared storage area, and the command storage area 441. ), The transmission completion command may be written, the index for the specific channel may be written in the channel index storage area 442, and the number of the plurality of data packets may be written in the packet number storage area 443. The second processor may not perform a process of extracting headers of each of the plurality of data packets to analyze an associated application, the number of packets, and the like. Accordingly, the process for interprocessor communication can be simply implemented.

5 is a flowchart illustrating a method of acquiring ownership of a shared storage area included in the interprocessor communication device of FIG. 2 in the system of FIG. 1.

1, 2, and 5, the first processor 200 reads information about ownership of the shared storage area 412 stored in the semaphore area 421, thereby obtaining ownership of the shared storage area 412. You can see which processor you have. When the second processor 300 has ownership of the shared storage area 412, the first processor 200 writes a ownership request command to the first mailbox 422 (step S511). When the ownership request command is written to the first mailbox 422, the interprocessor communication device 400 or 400a generates a first interrupt signal INT1 indicating that the message has been written to the first mailbox 422. When the second processor 300 receives the first interrupt signal INT1 (step S513), the second processor 300 reads the ownership request command from the first mailbox 422 (step S515).

The second processor 300, which is requested to transfer ownership from the first processor 200, writes an ownership release command to the second mailbox 423 in response to the ownership request command (step S517). In addition, the second mailbox 423 may access the semaphore area 421 and change information about ownership stored in the semaphore area 421. According to an embodiment, when the second processor 300 needs to continuously access the shared storage area 412, the second processor 300 writes a non-release command to the second mailbox 423 or The first processor 200 writes a request cancel command to the first mailbox 422 after waiting a predetermined time, or the first processor 200 requests a ownership command to the first mailbox 422 without transmitting a message. Can be rewritten. When the ownership release command is written to the second mailbox 423, the interprocessor communication device 400 or 400a generates a second interrupt signal INT2 indicating that the message has been written to the second mailbox 423. When the first processor 200 receives the second interrupt signal INT2 (step S519), the first processor 200 reads the ownership release command from the second mailbox 423 (step S521). Accordingly, the first processor 200 may transfer ownership of the shared storage area 412 from the second processor 300.

6 is a flowchart illustrating a method for transmitting data between processors in the system of FIG. 1.

1 through 4 and 6, the first processor 200 may identify a processor having ownership of the shared storage area 412 through the semaphore area 421. If the second processor 300 has ownership of the shared storage area 412, the first processor 200 acquires the ownership through the method shown in FIG. 5 (S610). When the first processor 200 acquires the ownership, that is, the access right to the shared storage area 412, the first processor 200 writes data packets to the shared storage area 412 (S620). In an embodiment, the first processor 200 writes the data packets to buffers of one channel, for example, first buffers TX_BUF1, TX_BUF2, TX_BUF3, TX_BUFN of the first channel CH1. One data packet may be written in each of the first buffers TX_BUF1, TX_BUF2, TX_BUF3, and TX_BUFN. After the first processor 200 writes the data packets to the shared storage area 412, the first processor 200 indicates that there is data to be transmitted to the first mailboxes 422 and 422a, that is, data transmission. The command and data transfer information are written (step S630). That is, the first processor 200 writes a data transfer command in the command storage area 441, writes an index of the channel in which the data packets are written in the channel index storage area 442, and stores the packet number storage area 443. ) The number of data packets. When the data transfer command and the data transfer information are written to the first mailboxes 422 and 422a, the interprocessor communication apparatus 400 or 400a generates a first interrupt signal INT1.

When the second processor 300 receives the first interrupt signal INT1 from the interprocessor communication device 400 or 400a, the second processor 300 may transmit the data transfer command from the first mailboxes 422 and 422a. The data transmission information is read (step S640). That is, the second processor 300 reads the data transfer command from the command storage area 441, reads the index of the channel in which the data packets are written from the channel index storage area 442, and stores the packet count storage area ( The number of data packets is read from 443. Based on the index of the channel and the number of data packets, the second processor 300 reads the data packets from the shared storage area 412 (step S650). Accordingly, the second processor 300 receives the information on the plurality of data packets through a message transmitted through the first mailboxes 422 and 422a, so that the second processor 300 separates the plurality of data packets. The plurality of data packets may be provided to a designated application without processing.

7 is a block diagram illustrating modules executed in a processor included in the system of FIG. 1.

Referring to FIG. 7, the first processor 200a executes the device driver 210, the IPC driver 220, and the application 230. In one embodiment, device driver 210 and IPC driver 220 may be registered with kernel 240 as a kernel driver. In one embodiment, device driver 210 and IPC driver 220 may each be implemented as separate kernel drivers. In another embodiment, the device driver 210 and the IPC driver 220 may be implemented as one kernel driver.

The application 230 executed in the first processor 200a may be an application requiring data communication with an application executed in the second processor 200 of FIG. 1. For example, the application 230 may be a program that provides a modem function for demodulating data and providing the application to the application executed in the second processor 200 of FIG. 1.

The IPC driver 220 may perform a function of connecting the application 230 and the device driver 210. For example, the application 230 may call a function of the IPC driver 220 directly or through the kernel 240, and the IPC driver 220 may call a function of the device driver 210. According to an embodiment, the first processor 200a may execute only the application 230 and the device driver 210 without the IPC driver 220, and the application 230 may directly call a function of the device driver 210 or may execute a kernel. Call through 240. In addition, the IPC driver 220 may manage the data packet queue through an internal thread.

The device driver 210 provides an application programming interface (API) to the IPC driver 220 or the application 230, and controls the interprocessor communication device 400 of FIG. 1. According to an embodiment, the device driver 210 may be implemented as a library. For example, the device driver 210 may provide an API as shown in Table 2 below to the IPC driver 220 or the application 230.

As described in Table 2, the device driver 210 may provide message transfer related functions, data transfer related functions, and other functions to the IPC driver 220 or the application 230. For example, the device driver 210 may have a message write function, a message read function, a data packet write function, a data packet read function, an initialization function, a ownership check function, an error check function, a channel address search function, and the like. The message writing function is a function of writing a message to the first mailbox 422 of FIG. 2, and the message reading function is a function of reading a message from the second mailbox 423 of FIG. 2, and the data packet. The write function is a function that writes one or more data packets to the shared storage area 412, and the data packet read function is a function that reads one or more data packets from the shared storage area 412, and the initialization function is a device driver. 210 is a function for initializing the ownership verification function, which accesses the semaphore area 421 of FIG. 2 and checks which processor has ownership of the shared storage area 412. Is a function of returning an error of the device driver 210 generated in a code or a message, the channel address search function is para Is a function that returns the address of the channel that provides teoro. The IPC driver 220 or the application 230 may access the interprocessor communication device 400 of FIG. 1 through the above API of the device driver 210.

Hereinafter, single data transmission and burst data transmission will be described with reference to FIGS. 2, 8, and 9 through the API provided by the device drivers 210a and 310a.

8 is a flowchart illustrating a single mode data transmission method in the system of FIG. 1.

2 and 8, the first processor 200a executes the first device driver 210a and the first IPC driver 220a. In one embodiment, the first processor 200a may further execute the application 230 of FIG. 7 that calls the first IPC driver 220a. In another embodiment, the application 230 of FIG. 7 may be executed instead of the first IPC driver 220a. In addition, the second processor 300a executes the second device driver 310a and the second IPC driver 320a. In one embodiment, the second processor 300a may further execute the application 230 of FIG. 7 calling the second IPC driver 320a. In another embodiment, the application 330 of FIG. 7 may be executed instead of the second IPC driver 320a.

In order for the first processor 200a to acquire ownership of the shared storage area 412 in the single mode, the first IPC driver 220a may provide an ownership request command as a parameter to write a message of the first device driver 210a. Call the function The first device driver 210a writes the ownership request command to the first mailbox 422 in response to the call. The interprocessor communication device 400a generates a first interrupt signal and transmits the first interrupt signal to the second processor 300a. In an embodiment, the kernel of the second processor 300a may call the interrupt handler of the second IPC driver 320a by receiving the first interrupt signal. Accordingly, the second IPC driver 320a may know that a message is written in the first mailbox 422, and the second IPC driver 320a calls a message read function of the second device driver 310a. . The second device driver 310a reads the ownership request command from the first mailbox 422 in response to the call. The second device driver 310a calls the message writing function of the second device driver 310a by providing the ownership release command as a parameter in response to the ownership request command. The second device driver 310a writes the ownership release command to the second mailbox 423 in response to the call. The interprocessor communication device 400a generates a second interrupt signal and transmits the second interrupt signal to the first processor 200a. In an embodiment, the kernel of the first processor 200a may call the interrupt handler of the first IPC driver 220a by receiving the second interrupt signal. Accordingly, the first IPC driver 220a may know that a message is written in the second mailbox 423, and the first IPC driver 220a calls the message read function of the first device driver 210a. . The first device driver 210a reads the ownership release command from the second mailbox 423 in response to the call. The first device driver 210a may provide a read ownership release command to the first IPC driver 220a so that the first IPC driver 220a may know that ownership of the shared storage area 412 is obtained.

When there is a first data packet and a second data packet to be transmitted from the first processor 200a to the second processor 300a, the first IPC driver 220a of the acquired first processor 200a transmits data. For example, a data packet write function of the first device driver 210a may be called by providing a pointer to the first data packet or the first data packet together with a channel identifier, for example, a channel index or a channel handle. . The first device driver 210a writes the first data packet to a channel in the shared storage area 412 corresponding to the channel identifier in response to the call. After the writing of the first data packet is completed, the first IPC driver 220a calls a message writing function of the first device driver 210a by providing a transmission completion command and a channel index as parameters. The first device driver 210a writes the transfer completion command and the channel index into the first mailbox 422 in response to the call. The second IPC driver 320a calls a message reading function of the second device driver 310a, and the second device driver 310a receives the transmission completion command and the channel index in response to the call. 422). The second device driver 310a reads the data packet of the second device driver 310a by providing the channel index as a parameter to read the first data packet stored in the channel corresponding to the channel index in the transfer completion command. Call the function The second device driver 310a reads the first data packet stored in the channel of the shared storage area 412 in response to the call. Accordingly, the first data packet of the first processor 200a is transmitted to the second processor 300a.

In addition, the first processor 200a regains ownership of the shared storage area 412 and transmits the second data packet in the manner described above. Thus, in single mode, each time one data packet is sent from one processor to another, communication for exchange of ownership is required. The system according to an embodiment of the present invention supports data transmission in burst mode in addition to data transmission in single mode.

9 is a flowchart illustrating a data transmission method in burst mode in the system of FIG. 1.

2 and 9, the first processor 200a executes the first device driver 210a and the first IPC driver 220a. In one embodiment, the first processor 200a may further execute the application 230 of FIG. 7 that calls the first IPC driver 220a. In another embodiment, the application 230 of FIG. 7 may be executed instead of the first IPC driver 220a. In addition, the second processor 300a executes the second device driver 310a and the second IPC driver 320a. In one embodiment, the second processor 300a may further execute the application 230 of FIG. 7 calling the second IPC driver 320a. In another embodiment, the application 330 of FIG. 7 may be executed instead of the second IPC driver 320a.

When there are a plurality of data packets to be transmitted from the first processor 200a to the second processor 300a, for example, the first data packet and the second data packet, the first processor 200a is in the single mode of FIG. 8. Take ownership of the shared storage area 412 in a manner similar to taking ownership of. The first IPC driver 220a of the acquiring first processor 200a acquires the first and second data packets or the first together with a channel identifier, for example a channel index or channel handle, for data transmission. And a data packet write function of the first device driver 210a by calling the second data packets and the number of packets as parameters. The first device driver 210a writes the first and second data packets to the channel of the shared storage area 412 corresponding to the channel identifier in response to the call. After the writing of the first and second data packets is completed, the first IPC driver 220a calls the message writing function of the first device driver 210a by providing the transmission completion command, the channel index, and the number of packets as parameters. . The first device driver 210a writes the transfer completion command, the channel index, and the number of channels in the first mailbox 422 in response to the call.

The second IPC driver 320a calls the message read function of the second device driver 310a, and the second device driver 310a resets the transmission completion command, the channel index, and the number of packets in response to the call. 1 Read out from the mailbox 422. The second device driver 310a provides the channel index and the number of packets as parameters to read the first and second data packets stored in the channel corresponding to the channel index in the transfer completion command, thereby providing a second device driver. Call the data packet read function of 310a. The second device driver 310a reads the first and second data packets stored in the channel of the shared storage area 412 in response to the call. Accordingly, the first and second data packets of the first processor 200a are transmitted to the second processor 300a.

As such, in burst mode, a plurality of data packets may be transmitted from one processor to another at a time through communication for one ownership exchange. Accordingly, such a burst transmission can transmit a large amount of data without the overhead of ownership exchange, and the data transmission speed of the system can be improved.

10 is a block diagram illustrating a system according to an embodiment of the present invention.

Referring to FIG. 10, the system 900 includes a first processor 910, a second processor 920, an interprocessor communication device 930, an antenna 940, a flash memory 950, and a liquid crystal display 960. , Speaker 970, input device 980, and bus 990. In one embodiment, system 900 may be a portable device. For example, the system 900 may be a personal digital assistant (PDA), a portable multimedia player (PMP), a mobile phone, a smartphone, a mobile TV, navigation, a portable game machine, or the like. .

The first processor 910 and the second processor 920 are connected to the interprocessor communication device 930, respectively. 10 illustrates a system 900 including two processors 910 and 920 respectively coupled to an interprocessor communication device 930, those of ordinary skill in the art will appreciate It will be appreciated that three or more processors may be connected to the device 930.

In one embodiment, the first processor 200 demodulates the communication signal received from the antenna 940 and provides it to the second processor 920, and modulates the data received from the second processor 920 to antenna 940. It may be a processor that performs a modem function provided to the outside through). In addition, the second processor may be an application processor or a multimedia processor that executes applications that provide an internet browser, a 3D map, a game, a video, and the like. The interprocessor communication device 930 may include a shared storage area for data transmission between the first processor 910 and the second processor 920, and a first code and data of a program executed in the first processor 910. It may include a dedicated storage area, a second dedicated storage area in which code and data of a program executed in the second processor 920 are stored. In one embodiment, the interprocessor communication device 930 may be dynamic random access memory (DRAM). In some embodiments, each of the first processor 910, the second processor 920, and the interprocessor communication device 930 may be implemented as a separate chip or may be implemented as a single chip.

In one embodiment, the first processor 910 may not be connected to a separate storage device other than the interprocessor communication device 930. That is, codes and data of a program executed in the first processor 910 may be stored in the first dedicated storage area of the interprocessor communication device 930. For example, the code of a program executed in the first processor 910 may be transferred from the flash memory 950 or the file system (not shown) connected to the second processor 920 through the second processor 920 at system boot. It may be stored in the first dedicated storage area. In this case, the second processor 920 may access the first dedicated storage area during system booting, and may not access the first dedicated storage area after booting is completed. As such, since the system 900 does not include a separate storage device for the first processor 910, the size of the system 900 may be reduced.

The second processor 920 may be connected to the flash memory 950. The flash memory 950 may store boot codes of the second processor 920 or boot codes of the first processor 910 and the second processor 920. The application code and / or data of the second processor 920 may be stored in the second dedicated storage area of the interprocessor communication device 930. Accordingly, the system 900 may not include a separate DRAM for storing the application data of the second processor 920, so that the size of the system 900 may be further reduced.

In addition, the second processor 920 may be connected to the liquid crystal display 960, the speaker 970, and the input device 980 through the bus 990. The second processor 920 is based on the communication data received through the first processor 910 and the interprocessor communication device 930 and / or the input data provided from the input device 980 and the liquid crystal display device 930. Image data and / or audio data may be provided to the speaker 970.

As such, the system 900 according to an embodiment of the present invention may include an interprocessor communication device 930 having a dedicated storage area and a shared storage area, thereby reducing the size of the entire system and reducing power consumption. . In addition, the interprocessor communication device 930 may efficiently transmit data by transmitting data through the shared storage area and transmitting a message through a mailbox. In addition, the interprocessor communication device 930 may support burst transmission to further improve the data transmission speed.

As described above, the interprocessor communication apparatus, system, and device driver according to embodiments of the present invention transmit data packets for each channel through a shared storage area including channels, and include data transmission information through a mailbox. By sending a message, data transmission can be performed efficiently. In addition, the interprocessor communication apparatus, system, and device driver according to embodiments of the present invention may further improve data transmission speed by supporting burst transfer to reduce the overhead of ownership exchange.

The present invention can be usefully used in any system including a plurality of processors. In particular, the present invention is more useful for portable devices such as personal digital assistants (PDAs), portable multimedia players (PMPs), mobile phones, smart phones, mobile TVs, navigation, portable game machines, and the like. Can be used.

While the invention has been described above with reference to preferred embodiments, those skilled in the art will be able to make various modifications and changes to the invention without departing from the spirit and scope of the invention as set forth in the claims below. I will understand.

1 is a block diagram illustrating a system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an interprocessor communication device included in the system of FIG. 1.

3 is a block diagram illustrating a shared storage area included in the interprocessor communication device of FIG. 2.

4 is a block diagram illustrating a mailbox included in the interprocessor communication device of FIG. 2.

5 is a flowchart illustrating a method of acquiring ownership of a shared storage area included in the interprocessor communication device of FIG. 2 in the system of FIG. 1.

6 is a flowchart illustrating a method for transmitting data between processors in the system of FIG. 1.

7 is a block diagram illustrating modules executed in a processor included in the system of FIG. 1.

8 is a flowchart illustrating a single mode data transmission method in the system of FIG. 1.

9 is a flowchart illustrating a data transmission method in burst mode in the system of FIG. 1.

10 is a block diagram illustrating a system according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 900: system

200, 200a, 300, 300a, 910, 920: processor

400, 400a, 930: interprocessor communication device

412, 412a: shared storage

Claims (20)

A first port coupled to the first processor; A second port coupled to a second processor; Shared storage area for storing a plurality of data packets selectively accessed by the first processor or the second processor through the first port or the second port, and transmitted between the first processor and the second processor ; And An interprocessor connected to the first port and the second port and including a mailbox area for storing a command transmitted between the first processor and the second processor and data transmission information for the plurality of data packets Communication device. The method of claim 1, The shared storage area includes a plurality of channels, And wherein the plurality of data packets are stored in any one of the plurality of channels. The method of claim 2, The one channel in which the plurality of data packets are stored comprises a plurality of buffers, And each of the plurality of buffers stores one data packet of the plurality of data packets. The method of claim 2, The one channel in which the plurality of data packets are stored comprises a plurality of first buffers and a plurality of second buffers, The plurality of first buffers store a data packet of any one of a first plurality of data packets transmitted from the first processor to the second processor, And the plurality of second buffers store one of the second plurality of data packets transmitted from the second processor to the first processor. The method of claim 1, wherein the mailbox area, A command storage area for storing the command; A channel index storage area for storing information about a location in the shared storage area of the plurality of data packets; And And a packet number storage area for storing information on the number of the plurality of data packets. The method of claim 1, wherein the mailbox area, A first mailbox for storing first data transmission information for the first command transmitted from the first processor to the second processor and the first plurality of data packets transmitted from the first processor to the second processor; And A second mailbox for storing second data transmission information for a second command transmitted from the second processor to the first processor and for a second plurality of data packets transmitted from the second processor to the first processor; Interprocessor communication device comprising a. The method of claim 1, wherein the command is: An ownership request command, a release ownership command, a transfer hold command, a transfer resume command, a transfer complete command, or a transfer complete and ownership request command. The method of claim 1, wherein the data transmission information, An index of a channel in which the plurality of data packets are stored; And And a number of the plurality of data packets. The method of claim 1, And a semaphore area for storing information about ownership of the shared storage area. The method of claim 9, A first dedicated storage area accessed by the first processor through the first port; And And a second dedicated storage area accessed by the second processor through the second port. The method of claim 1, The shared storage area includes a plurality of memory cells arranged in a matrix of rows and columns, And each of the plurality of memory cells is a dynamic random access memory (DRAM) cell consisting of one access transistor and a storage capacitor. A first processor executing a first application to perform a first task; A second processor executing a second application to perform a second task; And Is selectively accessed by the first processor or the second processor, stores a plurality of data packets transmitted between the first processor and the second processor, and is transmitted between the first processor and the second processor. And an interprocessor communication device for storing a command and data transmission information for the plurality of data packets. The processor of claim 12, wherein each of the first processor and the second processor includes: Write the plurality of data packets for each channel to the interprocessor communication device, read the plurality of data packets for each channel from the interprocessor communication device, write the command and the data transmission information to the interprocessor communication device, and And a device driver for reading the command and the data transmission information from the interprocessor communication device. The device driver of claim 13, wherein the device driver comprises: Writing processing of the plurality of data packets to the first application or the second application, reading processing of the plurality of data packets, writing processing of the command and the data transmission information, and reading processing of the command and the data transmission information. System for providing an application programming interface (API) for. The method of claim 14, wherein the API, A data packet write function that writes the plurality of data packets to the interprocessor communication device; A data packet read function that reads the plurality of data packets from the interprocessor communication device; A message writing function for writing the command and the data transmission information to the interprocessor communication device; And And a message read function for reading the command and the data transfer information from the interprocessor communication device. The apparatus of claim 12, wherein the interprocessor communication device comprises: A first port coupled to the first processor; A second port coupled to the second processor; A shared storage area selectively accessed by the first processor or the second processor through the first port or the second port, and storing the plurality of data packets for each channel; And And a mailbox area coupled to the first port and the second port, the mailbox area storing the command and the data transmission information. The method of claim 16, The shared storage area includes a plurality of channels, And the plurality of data packets are stored in any one of the plurality of channels. The apparatus of claim 17, wherein the interprocessor communication device comprises: A first dedicated storage area accessed by the first processor through the first port and storing code and data of the first application; And And a second dedicated storage area accessed by the second processor through the second port and storing code and data of the second application. The method of claim 12, And said interprocessor communication device is dynamic random access memory (DRAM). A data packet write function for writing a plurality of data packets transmitted between processors in a shared storage area; A data packet read function for reading the plurality of data packets from the shared storage area; A message writing function for writing a command transmitted between processors and data transmission information for the plurality of data packets in a mailbox area; And And a device driver for providing a message reading function for reading the command and the data transmission information from the mailbox area.

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