SU1377865A1 - Device for interfacing computer with external devices - Google Patents

Abstract

The invention relates to computing and can be used for interfacing microcomputers with peripheral devices in automatic control systems, in data acquisition, processing and transmission systems. The aim of the invention is to increase the speed by reducing the number of cycles of the computer to the device. The device comprises a transceiver, a receiver of control signals, an identifier register, an address selector, a decoder, a receiver, a delay element transmitter, a data register. 4 il.

Description

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The invention relates to computing technology and can be used for interfacing microcomputers with peripheral devices in automatic control systems, in data acquisition, processing and transmission systems,.

The aim of the invention is to increase the speed due to the reduction in the number of computer cycles to the device.

FIG. 1 shows a functional diagram of a device for interfacing a computer with external devices in FIG. 2 is a schematic diagram of the address selector; in fig. 3 and 4 are the diagrams of the device operation during the Output and Input cycles, respectively.

the foreign address, the decoder 18 does not generate a signal. Resolution and the decoder 4 does not generate the signals of Input 1 and Output .1, therefore the information in registers 5 and 6 is not recorded,

In Output mode, the computer 11 accesses this device, exposes

its address on the DAOO-DA15 bus and signal exchange (see Fig. 3). The address is stored in register 17, and the decoder 18, recognizing its address, sets the Resolution signal; this is where the address part of the computer cycle ends. Then the computer sets the information on the DAOO-DA15 bus and the output signal on the corresponding line. Signal Presence Authorization at the entrance

The device contains a transceiver; 20 Ritor 4 ensures the formation

tick 1, receiver 2 control signals. neither, the address selector 3, the decoder 4 data register 5, the identifier register 6, the delay element 7, the receiver 8j transmitter 9, the computer trunk 10 connected to the computer 11 and containing the bus Data-address (ДАОО-ДА15) and control signal lines: Exchange, Input, Output; and Answer, as well as the trunk 12 of external devices containing the data input bus 13 and the data output bus 14 to which external devices (IU) 15 are connected,

The address selector contains (figure 2) the element NOT 16, the register 17 and the decoder 18,

The device operates in three modes: in the passive mode in the Output mode, when the device provides information transfer from the computer 11 to one of the slaves 15; in the Input mode, when the device provides information transfer from WU 15 to the computer 11.

To ensure interaction with the computer, the device has an address in the addressing field of the computer.

In the passive mode, the device does not transmit information either from the computer or from the slave, which happens if the computer does not access the slave connected to this device. In this mode, transceiver 1 provides information from the trunk 10 to the inputs of the selector 3 and registers 5 and 6. On the signal Exchange - the register 17 of the selector 3 stores the information set out on the DAOO-DA15 bus, but since this information is

0

signal output 1. On the signal edge, the Output 1 information set at the input of the register 5 is recorded into it and in the form of data DOO-D07 through

5, the transmitter 9 is transmitted to the bus 17 of the highway 12 and is fed to the slave unit 15. The information installed on the DA08-DA15 lines is written to the register 6 on the front of the signal Youq 2, delayed relative to the signal Output 1 by the element 7. From the output of the register 6 Data D08-D15 through the transmitter 9 is transmitted to the bus 14 of the highway 12 and is fed to the inputs of the slave. In addition, on the signal front

 The output of the decoder 4 generates a signal Answer and sends it to the highway 10, the computer notified from the beginning of the reception of information. Having received the Response signal, the computer removes the output signal, which ensures the reset of the signal. The exchange and resetting of registers 5 and 6. This completes the first cycle of the reference of the computer with the DD. Having received the information, first on the DOO-D07 lines, and this way on the D08-D 15 lines, each slave unit analyzes the data of the D08-D15 and understands that the data of the DOO-DO7 is the address of the slave with which the computer establishes the communication for the exchange, The SP recognizes its hell; res is prepared for exchange with a computer. Thus, the first cycle of the reference of the computer is the address part of the work cycle of the slave. In the second cycle, the Output device works in the same way as in the first one, while the word-identifier contained in bits D08-D15 indicates that, first, in the DOO-D07 bits, the set0

five

five

data, and, secondly, how this data should be used. The selected TDU accepts the Data and executes the instructions contained in D08-D15. At this cycle, the work of WU to receive data from the computer ends. Thus, in Output mode, two cycles of a computer are required to exchange information with the slave unit.

In the Input mode, the computer also performs two cycles of accessing the device.

In the first cycle, the computer transfers the address to the CU as described above. When transmitting, the addresses of the VU in the data D08-D15, besides indicating that the address of the VU is transmitted, it is also specified that the VU set the data on the bus 13 of the highway 12. Performing the instructions of the computer, the VU sets the data on the bus 13 to the time equal to the computer cycle.

In the second cycle, the computer accesses the data installed on bus 13. For this (Fig. 4), the computer sets the address of the device on the DAOO-DA15 bus and the Exchange signal. Having recognized its address, the address selector 3 sets the Resolution signal, which unlocks the decoder 4. Then the computer sets the Input signal, which from the corresponding output of the decoder 4 as the Input 1 signal goes to the control input of the transceiver 1, opens its input, and installed on bus 13, through receiver 8 and with transceiver 1 transmitted to trunk 10. When a signal arrives, the input of the decoder 4 generates a Response signal that informs the computer that data is installed on highway 10, the computer enters data and removes Entering drove that provides reset signals Exchange, Input 1 and response. This completes the cycle of information transfer from the slave to the computer.

Claims (1)

Invention Formula A device for interfacing a computer with external devices, comprising a transceiver, a receiver of control signals, a receiver, a transmitter, an address selector, a descrambler, the group of information inputs-outputs 0 five 0 five 0 five 0 five 0 five The transceiver forms a group of input-output devices for connecting to a group of information input-outputs of a computer, the first, second, third information inputs of the control signal receiver and the first output of the decoder are inputs and outputs of the device for connecting respectively the exchange, input, and output outputs the response of the computer, groups of information inputs of the receiver and outputs of the transmitter form groups of inputs and outputs of the device for connecting respectively to groups of information outputs and inputs of external devices, the group of information outputs of the receiver is connected to the group of information inputs of the transceiver, the group of information outputs of which is connected to the group of information inputs of the address selector, the gate of which is connected to the first information output of the control signal receiver, the second and third information outputs of which are connected to the first and BTopbw the information inputs of the descrambler, the resolution input and the first Kotoporo code are connected respectively to the output of the address selector and to the control The input of the transceiver is characterized by the fact that, in order to increase speed, a data register, an identifier register, and a delay element are entered into it, while the group of information inputs of the data register is connected to the lower bits of the group of information outputs of the transceiver, the highest bits of the group of information outputs of which connected to a group of information inputs of the register of identifiers, the installation input of which is connected to the first information output of the receiver of control signals and to the installation m input of the data register, the entry of which is connected to the second output of the decoder and to the input of the delay element, the output of which is connected to the input of the record of the identifier register, the group of information outputs of the data register and the identifier register  katorov connected to the group of information inputs of the transmitter. Offfffff 1b LMO LM € Resolution