SU1456964A1 - Device for interfacing processor with input/output system - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer systems for processing and preparing data. for matching I / O device interfaces and a processor having a different set of signals. and an information exchange protocol. The aim of the invention is to expand the class of mating devices by increasing the length of the generated sequences of control signals and increasing the noise immunity when operating in the polling mode. The device contains a command transceiver terminal, a command decoder, a synchronization node, considered interrupt formations, a feedback code processing node, an instruction register, input and output information registers, and input and output control registers. 2 hp f-ly, 7 ill. R.

Description

The invention relates to computer technology and can be used in computer systems for processing and preparing data for matching I / O device interfaces and a processor having a different set of signals and an information exchange protocol.

The purpose of the invention is to expand the class of mating devices by increasing the length of the generated control signal sequences M and increasing the noise immunity when operating in the polling mode.

Figure 1 shows the structural diagram of the device; figure 2 is a functional diagram of the decryptor commands; FIG. 3 is a functional diagram of a chap formation unit; Fig. 4 is a functional diagram of the input control register; Fig. 5 is a functional diagram of the output control register; figure 6 is a functional diagram of the synchronization node; Fig. 7 is a functional diagram of the feedback code processing unit.

The device for interfacing the processor with input-output devices (Fig. 1) contains a decoder of I commands, a transceiver node 2, an interrupt generation node 3, an output 4 and an input 5 information registers, an input 6 and an output 7 control registers, an instruction register 8, the synchronization node 9 and the feedback code processing node 10. Figure 1

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Also indicated are the bidirectional data interface 11 of the processor interface, the internal bidirectional data device bus 12, the inputs and outputs 13-66 of the device and its nodes.

The decoder 1 command is designed to identify the addresses of the input ports and ports of the device in the processor commands and generate the appropriate control signals for the internal nodes of the device. De i encoder i contains (FIG. 2) a permanent memory 67 for decoding the addresses of input ports and a permanent memory 68 for decoding the addresses of the output ports.

Transceiver unit 2 is designed to match the bi-directional data bus 11 of the processor interface with the internal bi-directional bus 12 of the device data. Node 2 consists of bi-directional bus drivers (PF), the choice of which is determined by the signal at the input A1 of the node generated when 14 processor accesses the ports of the device, and the direction of transmission depends on the signal level at the input of Input 13 of the processor interface.

Interrupt shaping node 3 is designed for: masking interrupt requests arriving at inputs 48 and 27 and switching them to interrupt output 28 for the processor interface. Node 3 (fig.Z) contains the register 69 of the mask, a group of elements And 70 and a group of elements OR 71

The output information register 4 is intended for recording information transmitted via the internal bus 12 dann and transmitting it to output 30 to the interface of the input-output device.

The input information register 5 is designed to capture information from input 32 from the interface of an I / O device and transmit it to the internal data bus 1 of the device when there is a read signal at input 54. Register 5 is a register that has outputs with three states nor mi. In the absence of a read signal at input 54, information from input 32 is permanently entered into register 5, but is not translated into bus 12 of the device. When a read signal appears at input 54, entering information into register 5

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stops and it is broadcast on bus 12.

The input control register 6 is designed to capture the control signals from the input-output device to input 33, and to transmit them to the device data bus 12 in the presence of a readout signal at input 55; at output 26 of the feedback code of the node. Register 6 contains (figure 4) trigger 72 and the tire driver 73.

The output control register 7 15 is designed to fix information post-test on the data bus 12 and the group of inputs 62f to transmit it to output 31 to the interface of the input / output device when there is a read signal 20 or input 59. Register 7 contains (FIG. 5) the triggers 74 and 75 and the tire driver 76.

Register 8 of the instruction is intended for fixing a combination of signals on 25 inputs 37 and 39 from the processor interface in the form of an instruction code determining the choice of the generated sequence of control signals.

The synchronization node 9 is intended to organize the operation of the registers 6 and 7 and the node 10 in the process of generating sequences of feedback control signals, as well as to block synchronization signals when the processor accesses the input and output ports of the device. Node 9 contains (6) pulse generator 77, the trigger 78 and the element 79 of the delay.

The feedback code processing node 10 is designed to generate feedback output control signal sequences at output 24, request signals for interrupt 45 3 output 46, and set signal to initial state of the register at output 23, depending on the instruction code at input 44 and sequences of input feedback control signals at input 49. Node 10 contains (FIG. 7) a persistent memory 80 and a register 81.

The device works as follows.

The device is reset by resetting the processor interface to the input. Reset device 29 and resetting the trigger.

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75 of the register 7, at the same time the output of the input-output device is generated at the output 31, which in response stops the formation of control signals to the input 33 transmitted through the output group 26 of the register 6 to the input of the feedback code of the node 10, which, in its the queue stops the generation of control signals on the group of outputs 24 and at the same time generates at output 23 a setup pulse to the initial state of register 8.

When addressed from the processor side, the device is a series of independently addressable input ports and output ports. In the information output commands to the device port, information from the processor interface data 11 is transmitted via node 2 to the data bus 12 and written either to register 4 or simultaneously to register 69 of node 3 and trigger 75.register 7. In commands to enter information from the device port information either from the outputs of the register 5, or simultaneously from the outputs of the bus driver 73 of the register 6 and bus driver 76 of the register 7 goes to the data bus 12 and is transmitted through the node 2 to the data bus 1 of the processor interface.

Before starting the exchange of information, depending on the I / O device being connected, the processor configures node 3 and register 7 by entering information into the configuration port, while the trigger 75 of register 7 is recorded unchanged during the exchange of control signals at the output 31 of the input device interface - output, and the register 69 of the mask of node 3 is written down the code that controls the selection as interrupt signals, arriving at the output 28 to the processor interface, the control signals at the input 33 from the interface of the input-in device output, transmitted through register 6, and interrupt request signals from the output 46 of node 10, generated in the process of information exchange. In comparison with the known process, the initial setup of the proposed device is significantly reduced or can be eliminated altogether (depending on the interface of the I / O device), since information about

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the control signals are stored in the permanent memory .80 of node 10.

When implementing the output of the information word to the I / O device, the processor outputs the information word to the output port of the device, the information is entered into register 4 and transmitted to output 30 to the I / O device, and the port address at input 15 of the address and the logical value of the input signal. Output 14 from the processor interface is written to register 8 as an instruction code, which through output 22 goes to the corresponding input group of node 10, at output 24 of which a combination is formed (a sequence of ) control signals transmitted via trigger 74 of register 7 to output 31 to the input-output device interface. The formation of a sequence of control signal combinations is ensured by the presence in node 10 of a register 81. The I / O device, having received the necessary control signals at output 31, enters information from output 30 and generates input confirmation signals at input 33, which through output 26 of register 6 are transmitted to the input of the feedback code of the node 10 and cause the formation of a response combination (sequence of combinations) at the output 24 of the node 10 and, accordingly, at the output 31 to the interface of the input device. Simultaneously outputs 23 and 46 of the assembly 10 are formed register set pulse 8 to its initial state and request signal prergoanie signaling processor on completion schenii output word information input device-vshoda. The processor, either having received a signal of interruption at the output 28 of interruptions of the device (operating mode by interruption), or by interrogating the device status port (polling mode), reads the contents of trigger 72 of register 6 and triggers 74 and 75 of register 7.

When implementing the input, the information words from the I / O device later forms the word gg of information at the input 32, and at the input 33 a combination of control signals that is transmitted through the output 26 of the register 6 to the inputs of the nodes 10 and 3. At the same time, the output node 3 to process30 interface

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A coping signal is generated, and at the output 24 of node 10, a combination of control signals is transmitted through register 7 to output 31 to the interface of the output device, which informs the input device of the occupation. The processor receiving the interrupt signal (the operation mode of the invention

1. A device for interfacing a processor with input-output devices, i containing a command decoder, a transceiver node, a crimp formation node, a feedback code processing node, an output and an input AI

by querying m), or by polling the port of the Formation registers, the output and

device status (polling mode), makes a call. to the Bzod port of the device, wherein the information at input 32 is fixed in register 5 and transmitted to the data bank 11 of the processor. At the same time, the port address at the input 15 of the address and the logical value of the signal at the output of the processor Interface 14 are fixed in register 8 as an instruction code. In this case, a combination of control signals (a sequence of combinations) is generated from the output 24 of node 10 through output 3 in the interface of the I / O device, informing the I / O device that the processor has entered information words. Upon completion of the input of information at the output 23 of the node 10, a pulse of setting the register 8 to the initial state is formed.

Addressing the processor to the configuration port and the device status port does not change the state of the register 8 and does not affect the operation of the node 10 in the process of entering information output. In the process of accessing the processor to the device ports by node 9, the clock signal at output 25 is blocked, and the state of registers 6 and 7 and node 10 is not changed even if the call occurs during the formation of a sequence of control signals, thus avoiding distortion information transferred between the processor, the device and the I / O device.

If in the process of information exchange a violation of the generated sequence of control signals occurs or the input device generates a combination of control signals of the exchange end at the output 28 of node 3 into the processor interface, an interrupt signal is formed with a different priority level than the normal signals generated during normal operation. device operation.

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input control registers, and the group of information inputs-in the transceiver node moves to form a device-input-output group for connecting to the group of information input-output of the processor, first, second permitting inputs and group of information inputs of the decrypted command form the inputs of the device to output Output, Output and a group of processor output outputs, a group of outputs of interrupt-forming nodes forms output signals, devices for connecting

25 nor to the group of inputs of the interrupt of the processor, the group of information outputs of the output information register and information inputs of the input information register,

30 groups of outputs and inputs of the device for connection respectively to. groups of information inputs and outputs of input / output devices, groups of information outputs of the output control register and information inputs of the input control register form groups of outputs and inputs of the device, for connecting responsibly to groups of control

Q inputs and outputs of the I / O device, with the second group of information inputs / outputs of the node of the electrical transmission connected to the group of information inputs of the output info

45 mation register, with a group of information outputs of the input information register, with the first group of information outputs of the input control register, with the first group of information inputs of the junction formation node, with a group of information inputs and outputs of the output control register, a group of information which inputs soy

gg of dinene with the first group of information outputs of the feedback code processing node, the second group of information outputs of which is connected by the second group of information inputs

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input control registers, where the group of information inputs / outputs of the transceiver node forms the device I / O group for connecting to the group of information I / O of the processor, the first, second permitting inputs and the group of information inputs of the command decoder form the device inputs for connecting respectively to the outputs of Output, In the output and the address group of the processor address, the output group of the interrupt-forming node forms a group; Pu outputs, devices for connecting to a group of interrupt inputs of the processor, groups of information outputs of the output information register and information inputs of the input information register,

groups of outputs and inputs of the device for connection respectively to. groups of information inputs and outputs of input / output devices, groups of information outputs of the output control register and information inputs of the input control register form groups of outputs and inputs of the device, to be connected, respectively, to groups of control

inputs and outputs of the input / output device, while the second group of information inputs / outputs of the transceiver node is connected to the group of information inputs of the output information register, with the group of information outputs of the input information register, with the first group of information outputs of the input control register, with the first group of information inputs node of formation of distortions, with a group of information inputs-outputs of the output control register, the group of information inputs of which is connected to ne your group of information outputs of the feedback code processing node, the second group of information outputs of which is connected to the second group of information inputs

the group of the formation of faults, the first group of information inputs of the node processing the feedback code is connected to the second group of information outputs of the input control register, the first input of the command decoder is connected to the input of the output information register, the second output of the command decoder is connected to the inputs of the node record generation of interrupts and output control register, characterized in that, in order to expand the class of matching devices by increasing the length of the generated sequences control signals and increase noise immunity when operating in the polling mode, a synchronization node and an instruction register are entered into it, the information input and a group of information inputs of the register of the instruction are connected respectively to the second enabling input and the group of information inputs of the command decoder, the transmission direction input of the transceiver node is connected to the first enable input of the command decoder, the setup input of the output control register is the device input for connecting to the Reset output processor, the third group of information inputs of the interrupt shaping node is connected to the second group of information outputs of the input carbon register, the group of information outputs of the instruction register is connected to the second group of information inputs of the feedback code processing node, the installation output of which is connected to the installation input of the register of instructions, the write input of which is connected to the third output of the instruction decoder, the fourth output of which is connected to the reading input of the input information register Stra, fifth, command decoder output coupled to inputs of a read input and output control registers, the sixth decoder output commands

connected to the enable input of the transceiver node and to the trigger input of the synchronization output node of which is connected to the synchronous inputs of the feedback code processing node of the input and output control registers.

2, The device according to claim 1, which is tlicking in that the feedback code processing node contains a fixed memory and a register, with the first and second groups of address inputs of the fixed memory form, respectively, the first and second groups of information inputs of the node The first rpynrffe information outputs of the permanent memory and the first group of information outputs of the register form the first and second groups of information outputs of the node, respectively, the synchronous input and the information output of the register are respectively the synchronous input and the set output home node, wherein the node handling code feedback second group of information outputs of the register connected to the third group of address inputs of the ROM, a second group of information outputs of which is connected with the group of information inputs of register.

 3. The device according to claim 1, about tl and - the fact that the node interrupt formation contains re

the mask mask, the group of elements AND, the group of elements OR, the group of information inputs of the mask register form the first group of information inputs of the node, the first and second inputs of elements AND of the group form the second and third groups of information inputs of the node, respectively; the synchronous input of the mask register is the input of the node recording, the outputs of the elements OR groups form a group of outputs of the node, while in the node form-. interrupt ki group of outputs register-. The mask is connected to the third inputs of the AND elements of the group, the outputs of which are connected to the inputs of the elements of the OR group.

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Claims (3)

Claim 1 О is connected to the enabling input of the transceiver unit and to the start input of the synchronization unit ^ whose sync output is connected to the synchro inputs of the node · · -5 processing the feedback code of the input and output control registers. 1. A device for interfacing a processor with input-output devices, ι containing an instruction decoder, a transceiver unit, an interrupt generation unit, a feedback code processing unit, output and input information registers, output and input control registers, and a group of information input-output nodes the transceiver forms a group of inputs and outputs of the device ed to connect to the group of information inputs and outputs of the processor, the first, second enable inputs and the group of information inputs of the command decoder image cosiness device inputs for 2Q connection respectively to outputs Input ¹¹ , Output and output group of the processor address, the group of outputs of the interrupt generation unit forms a group of outputs, devices for connecting to a group of processor interrupt inputs, a group of information outputs of the output information register and information inputs of the input information register form. 30 groups of outputs and inputs of the device for connecting respectively to. groups of information inputs and outputs of input-output devices, groups of information outputs of the output __ control register and information of other inputs of the input control register form groups of outputs and inputs of the device. to connect respectively to groups of control ₄ 0 inputs and outputs of the input-output device, while the second group of information the inputs and outputs of the transceiver node is connected to the group of information inputs of the output information register45, with the group of information outputs of the input information of the register, with the first group of information outputs input control ¹ registers, the first grup5Q sing information inputs formation unit interrupts a group of information inputs-outputs of the output control register, a group of information inputs of which soe55 dinena the first group of processing feedback code node information outputs, the second group of information outputs of which is connected to the second group of information inputs of the interrupt generation unit, the first group of information inputs of the processing unit and the feedback is connected to the second group of information outputs of the input control register, the first output of the command decoder is connected to the write input of the output information register, the second output of the command decoder is connected to the record inputs of the interrupt generation unit and the output control register, characterized in that, in order to expand the class of paired devices by increasing the length of the generated sequences of control signals and increasing noise immunity when working in the polling mode, The synchronization node and the instruction register are provided, the information input and the group of information inputs of the instruction register are connected respectively to the second enable input and the group of information inputs of the command decoder, the transmission direction input of the transceiver unit is connected to the first enable input of the command decoder, the setting input of the output control register is the input devices for connecting to the output Reset the processor, while the third group of information inputs of the interrupt generation unit is connected and with the second group of information outputs of the input engraving register, the group of information outputs of the instruction register is connected to the second group of information inputs of the feedback code processing unit, the installation output of which is connected to the installation input of the instruction register, the input of which is connected to the third output of the command decoder, the fourth output which is connected to the reading input of the input information register, the fifth, the output of the command decoder is connected to the reading inputs of the input and output control p Trunk, the sixth decoder output commands 2. The device according to claim 1, wherein the feedback processing unit of the feedback code contains read-only memory and a register, the first and second groups of address inputs of read-only memory forming, respectively, the first and second groups of 15 information inputs of the node, the first rpynrffe of information outputs of read-only memory and the first group of information outputs of a register form the first and second 2o groups of information outputs of a node, respectively, the clock input and information output of a register are respectively a sync input and set to stroke node, wherein the node ki obrabot25 feedback code register a second group of information outputs connected to address inputs of the third group of permanent memory, a second group of information outputs koto30 swarm is connected to a group of information inputs of register. \ 3. The device according to claim 1, wherein the interrupt generation unit contains a re ₃₅ mask mask, a group of AND elements, a group of OR elements, and the group of information inputs of the mask register forms the first group of information inputs of the node, the first and second The first inputs of the elements AND groups form the second and third groups of information inputs of the node, respectively, the input of the mask register is the input of the node record, the outputs of the elements OR ₅ groups form the group of outputs of the node, and the node is formally. interruptions, the group of outputs of the mask register is connected to the third inputs of AND elements of the group, the outputs of which 50 are connected to the inputs of OR elements of the group. FIG. J FIG. 6 FIG. 7