SU1365089A1 - Device for interfacing two computers with common external device - Google Patents

Abstract

The invention relates to plumbing technology and can be used to create multi-machine systems based on microcomputers with shared memory and common external input-output devices. The purpose of the invention is to expand the range of connected external devices. The device contains six groups of channel transceivers, three channel transceivers, a pulse generator, a counter, a decoder, two registers and addresses, a multiplexer, two priority triggers, four control triggers, three OR elements, seven I. 6 ill., 1 tab. o (l

Description

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The invention relates to the field of computer technology and can be used to create multi-machine systems on microcomputers with shared memory and common external input-output devices.

The aim of the invention is to expand the functionality of the device by expanding the range of connectable common external devices.

 FIG. 1-3 shows a functional diagram of the device; in fig. 4-6 are the timing diagrams of the device operation when the computer accesses the shared memory, when it requests interruption, and provides direct access.

The device contains (Fig. 1-3) the first 1, second 2, third 3 groups of information inputs-outputs of the device, first A, second 5, third 6 groups of control inputs-outputs of the device, first 7, second 8, third 9 channel groups transceivers, first 10 and second 11 address registers, multiplexer 12, fourth 13, fifth 14, sixth 15 groups of channel transceivers.

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9 and 15 - to transfer mode. From the direct and inverse outputs of the pulse generator 38, the C-inputs of the flip-flops 41 and 42 receive different polarity pulses, which are used to interrogate the presence of calls received from the first and second computers. Computer circulation can be of three types:

memory access (or external device register);

interrupt handling

handling when granting direct access.

When there is access from one or at the same time from two computers to a common memory area, one of the priority triggers (41 or 42) is installed, which controls the connection of the channel of the first (group 1, 4 input-output) or second (group 2, 5 input- outputs) computer to the common channel (groups 3, 6 inputs-outputs).

When the software is accessed by the computer to 25 memory (or the external device register) located in the common area, the device operates as follows.

The exchange cycle begins with the receipt.

20

elements ШШ 16-20, elements И 21-37, with a heel, for example, from the first computer, the signal generator 38 pulses, the counter 39, the decoder 40, the first 41, the second 42 priority triggers, the control triggers 43-46, the AND-OR elements 47- 49, first 50, second 51, third 52 channel transceivers, bus 53 Reset.

The device is connected to the channels of two small computers (of type Electronics-60) as follows.

Group 1 of information I / O and 4 control I / O of the device is connected to the computer channel. Groups 2 of information I / O and 5 control I / O of the device are connected to the channel of the second computer. Groups of 3 information I / O and 6 control I / O devices form a third (common) channel for connecting a common memory and common external devices.

The device works as follows.

By the reset signal 53, the triggers 41-46, the counter 39 are set to the zero state. The channel transceiver groups 7, 8, 13, 14 are set to receive mode, and the groups

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9 and 15 - to transfer mode. From the direct and inverse outputs of the pulse generator 38, the C-inputs of the flip-flops 41 and 42 receive different polarity pulses, which are used to interrogate the presence of calls received from the first and second computers. Computer circulation can be of three types:

memory access (or external device register);

interrupt handling

handling when granting direct access.

When there is access from one or at the same time from two computers to a common memory area, one of the priority triggers (41 or 42) is installed, which controls the connection of the channel of the first (group 1, 4 input-output) or second (group 2, 5 input- outputs) computer to the common channel (groups 3, 6 inputs-outputs).

When the software is accessed by a computer to 5 memory (or the external device register) located in the common area, the device operates as follows.

The exchange cycle begins with the receipt5

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synchronization of the K1 SIL address to the input of the first group of 4 control inputs-outputs of the device. Since the transceiver group 13 operates in the receive mode, the signal K1 SIL via the transceiver of group 13, the elements OR 16 and I 1 will go to the information input of the trigger 41, which with the positive differential from the generator 38 pulses will be set to one what will mean the priority setting for the first computer. In this case, a low level signal from the zero output of the trigger 41 will be prohibited from setting And 1 to 1 to the trigger 42 via the element 22, if the second computer turns to the common memory area at this time. Moreover, with the simultaneous access of two computers to the common Ps1m region, that trigger (41 and 42) of priority will be set to the active state, to which a positive differential from the 38 pulse generator will arrive. When the synchronization signal of the K1 SIL address is detected, the first computer installed the information inputs-outputs 1 of the device, the address is stored in the address register 10, with

the outputs of the register 10 address through the multiplexer 12 (on the control inputs of which the code 00 is set), through a group of 9 channel transceivers, the address code is fed to the information inputs-outputs 3 of the device. After the flip-flop 41 is turned on, the active level of the signal is removed from the zero inputs of the counter 39, the flip-flops 43-46, and a sequence of four clock pulses is generated at the output of the decoder 40, and the triggers 43-46 are successively switched on (in the input cycle) and 35 (in the output loop), as well as a group of channel transceivers 15, the control signals of the short-circuit power, short-start and short-circuit (in the output loop) for the third channel are formed. According to the first clock pulse (from the decoder 40), the short-circuit signal of the SIL is generated; its leading edge signals the presence of an address code at the information inputs-outputs 3 of the device.

The second clock pulse includes a trigger 44, the signal from which switches multiplexer 12 to select the first group of inputs (or the second if priority is set for the second computer), and data from the computer channel are transmitted to the information inputs-outputs 3 of the device. In addition, on the second clock pulse, a short-enter signal is generated if an input cycle is performed, and the signals ENTER and ENTER 1 (elements OR 19 and AND 30) are used to switch the group of channel transceivers 9 to receive, and group 7 to transmit, and data is transferred from the common (third) channel to the first. On the third clock pulse, a fault signal is generated (if an output cycle is performed), channel transceivers of groups 7 and 9 remain in the same state: group 7 in reception, group 9 in transmission. Data comes from the first to the common (third) channel.

From the memory device or external device connected to the common (third) channel, after recognizing the address, in response to the SC INPUT signal (or CZ OUTPUT), a MIL CC signal is received, which passes through the channel transceiver 50 (in receiving mode) to the inputs channel transceivers

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51 and 52. At the output of the channel transceiver 51, a signal K1 SIP is generated, having received the first computer that ends the exchange cycle, removes the signals K1 ENTER (or K1 OUTPUT) and K1 SIL, which leads to the removal of the signals KZ ENTER (or KV RT) ) and KZ SIL in general (third) canapés; In addition, when the K1 SIL signal is removed, the trigger 41 is set to the zero state, thereby allowing the installation of the trigger 42, and hence the exchange of the second computer with the common (third) channel. An example of a time diagram of the operation of the device during the exchange of the first computer (in input mode) and the second computer (in output mode) with the common channel is shown in FIG. four.

The operation of the device during the operation occurs as follows.

When a demand is received from the common channel, the demand for the first computer of the KZ TPR1 computer to the channel of the first computer on the bus K1 TPD is set to the active level. By providing an interrupt, from the channel of the first computer to the device, the first group of control inputs and outputs receives the signal K1 SPR, which, like the signal K1 SIL when programmed, sets the priority trigger 41 to one state (i.e., sets the priority for the first computer). Thereafter, a sequence of clock pulses is formed on the decoder 40. On the second clock pulse of the decoder 40, the short-circuit signals ENTER (ENTER) and ENTER 1 are formed, by which the group of channel transceivers 9 is switched to reception from the common channel, and group 7 is sent to the first channel. On the fourth clock pulse on the element AND 29 (if the second computer is interrupted - on the element 32), a short-circuit signal SH1R1 is formed, through which the address of the interrupt vector, followed by the short-circuit fault signal, is transmitted from the common channel (from the external device interface) through the groups of information inputs outputs 3 and 1 to the channel of the first computer. After the first computer takes the address of the vector, signals K1 ENTER, K1 SPR are removed in the first channel, which entails the device clearing the signals of the CIN ENTER, KZ SPR1 and KZ CIP signals, while the trigger 41 is set to the zero state. Job device30

35

40

50

55

The second computer with interruptions occurs in the same way. FIG. 5 shows a timing diagram of the operation of the device when the first computer is interrupted.

The operation of the device in direct memory access cycles is as follows.

When a first computer accesses the memory of the first computer KZ TPD1 (when accessing the second computer sets the signal TPZ2 CD) on the bus K1 TPD sets the active level. Having provided direct access, the first computer sends the signal K1 DPT, which arrives at the input of the element OR 16. If the second computer does not access the common channel (or as soon as the cycle has ended), the trigger 41 through the positive NOW signal difference from the generator 39 is set, and the output of the element 28 enters the common channel cash fault PPD. In response, from the interface of the external device, a KZ PV signal is generated to the common channel, which, through element 23, holds trigger A1 in the on state, disables the decoder 40, switches the channel transceivers of groups 9 and 1 to receive, groups 7 and 13 - to transmission, the channel of the first computer from the output of element 25 receives a signal K1 PV, confirming the capture of the active interface of women. Having received the signal K1 PV, the first computer removes the signal K1 SPD, which entails the removal of the signal KZ KZ1D1 from the output of the element 28.

After installation of the short-circuit alarm signal, the external device interface performs a cycle (or cycles) of accessing the memory (to a common memory for both computers, or to its own computer). At the beginning, the information buses of the common channel (group of information I / O 3) are used to determine the memory address, which through the channel transceiver groups 9 and 7 enters the first channel. Receiving the KZ signal SIL from the common channel, using the channel transceiver groups 15 and 13, the device generates the K1 CHA signal for the first channel. On the leading fronts of the short-circuit signals of the SIL and K1 SIL from the information buses, the address code is read both in common and in the first channels by memory devices.

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If the external device performs an input cycle, then by the INPUT signal, the channel transceivers of group 9 are switched to transmit, and group 7 are sent to receive (by the control signal CW PW ENTER from the output of element 27) and the first channel transmits the signal K1 ENTER. If the data is read from a memory device located in the common channel, then the data on the common data busses are transmitted from the memory to the external device, accompanied by a CI CIP signal, via the SC IN signal. If the data is read from a memory device located in the first channel, then the data from the information. The first channel channels through channel transceivers of groups 7 and 9 are transmitted to the common channel and are accompanied by a CIP signal K1, which is also transmitted to the common channel through channel transceivers 51 and 50 and the OR element 20.

Having received the CIP CIP signal, the external device reads the data from the information bus, removes the signals of the CG INPUT, CZ SNA, CZ PW signals and the exchange cycle ends. In case the external device performs a data output cycle in the memory, the channel transceivers of group 9 are switched to receive, and groups 1 are sent to the transmission and by a fault signal OUTPUT (K1 OUTPUT 5 in the first channel) information is recorded in the memory device located in the first, or in the general channel. The exchange peak also ends after the occurrence of a CIP CIP signal. The exchange in the direct access mode with the channel of the second computer is carried out in a similar way. The time diagram of the operation of the device in the exchange mode during direct access to the memory of the first

 The computer is shown in FIG. 6

The table lists the tire names and abbreviations of the signals.

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Claims (1)

Invention Formula A device for interfacing two computers with a common external device, containing six groups of channel transceivers, two address registers, a multiplexer, two priority triggers, a decoder, two AND elements, the informational inputs-outputs channel transceivers of the first, second, third groups form device input-output groups for connecting the first computer, second computer and common external device to the information input-output groups, respectively; first, second, third information inputs-outputs of the fourth, fifth, sixth channel transceivers The groups are inputs to the device outputs for connecting to the inputs-outputs of address synchronization, input, output, respectively, the first computer, the second computer, the common external device, the outputs of the first, second electronic And are the outputs of the device for connecting respectively to the first, second inputs of direct access to the common external device, while the group of outputs of the multiplexer is connected to the information inputs of the channel transceivers third five ten g 3650898 the first computer is connected to the first input of the fourth element AND, and is the device input for connecting to the output providing the second computer interrupt, the outputs of the third and fourth elements AND are the device outputs for connecting respectively to the first and second input inputs interrupt the common external device, the second input of the first element OR is connected to the first input of the first element AND, and is the input of the device for connecting to the output providing direct the access of the first computer, the second input of the second element OR is connected to the first input of the second element AND, and is the device input for connecting to the output providing direct access of the second computer, the output of the fifth element AND is connected to the first input of the sixth element AND, 20 groups, information outputs of which 25 control inputs of the first channel are connected to information inputs of channel transceivers of the first, second groups, information outputs of which are connected respectively to groups of information inputs of the first, second address registers and the first, second groups of information inputs of a multiplexer, third and fourth groups of information whose inputs are connected to groups of outputs, respectively, of the first, second address registers, the synchronous inputs of which are connected to the first information The primary outputs of the channel transceivers of the fourth and fifth groups, respectively, the first, second and third information inputs of which are connected respectively to the first, second, third information outputs of the channel transceivers of the sixth group, characterized in that, in order to expand the functionality by expanding the range of connected common external devices, a pulse generator, a counter, a control trigger trigger, three channel transceivers, three AND-OR elements, five elec cops OR, n fifteen elements AND, and the first 30 35 40 45 50 transceiver with the control input of the channel transceivers of the fourth group and is the output of the device for connecting the input confirmation of the channel selection of the first computer to the input, the output of the seventh And element is connected to the first input of the eighth And element, with the first controlling input of the second channel transceiver with a control input channel transceivers of the fifth group and is the output of the device for connecting to the input of the channel selection confirmation of the second computer, the information inputs-outputs of the first, second, third The digital transceivers are the device inputs-outputs for connecting the passive device to the synchronization inputs-outputs of the first computer, the second computer, the common external device, the control input of the channel transceivers of the sixth group, and the first gate of the decoder, first The inputs of the fifth, seventh, ninth, tenth, eleventh And elements, with the control input of the third channel transceiver, with the first The first input of the OR element is the connecting input of the channel is acceptable to the first input of the third AND element and is the device input for connecting to the output provided by five 0 five 0 transceiver with the control input of the channel transceivers of the fourth group and is the output of the device for connecting to the input of the channel selection confirmation of the first computer, the output of the seventh element I is connected to the first input of the eighth element I, with the first controlling input of the second channel transceiver, with the control the input of the channel transceivers of the fifth group is the output of the device for connecting the second computer to the input of the channel selection confirmation, the information inputs-outputs of the first, second, third to The digital transceivers are the device inputs-outputs for connecting the passive device to the synchronization inputs-outputs of the first computer, the second computer, the common external device, the control input of the channel transceivers of the sixth group, and the first gate of the decoder, first The inputs of the fifth, seventh, ninth, tenth, eleventh And elements, with the control input of the third channel transceiver, with the first transmitters of the third group and is the device input for connecting to the output of the selection confirmation 913 the common external device channel, the first, second inputs and the output of the first AND-OR element are the inputs and the output of the device for connecting respectively to the outputs of the byte command feature of the first, second computer and the input of the byte command of the common external device, zero the input of the first priority trigger element And, the output of which is connected a dinene with zero input of the second priority trigger and is a setup input of the device, with the first output of the pulse generator connected to the second gate input 15 of the element And, the first input of which the decoder and the synchronous input of the second priority trigger, the unit output of which is connected to the first control input of the multiplexer, to the third input of the first AND-OR element, to the second input of the seventh element AND, p. the second control input of the second channel transceiver, with the second inputs of the second and fourth And elements, with the first input of the third OR element, with the first inputs of the second, third AND-OR elements and the thirteenth element And with the second input of the | From that element And, the output which is connected to the single input of the second priority trigger, the information input of which is connected to the output of the twelfth element I, the first input of which is connected to the zero output of the first priority trigger, the sync input of which is connected to the second a pulse generator with a counting input of the counter, the setup input of which is connected to the zero inputs of the first, second, third, fourth control triggers and the output of the third OR element, the second input of which is connected to the fourth input of the first AND-OR element, with the second inputs first, third, p of the elements And, with the second control. the first channel transceiver, with the second inputs of the second, third AND-OR elements, the first input of the fourteenth AND element, the single output of the first priority trigger, and the second input of the nine AND element whose output is connected to the single input of the first priority trigger, information the input of which is connected to the output of the fifteenth element I, the first input of which is connected to the zero output of the second priority trigger. 20 25 thirty connected to the output of the third element AND-OR, the third input of which is connected to the second information output of the channel transceivers of the fourth group, the third information output of which is connected to the second input of the fourteenth element And whose output is connected to the first control input of the channel transceivers of the first group and to the first input the fourth OR element, the output of which is connected to the second inputs of the sixth, eighth, eleventh elecCements AND, to the first control input of the channel transceivers of the third group and the third information input channel transceivers of the sixth group, the second input of the fourth element OR is connected to the first control input of the channel transceiver, the sensors of the second group and the output of the thirteenth element I, the second input of which is connected to the second information output of the channel receiving 0 transmitters of the fifth group, the first information output of which is connected to the fourth input of the second AND-OR element and to the third input of the second the OR element, the output of which is connected to the second input of the twelfth AND element, the third information output of the channel transceivers of the fifth group is connected to the fourth input of the third AND-OR element, the first, second, third outputs of the connection counter: the first, second, third information decoder inputs, the first, second, third, fourth outputs of which are connected to the individual inputs of the second, first, third, fourth control flip-flops, respectively; the output of the second control flip-flop is connected to the second 45 50 55 ten the second input of the fifteenth element AND is connected to the output of the first OR element, the third input of which is connected to the first information output of the channel transceivers of the fourth group and to the third input of the second AND-OR element, the output of which is connected to the first input of the sixteenth with the first information input of the channel transceivers of the sixth group, the second information input of which is connected to the code of the seven-parent connected to the output of the third element AND-OR, the third input of which is connected to the second information output of the channel transceivers of the fourth group, the third information output of which is connected to the second input of the fourteenth element AND, the output of which is connected to the first control input of the channel transceivers of the first group and to the first input the fourth OR element, the output of which is connected to the second inputs of the sixth, eighth, eleventh elecCements AND, to the first control input of the channel transceivers of the third the second input of the fourth element OR is connected to the first control input of the channel transceiver, the sensors of the second group and the output of the thirteenth element I, the second input of which is connected to the second information output of the channel transceivers p of the group, the first information output of which is connected to the fourth input of the second element AND-OR and the third input of the second the OR element, the output of which is connected to the second input of the twelfth AND element, the third information output of the channel transceivers of the fifth group is connected to the fourth input of the third AND-OR element, the first, second, third outputs of the connection counter: the first, second, third information decoder inputs, the first, second, third, fourth outputs of which are connected to the individual inputs of the second, first, third, fourth control flip-flops, respectively; the output of the second control flip-flop is connected to the second eleven the input of the sixteenth element And, the output of the third control trigger is connected to the second input of the seventeenth element And, the output of the fourth control trigger is connected to the third inputs of the third and fourth elements And, the output of the first control trigger is connected to the second control input of the multiplexer, with the third inputs of the thirteenth and fourteenth elements And, the outputs of the sixth, eighth and eleventh elements And are connected to the second control inputs of the channel receivers of the first, second and third groups but the information output of the third channel Synchronization K1 SNA K2 SIL addresses Synchronization of data entry K1 INP K2 INPUT K1 CONCLUSION K1 CPD K1 W1D K2 PPD K1 BYTE K2 BYTE K1 PV K2 PV K1 SIP K2 SIP 6508912 the transceiver is connected to the information inputs of the first and second channel transceivers, the information outputs of which are connected to the first, second inputs of the fifth OR element, the output of which is connected to the information input of the third channel of the transceiver, the fourth output of the counter is connected to its recording input, first, second, third information inputs of the counter are connected to the zero potential bus of the device, the fourth information input of the counter and the information input of the first trigger y The boards are connected to the unit potential bus. ten 15 KZ DREAM KZ ENTER ENTER 3 K2 CONCLUSION KZ CONCLUSION KZ PPR1 K 2 CPD KZ PPR2 KZ PPD1 KZ PPD2 KZ BYTE KZ PV KZ CIP 13 1365089 K1 TPD K2 TPD (ninth output) K1 TPD (tenth output) K2 TPD (tenth output) 14 Continuation of the table KZ TPR1 KZ TPR2 (thirteenth entry) KZ TSH11 (twelfth entry) KZ TPD2 (fourteenth entry) ENTER ENTER 1 T2 INPUT 2 P 1 P 2 TI1, TI2, TIZ, TI4 K1 PV INPUT K2 PV INPUT Direct Channel Transmission Control First Channel Address Synchronization Synchronize second channel address KZ PV INPUT SIL 1 SIA 2 Ouiuzi CLAH. -state on ciitna / iot in various Fig 4 JlJPJ lJTLJPJPJlJTGLrLJJ. the address of the vector is signaling state indifferent Gi KZ 7PSH {BBA / Y // 7/7/7 KZPPM / 7 / P2 KZPV (KinB) KZSIA (K1SIA Kzbbod (K1dbo} Kzdydod (Kidb / Sod) K1SIP, (KZSIL) Ford (bdod) T2 UPVbod KZPVbboZ in the address of the data channel 3 address data ZZIDO © C5CIZ 6