SU1418728A1 - Interface of two trunk lines - Google Patents

Abstract

The invention relates to computing and is intended for interfacing a parallel interface trunk and a CAMAC trunk. The aim of the invention is to expand the scope. This goal is achieved by the fact that the device containing the first decoder of the mode has two data registers, a response register, the first query register, the initial setup register, the reset register, the transceiver unit, the synchronization unit, the command register, the switching unit, the address coder, prohibition register, register recognized; as an address command and the second request register. 5 il. with

Description

1U

The invention relates to computing and is intended for; interface of the parallel interface of the terfeys (the microcomputer trunk) with the CAMAC trunk,

The need for such interconnection arises when creating systems for the immigration, modeling and testing of hardware and software of CAMAC systems, in particular when solving problems of modeling objects.

; The aim of the invention is to expand the scope of application through the organization of additional modes of operation.

Fig, 1 is a block diagram of the device; Fig 2 is a block diagram of the Apple Sync; Fig, 3 -; scheme of the second decoder mode; in fig. 4 - scheme of the first depfractor mode; FIG. 5 is an address encoder circuit.

The device contains the first decoder mode 1, the first data register 2, the command register 3, the prohibition register 4, the response register 5, the second data register 6, the readiness register 7, the first request register 8, the address command register 9, the initial setting register 10, the register 11 resets, second decoder 12 modes, switching unit 13, unit

14 transceivers, second register

15 requests, 16 address encoder and synchronization block 17.

The synchronization unit 17 contains elements AND 18-27, elements NOT 28-36, elements OR 37-40, element AND-OR 41 and trigger 42, the Second decoder 12 of the mode contains elements HE 43-50, a group of trigger 51, elements AND 52- 54, trigger 55, selector 56, elements OR 57-60 and elements 61-70,

The first decoder mode 1 contains the elements NOT 71-79, the elements 80 80 83, the elements of the IPI 84-87 and the selector 88 the address encoder 16 contains the elements NOT 89-93, elements AND 94.95} the trigger 96 and the element I-SH1I 97.

The device works as follows.

When powering the crate is turned on, the first request register 8 is reset. When the power of the microcomputer is turned on, the Reset signal is generated on the paralphone interface backbone by setting the 87282

readily available readiness register 7, block 17, second mode decoder 12, address instruction 9 register, register

 10 initial setup and reset register 11. When the crate controller transmits the initial installation command or the reset command, the transmission is

the second gate is recorded in registers 10 and 11 of the initial installation and reset, respectively. Then the register 10 of the initial installation initiates a cycle of aborting the work of the micro-computer,

, and also sets the ready register 7 to the active state, indicating the state of the exchange between the interface device and the micro-computer, whereby from the switching unit 13 through

.. the transceiver unit 14 enters the code of the address of the vector of the prefixed, corresponding to either the initial setup routine or the reset routine, depending on

1J as the command is transmitted by the crate controller. One of the commands of the initial setup routine clears the source of the request, and when the reset register 11 is active, block 17 initiates the shutdown cycle, as described. When the controller sends the crate together with the initial setup command of the prohibition command, the state of the corresponding bus of the main crate is recorded in register 4 on the second gate along the second gate. During the execution of the initial setup routine, implemented by the microcomputer, the contents of register 4 are disabled and the switching unit 13 is switched to the trunk of the microcomputer parallel interface. When the crate controller sends the address commands, the write data is written to the first bus register

 2 data and a register of 3 commands according to the corresponding control signals of the record generated by the first decoder of the 1 mode. When writing information to the command register, the fact of transmission of the address

The 0 command is fixed in the register 9 of the indication of the address command, while the block 17 initiates a cycle of aborting the microcomputer operation, as described above. The transfer of the contents of the first registrar 2 dunng, the register of 3 commands, the prohibition register 4, as well as the interrupt vectors to the microcomputer trunk is carried out via switch unit 13

tion and block 14 transceivers. The switching address is specified by the address encoder 16, which is controlled by the signals of the second decoder mode 12 when transmitting information from the indicated registers and the signals of block 17, as well as the second request register 15 when transmitting interrupt vectors. Information intended for transmission to the mainline of the crate is read out from the microcomputer via transceiver unit 14 to the first request register 8, the second data register 6 and the response register 5 from the recording signals generated by the second decoder 12 mode of operation. According to the commands of the crate controller, information from the response register 5 and the second data register 6 is transmitted to the crate trunk under the influence of control signals generated by the first decoder of the first operation mode. Information from the first register 8 requests is transmitted to the crate trunk permanently. Upon receipt of address commands from the main line, the transfer of information from the first request register to the main line is blocked. When the exchange between the interface device and the microcomputer is completed, the latter transmits a command, under the action of which the second decoder 12 of the mode generates a signal to set the readiness register 7 to the 7th state. By the corresponding command of the controller of the crate, the contents of the ready register 7 are transmitted to the main of the crate under the action of a control signal generated by the first decoder of the 1st mode of operation,

The synchronization unit 17 functions as follows.

When the microcomputer is powered up, a K RESET N signal is generated, which clears the bus to terminate the CTPRN bus. The appearance of an active signal at the group of inputs of the AND-OR elements 41 leads to the formation of a KTPRN signal, as well as activation of the signals at the first and fifth outputs. The signal from the first output is designed to capture the input information in the register 15 requests. The signal from the fifth output switches readiness register 7 to the active state. In the microcomputer interruption cycle, when a signal is received K INPUT N of the microcomputer control bus, the signal is activated

five

0

in the third code, the address encoder 16 generates an address that goes to the -13-switching unit. When the control bus signal of the microcomputer K SPR 1 N is cleared, the CRP N is cleared, the signals on the first, third and fifth outputs become passive, a signal is generated on

Q to the fourth output, which determines the direction of information transfer through the transceiver unit 14 from the interface to the microcomputer, and a control bus signal K SIN H is formed. After removing the signal K Tire 1 N, the bus K SIP N is cleared, and the signal on the fourth output takes the initial value, determining to the direction the direction of information transfer from the micro-computer through the transceiver unit 14 to the elements of the interface device. When micro-computer information and this interface are exchanged, in the Input and Output cycles, a signal is also generated.

5 К ШП Н, and in the Input cycle - a signal at the fourth output. When one of the cleaning signals appears on the cleaning input group, the D-flip-flop clock input is prepared for sensing the corresponding signal5 and the third output is activated, and the address encoder 16 generates the address received by the commutation unit 13. The second depmfrator 12 modes of operation operates as follows

5 In the address part of the Input and Output cycles, with the appropriate combination on the second group of inputs, on the leading edge of the control bus signal, the microcomputer K SIL H, the selection N and selection B signals are activated, the state of the four lower digits of the address / data pin is fixed in the register . The output information of the register is decrypted, and when a signal K INPUT N or L EXT N is detected on the microcomputer control bus, one of the interface elements control signals appears on the group of main outputs. On the falling edge of the signals is the selection of N

0 and SELECT B take the original value, and the decryption of the output of the register is prohibited.

The first decoder of the 1 operation mode functions as follows. With

5, by addressing the interface device crate controller in the CAMAC cycle, the corresponding signal combination is decrypted on the sub-address AO-AZ bus.

0

0

five

51

 From the outputs of the dust generator, in combination with the signals of the bus function F1-F5 and the signal of the strobe 51, one of the control signals of the second group of outputs is determined.

Claims (1)

Invention Formula A device for interfacing two trunks containing the first mode decoder, two data registers, the response register, the first request register, the initial setup register, the reset register, the transceiver unit, the synchronization unit, the first group of input-output mode settings which is also an input-output group devices for connecting to the synchronization buses and selecting the mode of the first highway; a gate input and a group of information inputs of the first mode decoder are respectively an input and a group of inputs of the device and for connecting to the first gating bus and the information bus group of the second bus, the first output of the first mode decoder is the device output for connecting the second bus to the first bus, the information inputs of the first data register are the input group of the device the records of the second line, the outputs of the response register of the first register of the request are the outputs of the device for connecting respectively to the second state bus and to the read bus In the second bus, the output group of the second data register is the device output group for connecting the second line to the read bus group, the information inputs of the initial and reset registers are the device inputs for connecting to the installation buses and resetting the second highway, synchronous inputs of the initial set registers and reset are the inputs of the device for connection to the second gate of the second gate, the second, third and fourth outputs of the first decoder mode are connected respectively with the synchronous inputs of the first and second data registers and the input of the response register, information inputs / outputs are 286 P1) and its transmissions are wired to the input-output of the device for connecting to the information buses of the first line, characterized in that, in order to expand the scope of application due to the organization of additional modes of operation, the register of commands, the register readiness, second mode decoder, switching unit, address encoder, prohibition register, address command register register and second request register, the group of information the command register inputs is a group of device inputs for connecting the second highway to the second group of write buses, the synchronous input, the first, second information of the prohibition register are the device inputs for connecting the second gate bus respectively, the third state bus and the second line reset bus, the output the readiness register is the output of the device for connecting the readiness of the second highway to the read bus; the first group of information inputs of the second mode decoder is the input group s device for connection to a group of the tire and identifying the mode of the first line, the band transceiver unit output is connected to a second group of information inputs of the second decoder mode and a group information inputs of the second data register, the first, second and third outputs of the transceiver unit are connected respectively to the first information inputs of the response and readiness registers, the information input of the first query register, the output group of the second mode decoder is connected to the first group of information inputs of the encoder ad reza, the second group of outputs of the second the mode decoder is connected to the sync-paths of the first data register, command registers, response, readiness, address coder's sign register, initial setup register, second data register, request register and to the group of cleaning inputs of the synchronization unit, the fifth, sixth and seventh outputs of the first decoder 55 modes are connected respectively with the synchronous inputs of the command register, readiness register and the register of the address command, the register outputs the sign of the address KOMaimbi, the initial setup register and the reset register are connected to the first, second and third information inputs of the second query register and the enable group of the synchronization unit, the first output of which is connected to the synchronous input of the second query register, the output group of which is connected to the second group of information inputs the address encoder, the outputs of which are connected to the address 4 inputs of the switching unit, and the first and second permitting inputs of the address encoder are connected to the second and tr respectively temu outputs sync block, a fourth output is connected to the enabling input of the transceiver unit, and the fifth 28 The Bt-txoA synchronization unit is connected to the information input of the readiness register, the first group of outputs of the first data register and the first group of outputs of the command register are connected to the first group of information inputs of the transceiver unit, the second group of information inputs of which are connected to the group of switching unit, the first and second group informational inputs of which are connected respectively to the second and third groups of outputs of the first data register, the third group of informational input inputs of the switching unit is connected to the second group of outputs of the register of commands, the control input of the block 1 of the round, is connected to the output of the register of prohibition. kpptn D J-d $ EXPOZ h-and SiMtaS ru.g Figz four  DuuHdz (i-2 y u alchnon nymdofnn | {