JPS5451737A - Input/output data transfer system - Google Patents

Input/output data transfer system

Info

Publication number
JPS5451737A
JPS5451737A JP11783677A JP11783677A JPS5451737A JP S5451737 A JPS5451737 A JP S5451737A JP 11783677 A JP11783677 A JP 11783677A JP 11783677 A JP11783677 A JP 11783677A JP S5451737 A JPS5451737 A JP S5451737A
Authority
JP
Japan
Prior art keywords
data
byte
register
transferred
maximum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11783677A
Other languages
Japanese (ja)
Other versions
JPS6010344B2 (en
Inventor
Takeshi Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11783677A priority Critical patent/JPS6010344B2/en
Publication of JPS5451737A publication Critical patent/JPS5451737A/en
Publication of JPS6010344B2 publication Critical patent/JPS6010344B2/en
Expired legal-status Critical Current

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  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To reduce the frequency of the memory access as well as to increase the process non-response allowance time and to enhance the process efficiency, by processing the byte number equivalent to the memory access with the 1-byte transfer in case the data to be transferred are identical.
CONSTITUTION: The 1 byte of input/output device B and the data of data buffer register 6 which are read out of I/O are transferred to input data register 2 of channel A to be transferred to the desired 4-byte position of memory register 1 and then to be stored in memory 100 ( which can read in the data of maximum 4 bytes with one memory cycle MC). Then counter 9 counts up to "3", i.e., the maximum byte number that can be processed with 1 MC. Accordingly, register 6 features a buffer function up to maximum 4 bytes in case the same data are continuous, thus increasing the process non-response allowance time. In the case of transfer from B to A, the same data equivalent to maximum 4 bytes can be transferred to each byte position of register 1 just through transfer of the data of 1 byte
COPYRIGHT: (C)1979,JPO&Japio
JP11783677A 1977-10-03 1977-10-03 Input/output data transfer method Expired JPS6010344B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11783677A JPS6010344B2 (en) 1977-10-03 1977-10-03 Input/output data transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11783677A JPS6010344B2 (en) 1977-10-03 1977-10-03 Input/output data transfer method

Publications (2)

Publication Number Publication Date
JPS5451737A true JPS5451737A (en) 1979-04-23
JPS6010344B2 JPS6010344B2 (en) 1985-03-16

Family

ID=14721445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11783677A Expired JPS6010344B2 (en) 1977-10-03 1977-10-03 Input/output data transfer method

Country Status (1)

Country Link
JP (1) JPS6010344B2 (en)

Also Published As

Publication number Publication date
JPS6010344B2 (en) 1985-03-16

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