JPH03203445A - Line control system based upon switching of receiving buffer - Google Patents

Abstract

PURPOSE:To increase a data communication speed by writing received data in an individual memory in each frame and reading out the data from the memory even in its writing to execute receiving processing by a CPU. CONSTITUTION:At the time of receiving an interruption signal, the CPU 10 reads out a DMAC transfer frequency counting number from a DMAC transfer frequency counter 70 and sets up a DMAC 30 so that the succeeding frame data are transferred to a memory 40-2 for instance. Simultaneously, the CPU 1 reads out the received data for the number of bytes corresponding to the count value from a memory 40-1 until the reception of the succeeding frame is completed to execute the receiving processing. Since the received data are written in individual memories in each frame by increasing the number of memories up to the memory 40-n and the stored data can be read out even in the writing operation to execute the receiving processing by the CPU, the data communication speed can be increased.

Description

[Detailed Description of the Invention] [Summary] Regarding a line control method by switching reception buffers of a line control unit using an HDLC procedure without a chain function, a line control method by switching reception buffers that can realize high-speed data communication speed. The purpose is to provide CPU, open^C, and HD L without chain function.
D using C procedure? A line control unit that transfers received data in a frame configuration to memory using an output control signal from the iAC, and a memory that writes data input from the line control unit and reads it out to the CPU are connected to each other by a bus, and the end of the frame is transferred from the received data to the memory. In a line control method for a line control unit that has a flag detection circuit that detects a flag indicating a flag and outputs a control signal to the CPU, a transfer count unit that is connected to a bus and counts the number of times data is transferred from the line control unit to the memory. and the memory is a second memory consisting of a plurality of memory pieces in which data is written separately for each frame, the second memory is switched by the output of the flag detection circuit, and the received data is written separately for each frame, Even during writing, the data written in the second memory is sequentially read out to the CPU by the output of the transfer count section.

[Industrial Application Field] The present invention is applicable to HDLC procedures (lligh level
Data Link Control Procedure
The present invention relates to a line control method using reception buffer switching of a line control unit using a high-level data link procedure (re, high-level data link procedure).

Line control Ls1 circuit (hereinafter referred to as line control 1LsI)
When using an external DMAC (Direct Me
When data is received from the line, line control l1L is required.
By the time all of the data has been received in the reception buffer memory in sI, the CPU must complete the processing related to the reception data written to the memory from the line control 1LsI and read from the memory.

As data communication speeds increase, CPU processing cannot be completed until all of the data has been received in the reception buffer memory in the line control LSI. As a result, the receive buffer memory becomes full with received data and the received data is discarded, so it is necessary to speed up the line control processing.

Therefore, there is a need for a line control system that can realize higher data communication speeds.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional line control unit.

In FIG. 3, the line control LsI 2 receives serial data constituting one frame of several bytes. Then, each time one byte is received, the line control is executed by DMAC3.
The data is transferred from the LSI 2 to the memory 4 via the bus 5 and written therein. This operation is performed for each byte, and when one frame of data is completed, the received data of the line control LsI 2 is branched and inputted to a flag detection circuit (not shown), and a flag indicating the end of the received data is detected and the CPU
1 as an interrupt signal.

When the CPU 1 receives this interrupt signal, it reads out the data stored in the memory 4 and starts data reception processing.

[Problem to be solved by the invention] However, in the above-mentioned line control unit, cp
DMAC from the time when u starts the reception process until it ends.
Since the CPU is suspending the work of transferring the received data in the line control ILsI to the memory, the CPU transfers the reception processing between lines?
It must be completed by the time all of the data in the receive buffer memory in IILsI has been received. For this reason, as the data communication speed increases, there is a problem in that the CPU cannot perform reception processing in time and the received data is destroyed.

Therefore, it is an object of the present invention to provide a line control system using receive buffer switching that can realize higher data communication speeds.

[Means to solve the problem]

The above problem is solved by the configuration of the unit shown in FIG.

That is, in FIG. 1, the CPU 100 and the DMAC 300
and DMA using HDLC procedure without chaining function.
A line control unit 200 that transfers received data in a frame configuration to a memory 400 using an output control signal of C and a memory 400 that writes data input from the line control unit and reads it out to the CPU are connected to each other by a bus, and are connected to each other by a bus. In a line control system for a line control unit having a flag detection circuit 600 that detects a flag indicating the end of a frame and outputs a control signal to the CPU, 700 is connected to a bus and measures the number of times data is transferred from the line control unit to the memory. This is a transfer count unit provided for counting.

and a plurality of second memories 800-1 to 800-n in which data is written separately for each frame.
shall be.

Then, the second memory is switched by the output of the flag detection circuit, and the received data is written separately for each frame.
Even during writing, the data written in the second memory is sequentially read out to the CPU by the output of the transfer count section.

(Function) In FIG. 1, the data received by the line control unit 200 is written into the second memory which is switched every l frame by the output of the flag detection circuit 600. At the same time, one second
A transfer count unit 700 counts the number of bytes of data written into the memory. During writing, the second memory 800-1 to 800-1 to
The data written to 00-n is sequentially read out to the CPU.

As a result, the CPU ioo only has to complete the reception process within one frame length, making it possible to achieve a higher data communication speed.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a line control unit according to an embodiment of the present invention.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, when the line control LSI 20 receives 1 byte of serial data, the DM is sent to the MAC 30.
^Outputs the REQUEST signal (DREQ signal). D
When the MAC50 receives the DREQ signal, the CPII
10NIll0LII REQtlEST signal (HLD
REQ signal). When the CPII 10 is ready to release the bus 50, it turns 1 (OL port ^CKNOWLE).
It outputs the DGB signal (tlLD A (J signal)) to the DMAC 50. When the DMAC 50 receives the HLD ACK signal, it recognizes that the bus 50 has been taken, and notifies the DMA of this.
The line charge (IILsI 20) is notified by the ACKNO LED GII' signal (DACx signal).

Next, DMAC30 is 1 in line charge 4i1LSI 20.
The received data corresponding to bytes is transferred to the memory 40-1, for example. When the transfer is completed, the line charge is 4IILSl 20 is DR
The output of the EQ signal is stopped, and the DMAC 50 stops outputting the signal to the DAC.

The above operation is repeated, and finally the flag detection circuit 60 branches the received data and transfers it to the shift register 6.
1 and converted into parallel data, and a flag pattern (for example, "01111110" consisting of 8 bits) 62 output from a flag pattern generation circuit (not shown).
The exclusive OR circuit 63 detects the flag indicating the end of the frame and sends the interrupt signal to CP
Output at t110.

When CPU IO receives an interrupt signal, DM^C
Transfer count The count of transfer times of Tauntau 0 MAC is read and the DMAC 50 is set to transfer the next frame data to, for example, the memory 40-2. At the same time, the CPU 10 reads the received data of the number of bytes corresponding to the count number from the memory 40-1 and performs the reception process until the next frame is finished receiving.

As a result, the memory for each frame is memory 40-3,...
・By increasing the number of frames, such as 40-n, the received data can be written to a separate memory for each frame, and even during writing, it can be read from the memory and received processing can be performed by the CPU, resulting in faster data communication speeds. can do.

〔Effect of the invention〕

As explained above, according to the present invention, received data can be written to a separate memory for each frame, and even during writing, it can be read from the memory and received processing can be performed by the CPU, thereby realizing an increase in data communication speed. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the configuration of a line control unit according to an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional line control unit. In the figure, 700 is a transfer count unit, and 800-1 to 800-n are second memories. Fig. 1 shows the structure of the cut sheet of the present invention.

Claims (1)

[Claims] A CPU (100), a DMAC (300), and an HDLC procedure without a chain function are used to store received data in a frame structure in a memory (40) according to an output control signal of the DMAC.
A line control unit (200) that transfers data to 0) and a memory (400) that reads data input from the line control unit to the writing CPU are connected to each other by a bus,
A flag detection circuit (600) detects a flag indicating the end of a frame from the received data and outputs a control signal to the CPU.
), a transfer count unit (70) connected to the bus and counting the number of times data is transferred from the line control unit to the memory.
A second memory (800-0) is provided, and the second memory (800-
1 to 800-n), the second memory is switched by the output of the flag detection circuit, the received data is written separately for each frame, and even during writing, the second memory is switched by the output of the transfer count section. 1. A line control system using reception buffer switching, characterized in that data written to a CPU is sequentially read out to the CPU.