JPH03198452A - Line control system by housing reception buffer - Google Patents

Abstract

PURPOSE:To accelerate the communication velocity of data and to improve the reliability of the data by storing the received data into a memory for each frame and executing a reception processing by a CPU while reading out the data from the memory even during the storage as well. CONSTITUTION:A transfer time number count part 700 is provided to count the number of times for transferring the data from a line control part 200 to a memory 400 while being connected to a bus, and tables 410-1-410-n are provided to store the data into the memory 400 for the unit of the frame. The received data are stored into the tables in the memory 400 for each frame and the reception processing is executed by a CPU 100 while reading out the data from the tables even during the storage as well. Thus, the received data can be preserved without being damaged, the communication velocity of the data can be accelerated and the reliability of the data can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a line control method by storing a reception buffer in a line control unit using an HDLC procedure without a chain function, it is possible to realize high-speed data communication speed and high data reliability. The purpose is to provide a line control method using reception buffer storage, and there is no CPU, DMAC, or chain function.
Line control of a line control unit in which a line control unit that transfers received data in a frame structure to memory using a DMAC output control signal according to a procedure, and a memory that reads data input from the line control unit to a writing CPU are connected to each other by a bus. In this method, a transfer count unit is provided that is connected to the bus and counts the number of times data is transferred from the line control unit to the memory, and a table that can store data in units of frames is provided in the memory, and the data is received by the line control unit. The data stored in the table is stored separately in a table for each frame, and even during storage, the data stored in the table is sequentially read out to the CPU by the output of the transfer count section.

[Industrial application field]

The present invention uses a so-called HDLC procedure (High Level D) without a chain function that transfers data in batches.
ataLink Control Procedure
, using high-level data link control procedures).
This invention relates to an improvement in a line control system by storing a reception buffer in a line control unit.

When using a line control LSI circuit (hereinafter referred to as line control LSI), an external DMAC (Direct Mem
When data is received from the line, the CPU stores the received data from the line control LSI in the memory and reads it from the memory until all the data has been received in the receive buffer memory in the line control LSI. The related process must be completed.

As data communication speeds increase, processing by the cPU cannot be completed until all of the data has been received in the receive buffer memory in the line control LSI. the result,
Since the receive buffer memory becomes full with received data and the received data is destroyed, it is necessary to speed up the line control processing.

Therefore, there is a need for a line control system that can achieve higher data communication speeds and higher data reliability.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional line control unit.

In FIG. 4, the line control LSI 2 receives serial data that constitutes one frame of several bytes. Each time one byte is received, the DMAC 3 transfers it from the line control LSI 2 to the memory 4 via the bus 5 and writes it. This operation is performed for each byte, and when one frame of data is completed, a flag detecting circuit (not shown) to which the received data of the line control LSI 2 is branched and inputted, detects a flag indicating the end of the received data, and the CPU l
output as an interrupt signal. When the CPU 1 receives this interrupt signal, it reads out the data stored in the memory 4 and starts data reception processing.

[Problem to be solved by the invention]

However, in the configuration of a conventional line control unit, D
Since the MAC suspends the work of transferring the received data in the line control LSI to the memory, the CPU should not complete the reception process until all the data has been received in the receive buffer memory in the line control LSI. For this reason, as the data communication speed increases, there is a problem that the reception processing by the CPU cannot be done in time (and the received data may be destroyed).

Therefore, it is an object of the present invention to provide a line control system using reception buffer storage that can realize higher data communication speeds and higher data reliability.

[Means to solve the problem]

The above problem is solved by the configuration of the device shown in FIG.

That is, in FIG. 1, the CPU 100 and the DMAC 300
, there is no chain function, and DMAC is performed using the HDLC procedure.
A line control unit 200 that transfers received data in a frame configuration to a memory 400 using an output control signal from the line control unit 200, and a memory 4 that reads data input from the line control unit to the writing CPU.
In a line control system of a line control unit in which 00 and 700 are connected to each other by a bus, 700 is connected to the bus,
This is a transfer count unit that counts the number of times data has been transferred from the line control unit to the memory.

Further, 410-1 to 410-n are tables provided in the memory and capable of storing data in units of frames.

The data received by the line control unit is stored separately in a table for each frame, and even during storage, the data stored in the table is sequentially transferred to the CPU using the output of the transfer count unit.
Configure it to read out.

[For production]

In FIG. 1, a table 410 is provided in a memo 00 for each frame of data received by the line control unit 200.
-1 to 410-n. A transfer count unit 700 counts the number of bytes of data stored in one table at the same time. Then, even during storage, the data stored in the tables 410-1 to 410-n is sequentially read out to the CPU 100 by the number of bytes corresponding to the transfer count output from the transfer count section 700.

As a result, the received data can be stored frame by frame in the table in Memo January 00, and even while being stored, it can be read from the table and the reception process can be performed by the CPU 100, so that the received data can be saved without being lost. It is possible to achieve higher data communication speed and higher data reliability.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a line control unit according to an embodiment of the present invention.

FIG. 3 is a flowchart for explaining the operation of the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, when the line control LSI 20 receives 1 byte of serial data, the DMAC 50 sends the DM
A REQUEST signal (DREQ signal) is output.

When the DMAC 50 receives the DREQ signal, the CPU
10 is the HOLD REQUEST signal (HLD REQ
signal). When the CPU 10 becomes ready to release the bus 50, it outputs a HOLD ACKNOWLEDGE signal (HLD ACK signal) to the DMAC 50.

When the DMAC 50 receives the HLD ACK signal, it recognizes that the bus 50 has been taken and sends a DMA ACKN signal.
The line control LSI 20 is notified by the OWLEDGE signal (DACK signal).

Next, the DMAC 50 transfers 1 byte of received data in the line control LSI 20 to the address (for example, area ■) indicated by the storage pointer 46 in the memo 1 month 0, and
For example, write in area ■. When the transfer is completed, the line control LSI 20 stops outputting the DREQ signal, and the DM
AC50 stops outputting the DACK signal. The above operation is repeated, and finally, the data obtained by branching the received data in the flag detection circuit 60 is inputted to the shift register 61 to convert the data into parallel data and the flag pattern (not shown) output from the flag pattern generation circuit (not shown). For example 8
An exclusive OR circuit 63 detects a flag indicating the end of the frame, and outputs an interrupt signal to the CPU 10.

When the CPU 10 receives the interrupt signal, it processes the storage pointer 46 as shown in FIG. 3(a). That is,
The address indicated by the storage pointer 46 is the END pointer 45
It is determined whether the addresses are equal to each other, and if they are equal, the storage pointer 46 is returned to the first address. And DM
Set the AC 50 to transfer the next frame data to the next storage area (for example, area ■). At the same time, C.P.
U10 is the DMAC transfer count from the DMAC transfer counter 70.
The transfer count is read, data of the number of bytes corresponding to the count is read from the address indicated by the read pointer 47 in the memo January 0, and predetermined processing is performed.

The operation of the read pointer is shown in FIG. 3(b). That is, the address indicated by the read pointer 47 is EN.
It is determined whether or not the address is equal to the address of the D pointer 45, and if they are equal, the read pointer 47 is returned to the start address of the write area. Next, it is determined whether the address indicated by the storage pointer 46 is equal to the address indicated by the read pointer 47, and if they are not equal (because the data stored at that address has not been read yet), the address indicated by the read pointer 47 is determined. Read data from the area. Then, the address of the read pointer 47 is updated.

It should be noted that the storage capacity of each area ■, ■, .

As a result, storage and retrieval of one storage area in the memo January 0 can be carried out asynchronously, making it possible to achieve higher data communication speeds and higher data reliability.

〔Effect of the invention〕

As explained above, according to the present invention, received data can be stored frame by frame in the memory, and even while being stored, it can be read out from the memory and the reception process can be performed by the CPU, so that the received data will not be lost (save data). This makes it possible to achieve higher data communication speeds and higher data reliability.

410-1 to 410-n are tables, 700 is the transfer count section shows.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the configuration of a line control unit according to an embodiment of the present invention, Fig. 3 is a flowchart for explaining the operation of the embodiment, and Fig. 4 is a conventional FIG. 2 is a block diagram showing the configuration of an example line control unit. Detailed pointer processing in the figure (Q) Explaining the movement of the correction A column Figure 3

Claims (1)

[Claims] A CPU (100), a DMAC (300), and a memory (400) which does not have a chain function and stores received data in a frame structure according to an output control signal of the DMAC according to an HDLC procedure.
A line control unit (200) that transfers data to the line control unit, and a memory (4) that writes data input from the line control unit and reads it to the CPU.
00) are connected to each other by a bus, a transfer count unit (70) is connected to the bus and counts the number of times data has been transferred from the line control unit to the memory.
0), and tables (410-1 to 410-n) capable of storing data frame by frame are provided in the memory, and the data received by the line control unit is stored separately in the table for each frame. A line control system using reception buffer storage, characterized in that even during storage, the data stored in the table is sequentially read out to the CPU by the output of the transfer count section.