JPH06309169A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor where the switching time of register banks is shortened. CONSTITUTION:A register file 2 where save and restore of information in registers are managed with a group as the unit, an incorporated RAM 3 to/from which information is saved/restored from/to the register file 2 through a private bus with a group as the unit, and a bank switching control circuit 1 which saves or restores only registers, which are discriminated based on information designating registers to be used before and after save or restore with a group as the unit and are used in common before and after save or restore, with a group as the unit are provided and are formed on the same chip to constitute the information processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bank switching of an information processing device having a register bank function.

[0002]

2. Description of the Related Art Register bank switching is performed at the time of an interrupt or a subroutine call, and the contents of general-purpose registers in the CPU before the interrupt is generated or before the subroutine call are temporarily saved or the saved contents are saved. Used to restore general purpose registers.

As one of the methods of realizing such a register bank function, there is a method of using an on-chip built-in RAM of a single-chip computer as a save destination of a general-purpose register. At this time, in order to perform high-speed bank switching,
The CPU and built-in RAM are connected by a dedicated bus for bank switching to transfer data.

FIG. 3 shows a block diagram of such a conventional microcomputer.

In FIG. 3, the microcomputer is
CPU internal control circuit 101 and bank switching control circuit 10
2 and register file (16 bits x 16 lines, R0-R
15) 103 and built-in RAM 104. The bank switching control circuit 102 includes a bank pointer register (BP) 105 and an old bank pointer register (O
BP) 106 is included.

When the bank switching control circuit 102 receives a bank switching signal from the CPU internal control circuit 101, it starts control of data transfer between the register file 103 and the internal RAM 104. The bank switching control circuit 102 sends a read / write signal (BRW), an enable signal (BEN) control signal, and an address (BAD) to the built-in RAM 104.
(7: 0)) is output to control the built-in RAM 104.
Further, the bank switching control circuit 102 outputs a read / write signal (RRW), an enable signal (REN), and a select signal (RSEL (1: 0)) to the register file 103 to control the operation of the register file 103. Further, the register file 103 and the internal RAM 104 are 64
It is connected by a bit bus (BNKBUS).

Bank pointer register (BP) 105
Is the internal R of the register file 103 after bank switching
The start position of the mapping area on the AM 104 is designated. The old bank pointer register (OBP) 106 indicates the start position of the mapping area of the register file 103 before the bank switching.

Each of BP and OBP is 8 × N (N = 0,
1, 2 ,. ． ． ． ． ) Holds the byte address value of
An address on the internal RAM 104 can be designated as a start position of the transfer area of the register file 103 in units of 8 bytes.

In such a configuration, when an interrupt or a subroutine call occurs, the CPU internal control circuit 10
1 activates and outputs the bank switching signal to the bank switching control circuit 102, and the bank switching control circuit 102 receives this and performs the following operation as shown in FIG. Control data transfer between them.

First, when the bank switching signal becomes active in the first clock cycle, the bank switching control circuit 1
02 is BNKBU for 64-bit data of R0 to R3
The register file 103 is instructed to output to S, and the internal RAM 104 is instructed to write the data on BNKBUS to the area of the internal RAM 104 having the address of OBP to OBP + 7. This gives R
Registers 0 to R3 are OBP to OB of the internal RAM 104
It is stored in the area of P + 7.

Next, in the second clock cycle, the bank switching control circuit 102 first issues an instruction to the register file 103 to output 64-bit data of R4 to R7 to BNKBUS, and to the internal RAM 104. Data on BNKBUS is stored in the internal RAM 104 as OBP +
It issues an instruction to write in an area having an address of 8 to OBP + 15. As a result, the registers R4 to R7 are stored in the areas of OBP + 8 to OBP + 15 of the internal RAM 104.

Next, in the third clock cycle, the bank switching control circuit 102 first issues an instruction to the register file 103 to output 64-bit data of R8 to R11 to BNKBUS, and to the internal RAM 104. OBP of built-in RAM 104 for data on BNKBUS
It issues an instruction to write in an area having an address of +16 to OBP + 23. As a result, the registers R8 to R11 are stored in the areas of OBP + 16 to OBP + 23 of the internal RAM 104.

Next, in the fourth clock cycle, the bank switching control circuit 102 first issues an instruction to the register file 102 to output 64-bit data of R12 to R15 to BNKBUS, and to the internal RAM 104. OB of the built-in RAM 104 for the data on BNKBUS
It issues an instruction to write in an area having an address of P + 24 to OBP + 31. As a result, the registers of R12 to R15 become OBP + 24 to OBP + 31 of the internal RAM 104.
Stored in the area.

Next, in the fifth clock cycle, the bank switching control circuit 102 issues an instruction to the built-in RAM 104 to output the 64-bit data at the addresses BP to BP + 7 to the BNKBUS, and then the register file. The data on BNKBUS is R0 for 103
Instruct to write to ~ R3. As a result, the built-in R
The data in the BP to BP + 7 area of AM104 is R0 to R3
Loaded in.

Next, in the sixth clock cycle, the bank switching control circuit 102 issues an instruction to the built-in RAM 104 to output the 64-bit data at the addresses BP + 8 to BP + 15 to the BNKBUS, and then the register file. An instruction is issued to 103 to write the data on BNKBUS to R4 to R7. This allows
The data in the BP + 8 to BP + 15 areas of the internal RAM 104 are loaded into R4 to R7.

Next, in the seventh clock cycle, the bank switching control circuit 102 issues an instruction to the built-in RAM 104 to output the 64-bit data at the addresses of BP + 16 to BP + 23 to BNKBUS, and to register file. An instruction is issued to 103 to write the data on BNKBUS to R8 to R11. As a result, the data in the BP + 16 to BP + 23 areas of the internal RAM 104 are loaded into R8 to R11.

Finally, in the eighth clock cycle, the bank switching control circuit 102 issues an instruction to the built-in RAM 104 to output the 64-bit data at the addresses BP + 24 to BP + 31 to BNKBUS,
The register file 103 is instructed to write the data on BNKBUS to R12 to R15. As a result, the data in the BP + 24 to BP + 31 areas of the internal RAM 104 are loaded into R12 to R15.

In this way, the register file 103
4 cycles to store all contents of, register file 10
The register bank switching is performed in 4 cycles for loading all contents of 3 and a total of 8 cycles. At this time, built-in RAM
The state of data transfer in the register file 103 and the data in the register file 104 is as shown in FIG. 4, and the entire contents of the register file 103 are stored in the areas of the internal RAM 104 up to OBP and OBP + 31.
The data in the +31 area is loaded into the register file 103.

On the other hand, Japanese Patent Laid-Open No. 63-13842 and Japanese Patent Laid-Open No. 2-1738226 disclose an information processing apparatus that saves and restores only necessary registers when task switching or subroutine call occurs. Have been described.

However, in these information processing apparatuses, the structure of the general-purpose register is not a bank structure, and save / restore control is performed for each individual register. For this reason, the processing efficiency of evacuation and recovery is poor, resulting in a decrease in processing capacity. Further, in the above information processing device, the main storage device for saving and restoring the information of the general-purpose register is not formed on the same chip as the general-purpose register and the CPU, and the input / output of information between the general-purpose register and the main storage device is performed. It required a dedicated bus and data bus.

For this reason, when a dedicated bus is provided, the bus must be provided between separate chips of a chip including a general-purpose register and a chip including a main memory device. When the number of bits of transfer data increases, the dedicated bus is used. The formation of the bus was difficult. On the other hand, when the data bus provided in the information processing device is used, the data bus is monopolized when the general-purpose register is saved and restored, and other data cannot be transferred, resulting in a decrease in processing efficiency. It was

[0022]

As described above,
In the conventional information processing apparatus shown in FIGS. 3 and 4, all the contents of the register file are saved and restored by transferring the data through the built-in RAM and the dedicated bus on the same chip. . For this reason, a large amount of time is required for saving and restoring, which causes a problem that the processing efficiency of the processing that requires bank switching is reduced.

On the other hand, in the information processing apparatus disclosed in Japanese Patent Laid-Open No. 63-138432 or Japanese Patent Laid-Open No. 2-1738226, saving / restoring is controlled for each individual register and a general-purpose register is used. Since the main memory device is not integrated into one chip, there are problems that the transfer efficiency is lowered and it is difficult to form the transfer bus.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to reduce the time required for saving and recovering a register file to improve the processing capability. To provide.

[0025]

In order to achieve the above-mentioned object, the invention according to claim 1 is such that the registers included in the register file are grouped and the information of the registers is saved in group units. A register file for which recovery is managed, a storage device in which register information is saved and recovered in group units via a dedicated bus between the register file, and the registers used before or after saving Group
Holds the information specified in units of groups and the information used in groups to specify the registers to be used after saving or restoring, and based on the held information, registers commonly used before and after saving or recovering registers It has a bank switching control means for discriminating a group and saving or recovering only commonly used registers in group units. The register file, the storage device and the bank switching control means are formed on the same chip. It is composed of

According to a second aspect of the present invention, in the information processing apparatus according to the first aspect, the group of registers used before and after saving or restoring is specified by the upper or lower register number used. The number of registered registers is defined by an integral multiple of the number of registers that can be saved and restored in one cycle time.

[0027]

In the above structure, the invention according to claim 1 provides a group unit between the register file and the storage device via a dedicated bus formed on the same chip in which the register file and the storage device are formed. The information is saved and restored in.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus of the embodiment shown in FIG. 1 is commonly used before and after register bank switching in a microcomputer in which a register file is grouped to transfer data to a built-in RAM to switch register banks. The built-in R functions as a storage device that saves and restores only the registers used for backup and restore, and the information in the register file is saved and restored in group units.
The AM and the register file are formed on the same chip and integrated into one chip.

In FIG. 1, the apparatus of this embodiment has a bank switching control circuit 1, a register file 2 (16 bits × 16) similar to the register file shown in FIG. 3, and a built-in R.
It is composed of AM3. The bank switching control circuit 1 includes a bank size register (BS) 4, a bank pointer register (BP) 5, an old bank size register (OBS) 6, and an old bank pointer register (OB).
P) 7 and a data transfer count register (CNTR) 8 are included. When receiving the bank switching signal, the bank switching control circuit 1 controls the data transfer between the register file 2 and the internal RAM. Bank switching control circuit 1 to built-in R
To the AM3, a read / write signal (BRW), an enable signal (BEN) control signal, and an address (BAD (7:
0)) is supplied. A read / write signal (RRW), an enable signal (REN), and a select signal (RSEL) are sent from the bank switching control circuit 1 to the register file 2.
(1: 0)) is supplied. Also, register file 2
And the built-in RAM 3 are connected by a 64-bit bus (BNKBUS).

The bank size register (BS) 4 specifies a register that can be used after bank switching, and the old bank size register (OBS) 6 specifies a register that can be used before bank switching. Both BS and OBS are 2-bit registers and define usable registers as shown in Table 1.

[0032]

[Table 1] As a designation method, in the case of a subroutine call, information is set in each register by a predetermined instruction executed by software. On the other hand, in the case of interrupt processing, the content of the interrupt is determined in the preprocessing of the interrupt processing, and the information is set in each register based on the determined content.

In the data transfer number register (CNTR) 8, the number of data transfers between the register file 2 and the internal RAM 3 is set according to the contents of BS4 and OBS6.

The bank pointer register (BP) 5 indicates the start position of the mapping area on the internal RAM 3 of the register file 2 after bank switching. The old bank pointer register (OBP) 7 indicates the start position of the mapping area of the register file 2 before bank switching.

BP5 and OBP7 are 8 × N (N = 0, 1,
2. ． ． ． ． ), The address on the internal RAM 3 can be designated as the start position of the mapping area in units of 8 bytes.

In such a configuration, when an interrupt or a subroutine call occurs, the CPU internal control circuit 10
1 activates and outputs the register bank switching signal, and the bank switching control circuit 1 receives this and performs the following operation to control the data transfer between the register file 2 and the internal RAM 3.

First, when the register bank switching signal becomes active, the bank switching control circuit 1 outputs BS4 and OBS.
The number of data transfers is determined from the smaller value of 6, and the data transfer count register (CNTR) 8 is set as shown in Table 2.
Set the value to. If BS4 and OBS6 have the same value, that value is set in CNTR8. And R
Instruct the register file 2 to output 64-bit data of 0 to R3 to BNKBUS,
3 is instructed to write the data on BNKBUS to the area of the internal RAM 3 having the address of OBP to OBP + 7, and R0 to R3 are written to the internal RAM 3 of OBP to OBP.
Store in the area of BP + 7. Then, the value of the data transfer end count register (CNTR) 8 is decremented by "1". In this way, the internal R from the register file 2
Data transfer to AM3 is repeated until the counter reaches "0", and only the necessary contents of the register file 2 are stored in the internal RAM3.

[0038]

[Table 2] Next, the bank switching control circuit 1 determines the number of times of data transfer from the smaller value of BS4 and OBS6, and sets the value in the number register (CNTR) 8. And built-in R
It instructs the AM3 to output the 64-bit data in the area of BP to BP + 7 to BNKBUS, and the register file 2 outputs the data of BNKBUS to R0 to R
3 to write to BP of internal RAM3
The data in the area of BP + 7 is loaded into R0 to R3. Then, after the data transfer is completed, the value of the count register (CNTR) 8 is decremented by "1". In this way, data transfer from the register file 2 to the internal RAM 3 is repeated until the counter reaches "0", and only the necessary contents of the register file 2 are loaded into the internal RAM 3.

For example, the state of data transfer when BS = 01, OBS = 10 is as shown in FIG. At this time, the registers commonly used are eight registers R0 to R7, and the store / load operation to the internal RAM 3 is performed only for these eight registers. Therefore, in this case, 2 clocks for store and 2 clocks for load, total 4
This is the clock data transfer time.

In the above embodiment, when only four registers R0 to R3 are commonly used, the time required to store / load the register file 2 is two cycles. In addition, if only eight registers R0 to R7 are commonly used, register file store / store
The time required for loading is 4 cycles. Further, when only 12 registers R0 to R11 are commonly used, the time required to store / load the register file is 6 cycles. If the registers commonly used are all the registers R0 to R15, the time required to store / load the register file is 8 cycles.

Therefore, the transfer time, which always takes 8 clocks in the prior art, is shortened by 0 to 6 clock cycles depending on how many registers are commonly used. As a result, high-speed register bank switching can be performed, and system performance can be increased.

Further, in the above embodiment, since the register file is grouped and saved and restored in units of 8 bytes (4 registers), the saving,
The management information for recovery is smaller than that when the registers are individually managed, and the management can be performed easily.
Further, since the register file 2 and the built-in RAM 3 are formed on the same chip, the dedicated bus (BNKBUS) for connecting the register file 2 and the built-in RAM 3 can be easily formed as compared with the case of using a different chip. You can

[0043]

The amount of data to be transferred is reduced by holding information about registers used before and after register bank switching and storing / loading only the register commonly used before and after register bank switching from this information. Therefore, the time required for data transfer is shortened, and the time for register bank switching can be shortened.

The registers are grouped into groups and grouped.
Since information is backed up and recovered in units of groups, management of backup and recovery becomes easy. Furthermore, since the device is integrated into one chip, it is possible to easily form a dedicated bus that serves as a transfer path of information for saving and restoring.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing how information is transferred in the device shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional information processing device having a register bank switching function.

FIG. 4 is a diagram showing how information is transferred in the device shown in FIG.

[Explanation of symbols]

 1,102 bank switching control circuit 2,103 register file 3,104 built-in RAM 4 bank size register 5,105 bank pointer register 6 old bank size register 7,106 old bank pointer register 8 data transfer count register 101 CPU internal control circuit

Claims (2)

[Claims] 1. A register file in which a register included in the register file is grouped, and saving and recovery of the register information is managed in group units, and a register file is provided via a dedicated bus. A storage device in which register information is saved and restored in group units, and information that specifies the registers used before or after restoration in group units and the registers used after or after restoration are grouped. Holds information specified in units of groups, determines the group of registers that are commonly used before and after saving or restoring the registers based on the retained information, and groups only the commonly used registers. Bank switching control means for saving or restoring in units, and the register file, the storage device, and the bank switching control means are formed on the same chip. Information processing equipment. 2. The registers used before and after saving or restoring are specified by the upper or lower register numbers used, and the number of registers used is the number of registers that can be saved and restored in one cycle time. The information processing apparatus according to claim 1, wherein the information processing apparatus is defined by an integral multiple of.