JPH0528416B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to microcomputer circuits, and more particularly to a novel configuration of serial input/output circuits integrated together with a CPU in one chip.

Prior Art A typical serial input/output circuit built into a microcomputer is configured as follows. That is, as shown in the attached Figure 2, a plurality of binary circuits corresponding to the number of bits of parallel data, such as delay flip-flop circuits, are connected in series like SR1, SR2, etc. When transferring data, first, one bit of parallel data to be transferred is input to each register via the parallel input/output circuit 2, and then the shift register circuit 1 The data stored in 1 is shifted 1 bit at a time toward the final stage of the shift register circuit, and the data at the final stage is serially output from the serial data output terminal 3.
Output to the outside of the CPU as data. The data shift at this time is configured to be performed in synchronization with a shift clock signal inputted from a clock signal input terminal 4 and inputted to the shift register circuit 1 via a shift clock control circuit 5. .

The shift register of such a serial input/output circuit is often
For example, for an 8-bit CPU, a shift register circuit consisting of 8 elements is incorporated.
One byte, or 8 bits, of serial/parallel conversion is considered to be one cycle of conversion/transfer.

Problems to be Solved by the Invention In recent years, with the expansion of the field of application of microcomputers, various serial data transfer systems have been developed and put into practical use. Therefore, a serial input/output circuit configured to perform conversion/transfer for each byte using a shift register that matches the word length of the CPU as described above is not efficient for various transfer methods. It may not be possible to respond well.

That is, for example, when transferring 1 byte (8 bits) of data with a microcomputer configured for 8 bits, there are cases where it is not always possible to transfer 1 byte of data in 1 cycle of conversion/transfer. . Hereinafter, the problems will be explained in detail using a serial input/output circuit configured for 8 bits as an example.

For example, as a method of confirming the accuracy of transferred data, it is widely practiced to add parity bits (redundant bits) to the transferred data before transferring the data. There are various types of parity, such as odd/even parity and horizontal/vertical parity, but in either case, it is common to add one or more bits of data as a parity bit to each byte.

However, when trying to transfer 1 byte of data with parity using a conventional 8-bit serial input/output circuit, for example, parallel/serial conversion/transfer must be performed in 8-bit units, so first 8 bits of data are transferred by cycle conversion, and when this serial transfer is completed, 8 bits of data consisting of 1 bit of parity data and 7 dummy bits are transferred again via the shift register circuit, and a total of 1 An operation is required to complete a serial data transfer of bytes. In other words, for 1 byte of data transfer, 2
Cycle conversion/transfer had to be performed.

Therefore, if you try to improve the reliability of transferred data by adding parity bits, the processing time will essentially double, and in addition, 7 dummy bits will be added for every 1 parity bit.
Data manipulation that is not originally required is required.

In addition, UART (Universal Asynchronous Serial Transmission/Reception) is widely used for transfer to relatively low-speed input/output devices.
A similar study will be conducted regarding the Receiver/Transmitter method).

Since the UART method performs asynchronous transmission and reception,
In this system, one cycle of transfer data consists of a start bit (1 bit) + transfer data + parity (1 bit) + stop bit (1, 1.5 or 2 bits).

Therefore, when using an 8-bit serial input/output circuit, at least two cycles of conversion must be performed to convert/transfer one byte of data, as in the case described above. On the other hand, to increase the efficiency of shift register use, dummy
If we try to avoid transferring bits, the data that can be transferred in one cycle of conversion will be 5 bits, which will reduce the amount of information that can be transferred per unit processing time, and the data that should be transferred in each cycle will have to be transferred every 5 bits. It is necessary to separate the data and input it to the serial input/output circuit.

Furthermore, in this method, in order to detect the start bit, it is necessary to keep the serial data external output line at a high level before starting data transfer. Therefore, in order to perform data transfer using the UART method using a conventional serial input/output circuit, data before starting data transfer and data for a stop bit must be set in a shift register, or Alternatively, it is necessary to take measures such as setting the serial data output terminal to a high impedance circuit and adding an external pull-up resistor before starting the transfer.

Above, we have described the problems of conventional serial input/output circuits regarding typical data transfer methods. However, with the recent development of microcomputer technology, the field of application has expanded, and many other methods have been developed and used in addition to the methods mentioned above. In many cases, a single microcomputer must support multiple systems, and there is a need for a highly versatile serial input/output circuit built into a microcomputer that can efficiently support any of the various systems. is being discussed.

Measures to solve the problem As mentioned above, in the conventional serial input/output circuit,
The input parallel data is directly output as serial data from the final stage of the shift register circuit. On the other hand, the problem when using the conventional serial input/output circuit described above to support various transfer methods is that data for different lengths of communication must be added to the transferred data depending on the various methods. This is due to the fact that

However, the length of each data added for transfer is usually about 1 to 3 bits, and does not have the same word length as the transfer data. The inventors of the present invention focused on this point, and by providing a latch circuit that can be controlled by software between the final stage of the shift register circuit and the output terminal of the serial input/output circuit, the data added to the transferred data is We have devised a method to increase the efficiency of use of the shift register by transfer data by adding it to the output data without going through the shift register circuit.

That is, the serial input/output circuit of the present invention includes a shift register circuit consisting of a plurality of series-connected binary element groups and a shift clock control circuit;
A serial input/output circuit comprising an input terminal for inputting parallel data to each binary element of the shift register circuit, and an output terminal for outputting data from the final stage of the shift register circuit to the outside of the microcomputer. and includes an output latch circuit that receives output data from the final stage of the shift register circuit and outputs the data to the output terminal, and an output latch control circuit that writes data directly to the output latch circuit. It is characterized by

Further, the writing of data to the output latch circuit by the output latch control circuit is configured to be controllable by software, and furthermore, the writing of data to the output latch circuit is controlled by the clock of the shift clock generation circuit. Advantageously, this is done synchronously with a pulse signal.

In other words, in the serial input/output circuit according to the present invention,
By providing a latch circuit that can be controlled by software between the final stage of the shift register and the output terminal of the serial input/output circuit, parity bits added to the data to be transferred can be adjusted according to various communication methods. Alternatively, various code bits can be added to the transferred data. Therefore, even if the word length of transfer data is increased depending on the communication method, the number of parallel/serial conversions during data transfer does not increase, and highly efficient data transfer can be achieved.

Embodiments The serial input/output circuit according to the present invention will be described in more detail below with reference to embodiments.
What is shown below is only one example of the present invention, and does not limit the technical scope of the present invention in any way.

FIG. 1a is a block diagram showing the basic configuration of the present invention. For convenience of explanation, the shift register in the figure is shown as an 8-bit shift register consisting of 8 elements, but it goes without saying that the present invention is not limited to this.

In the serial input/output circuit according to the present invention shown in the figure, like the conventional serial input/output circuit,
A shift register circuit 11 consisting of a binary circuit of eight elements SR1 to SR8, and this shift register circuit 1
1 and an output terminal 12 for outputting from the final stage to the outside of the microcomputer. In this serial input/output circuit, parallel data input from the internal bus 13 of the CPU to the shift register circuit 11 via the parallel input/output control circuit 14 is transferred from the first stage SR1 of the shift register to the final stage.
The data is shifted one bit at a time toward SR8, and sequentially output as serial data from the final stage of the shift register circuit 11. The shifting at this time is performed in synchronization with a clock signal input from the clock signal input terminal 15 and input to the shift register circuit 11 via the shift register clock control circuit 16.

In the serial input/output circuit according to the present invention, between the final stage of the shift register and the output terminal 12,
An output latch circuit 17 is provided, and the output latch circuit 17 is configured to be capable of writing arbitrary data by an output latch control circuit 18.

For example, when transferring 8-bit data with 1-bit parity, the serial input/output circuit according to the present invention takes the following steps.

First, 8-bit data to be transferred first is written into each element SR1 to SR8 of the shift register 11 via the internal bus 13 by the parallel input/output control circuit 14. This transfer data is transferred one by one according to the clock output from the shift register clock control circuit 16 in response to a serial transfer start command.
Bit by bit is sequentially transferred to the output latch circuit 17 and output from the serial data output terminal 12 to the external serial
Output to the data line. After the 8-bit data transfer is completed, the output latch control circuit 18 writes parity data into the output latch circuit 7, and outputs it from the output terminal 12 following the transferred data. Through the above series of operations, serial transfer of 8-bit data with parity added is completed.

At this time, if the data to be written to the output latch circuit 17 is either binary value "0" or "1", the output latch circuit and its control circuit should have a circuit as shown in FIG. 1b. can be used.

That is, in FIG. 1b, when the latch signal C is "0", the circuit 17 surrounded by the dotted line constitutes a latch circuit, and sequentially latches and outputs the signals from the shift register 11. Furthermore, when the latch signal C becomes "1", the shift register 11
The input from the write data signal B is blocked, while the input from the write data signal B is input to the output terminal 1 of the serial input/output circuit.
It is sent by wire to 2. At this time, write signal B is controlled by write control signal A.

In such a circuit, as a latch signal,
Using the shift clock signal, output terminal 12
Since the signal output from the converter is synchronized with the shift clock, the exact same signal that converts/transfers the dummy bits is used when 9-bit data is serially transferred using a conventional serial input/output circuit. It is output to the outside of the microcomputer without any interference.

Further, it goes without saying that such a circuit does not interfere with the function of the device according to the present invention as a conventional serial input/output circuit.

Next, consider UART-based transfer.

Since the UART method is an asynchronous transfer, it is necessary to keep the external serial data line at a high level before starting the data transfer in order to detect the start bit "0" on the data line at the start of the transfer. Therefore, in the serial input/output circuit according to the present invention,
The output latch control circuit allows this to be achieved by keeping the output latch circuit at a high level.

For the output latch circuit in this case, for example, a circuit as shown in FIG. 1C can be used.

That is, when the latch signal C is "0", the circuit indicated by reference numeral 17 functions as a latch,
The signal from shift register 11 is blocked.
Also, when the latch signal C is "1", the shift
The data from the register 11 is transmitted to the output terminal 12, but the output latch control circuit 18 outputs "1".
is input, “1” is output terminal 12
Output to.

Therefore, when communicating data using the UART method, the output terminal 12 is kept at a high level, that is, "1", by the output latch control circuit 18 before transmission, and the start bit "0" is written to the output latch circuit 17 at the start of transfer. , and then serially transfers the transfer data via the shift register, and finally writes "1" into the output latch circuit 17 again. All of these operations are performed in synchronization with the shift clock signal, and the output signals are completely equivalent to those output by the UART system using a conventional serial input/output circuit.

The above series of operations completes the transfer using the UART method.

As described above, in the serial input/output circuit according to the present invention, by writing appropriate data to the output latch circuit 17 by the output latch control circuit 18, the transfer data is converted from serial to parallel using the shift register circuit. Serial transfer,
Data added by various transfer methods can be serially added before and after the transfer data by the required number of bits by using the output latch circuit 17 and the output latch control circuit 18.

Note that each of the circuits mentioned here is only one example, and it is possible to write or maintain "0" or "1" in the output latch circuit.
Furthermore, the choice of circuit is not a limitation on the invention, provided that its writing can be synchronized with the shift clock signal.

Effects of the Invention As detailed above, in the microcomputer built-in serial input/output circuit provided by the present invention, an output latch circuit and this output latch circuit are newly added between the final stage output of the shift register and the serial output terminal. By providing an output latch control circuit that writes data to the circuit, and making it possible to add data directly to the output signal using software, you can use the shift register according to the word length of the CPU and Just by operating
It becomes possible to perform highly efficient transfer for various serial data transfer methods.

Further, the serial input/output circuit according to the present invention includes:
In addition to the methods mentioned above, it can support unknown methods that will be developed in the future, as well as special methods depending on the usage, without changing the hardware, making it extremely effective in expanding the scope of use of microcomputers. It is something.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the serial input/output circuit of the present invention, FIG. 1a is a block diagram of the serial input/output circuit of the present invention, and FIGS. 1b and 1c are FIG. 2 is a circuit diagram showing an example of an output latch control circuit of a serial input/output circuit according to the present invention. Further, FIG. 2 is a block diagram showing an example of a conventional serial input/output circuit. [Main reference symbols], 1, 11...Shift register circuit, 2, 14...Parallel input/output control circuit, 3, 12...Serial data output terminal,
4, 15...Clock signal input terminal, 5, 16...
...Shift clock control circuit, 13...Microcomputer internal bus, 17...Output latch circuit, 18...Output latch control circuit, A...Write control signal, B...Write data signal, C...Latch signal .

Claims (1)

[Claims] 1. A shift register circuit having first and second binary elements connected in series and a shift clock control circuit, inputting parallel data to the first and second binary elements of the shift register circuit. and an output latch circuit that receives data from the final stage of the shift register circuit and outputs the data to the output terminal, wherein the parallel data is output from the output terminal. The serial input/output circuit further comprises an output latch control circuit that directly writes binary data into the output latch circuit and outputs it from the output terminal after the data has been processed.