JPH05204848A - Serial communication system - Google Patents

Abstract

PURPOSE:To reduce the redundancy in address data transfer and to improve the transmission efficiency time of data by varying address length according to the state of a slave device. CONSTITUTION:In the serial communication system which transfers data among plural peripheral components 15A, 15B, 15C...15N connected to a microcomputer 1 through a serial bus 2, the number of bits of address information sent from the microcomputer 1 to the peripheral components 15A, 15B, 15C...15N through the serial bus 2 is hierarchically separated and varied. A slave device 15 which access addresses, assigned to the slave devices 15 from the CPU 1, frequently in the same system is given a short address number. Further, the slave device 15 which is low in use frequency is given a relatively long address number to improve the transmission efficiency of the data and the address length is freely varied according to the scale of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication system, and more particularly to a serial bus communication system connecting a microcomputer and peripheral components.

[0002]

2. Description of the Related Art A conventional microcomputer (hereinafter referred to as CP
Two transfer methods have been proposed for controlling an external input / output device or the like via an interface. One is a parallel communication system, and the other is a serial communication system. In the parallel communication system, if the data is 8 bits, it is transferred simultaneously by eight signal lines, but in the serial communication system, the transfer data is divided and transmitted every unit time. The serial communication system may or may not have a control signal line. In the absence, the start bit and stop bit are inserted in the data.

Various methods of these serial communication methods will be briefly described with reference to FIGS. 7 to 9.

FIG. 7 shows a synchronous serial communication system. Between the CPU 1 and other CPUs or peripheral devices such as a digital-analog converter (hereinafter referred to as D / A) and peripheral parts 3A, 3B. Is provided with one bidirectional data line 5, a clock line 6 and, if necessary, a control signal line 7. In this method, a reference signal is sent from the clock line 6 and data is transmitted from the data line 5 in synchronization with this reference signal.

FIG. 8 shows a serial communication system called M system. In this system, two data lines (for input / output) 7 are provided between the CPU 1 and a plurality of peripheral devices 3A, 3B. In addition to the clock line 6, each peripheral device 3A, 3B ...
It is necessary to pull out B ... 8N and send a selection signal to one of the peripheral devices 3A, 3B ... 3N accessed by the CPU 1 through these selection signal lines 8A, 8B ... 8N, and the peripheral devices 3A, 3B. There is a drawback that the selection signal lines 8A, 8B ... 8N increase in proportion to the number of 3N.

FIGS. 9A and 9B show the serial communication I ² C and IM bus systems. The I ² C bus system of FIG. 9A has a data line 5 and a clock line 6, but 8 bits are allocated as an address, and the CPU 1 transmits address data via the data line 6 before transmitting the data. Similarly, in the IM bus system shown in FIG. 9B, in addition to the data line 5 and the clock line 6, the address data identification line 9 for address data identification is provided, and the identification signal for address is transmitted similarly to the I ₂ C bus system. Be done. In each of these methods, the address length is a fixed bit, so the peripheral device 3A connected to the CPU 1
・ ・ ・ ・ ・ ・ When the number of 3N is small, there is a lot of waste, and conversely, 2 of 2 ⁸
You will not be able to control more than 56 peripherals.

[0007]

[SUMMARY OF THE INVENTION The serial communication system synchronous bus type described in the above configuration, a clock line, and requires external to the control line and the select signal lines of the data lines in the M bus system or the like, I ² C and In the IM bus, the address length is fixed, and because it is, for example, 8 bits, there is a limit on the maximum number of peripheral devices (hereinafter referred to as slave devices) connected to the CPU, and in the case of a small number, the address is wasted. Occurs. That is, when such an address is applied to a small-scale bus system, most of the addresses are not used, and there are many redundant parts, so that the clock signal (hereinafter C
In the data transmission supplied after the redundant address data transmission, the data transmission time is delayed by the time used for the redundant address data transmission.
There was a problem that wasted time increased.

On the other hand, when fixed-length addresses are used in a large-scale bus system, the addresses may run short.

The present invention provides a serial communication system that solves the above problems. The object of the present invention is to allocate a short address to a slave device that is frequently accessed and to use a slave device that is rarely used. It is configured such that a long address is assigned to the device and the address is made variable and transmitted.

[0010]

As shown in FIG. 2, the serial communication system of the present invention has a plurality of peripheral parts 15A, 15B connected to the microcomputer 1 via a serial bus 2. 15C ... In the serial communication system for exchanging data between 15N, a plurality of peripheral parts 15A, 15B, 15C from the microcomputer 1
The number of bits of the address information transmitted to the 15N via the serial bus 2 is hierarchically separated and variable.

[0011]

According to the serial communication system of the present invention, the slave device which is frequently used in the same system assigns a short address number to the slave device which frequently accesses the addresses assigned to a plurality of slave devices by the CPU 1. In contrast, a relatively long address number is given to improve the data transmission efficiency and the address length can be freely changed according to the scale of the system.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the system communication system of the present invention with reference to FIGS. 1 to 5, the overall configuration will be described with reference to FIG.

In FIG. 2, reference numeral 1 denotes a CPU, 15A. 15B, 1
5C ‥‥ 15N are each D / A, Analog - (hereinafter referred to as A / D) digital converters, parallel inputs (hereinafter referred to as P / S · REG) register for converting the serial output parallel serial input to parallel It is a register (hereinafter referred to as S / P.REG) for converting into an output, and data is supplied from the CPU 1 through an appropriate interface (I / F) (not shown) in the A / D 15B or the like.

2 is each D / A15A, A / D15B,
A serial bus for supplying address data and data from the CPU 1 to the slave device 15 such as P / S.REG15C ... S / P.REG15N.

FIG. 1 shows one slave device 15 and C described above.
FIG. 3 is a system configuration diagram with PU1, in which a slave device 15 is composed of, for example, a D / A 15A, an N-bit shift register 16 in the slave device 15,
It has a bit latch circuit 17, an N-bit comparison circuit 18, and a timing control circuit 19.

From the CPU 1, a clock signal (CLK),
Master data output signal (Master Data Ou
t: hereinafter referred to as MDO), slave data output signal (S
A control signal (hereinafter, referred to as CT) is supplied to the slave device 15 via the serial bus 2 as well as a slave data out (hereinafter, referred to as SDO).

That is, CLK is supplied in parallel to each digit of the shift register 16 via the switch 20. Further, it is supplied to the timing control circuit 19 and the clock terminal of the D / A 15A.

The MDO is a shift register 16 and a D / A.
It is supplied to the input terminal SI of 15A and the output of the D / A 15A is supplied from the output terminal SO of the D / A 15A to the CPU 1 through the line for SDO.

The CT is supplied to the latch circuit 17 and the timing circuit 19 through the CT line. The operation piece of the switch 20 is opened and closed by CT, and is turned “on” when CT is high (H) and is “off” when CT is low (L).

The output of each digit of the shift register 16 is supplied in parallel to the corresponding digit of the latch circuit 17, and the output of each digit of the latch circuit 17 is output to the corresponding digit of the comparison circuit 18. The slave address A is assigned to each digit of the comparison circuit 18.
₀ , A ₁ , A ₂ ... A _N-1 are given. Comparison circuit 18
Is supplied to the timing control circuit 19 and a chip enable signal (Chip Enable: CE
And a load signal (hereinafter referred to as load) are output and supplied to the respective input terminals of the D / A 15A for D / A.

The operation of the above configuration will be described with reference to FIGS.

Although N bits of address data bits are assigned to the shift register 16 and the latch circuit 17 as well as the comparison circuit 18 in the above configuration, the bit length (number) is a plurality of other slave devices 15, for example, A / D 15B, P / SR
EG15C ... S / P.REG15N and the like differ, and each slave device is assigned a unique address length. Therefore,
The number of digits (the number of bits) of the shift register 16, the latch circuit 17 and the comparison circuit 18 are determined according to the bit length of the address thus assigned.

When the CPU 1 sends the signals of each format shown in FIG. 3 to the slave device 15 in FIG.
While H is H, the switch 20 is turned on, CLK is supplied to the shift register 16 in parallel, and the addresses A ₀ , A ₁ , A ₂ transmitted from the CPU 1 by the MDO are transmitted.
... AN _-1 sequentially shifts in synchronization with CLK 16
Stored from higher digit to lower digit.

Next, when CT becomes "L", the switch 20
Is turned off and the N-bit address data stored in the shift register 17 is transferred to the latch circuit 17, further shifted to the comparison circuit 18, and the address data shifted to the comparison circuit 18 and the comparison circuit 18 are transferred. The supplied reference slave address data A ₀ , A ₁ , A ₂ ... A
A comparison with _N-1 is made.

When the comparison outputs of the comparison circuit 18 become equal, the comparison output 18A is supplied to the timing circuit 19 and CL
A control signal for controlling the D / A 15A is generated based on K and CT. That is, the inverted CE and Load are set to
5A and outputs the slave data as SDO from the SO to the CPU 1 via the SDC line. In addition, Loa
In consideration of the A / D 15B and the like, d is configured to take in data when reading into the shift register in the A / D and to generate a pulse after the data is fixed when writing.

The operation of the shift register 16 for the address data, the latch circuit 17, and the comparator circuit 18 will be described in more detail. D / A15A, A / D15B, P / S REG15C which are IC parts in the slave device 15 now.
Eight S / P / REG15N etc. are connected to the CPU1 via the serial bus 2 as the slave 1, the slave 2, the slave 3, and the slave 8 as shown in FIG. And

Addresses for operating the slave 1, slave 2, ..., Slave 8 for the above-mentioned slave device 15 are considered with 4 bits A ₀ , A ₁ , A ₂ , and A ₃ .

As shown in FIG. 4, in the slave 1 and the slave 8, the 2-bit shift register 16 of "00" and "11" is selected.

Further, in the slave 6 and the slave 7, "10
The 3-bit shift register 16 of "0" and "101" is selected.

Similarly, in slave 2, slave 3, slave 4, and slave 5, "0100", "0101", "0"
4-bit shift register 16 of "110" and "0111"
Select.

Then, depending on the frequency of use of the plurality of slaves 1 to 8 connected to the CPU 1, the slave device 15 having a higher frequency of use selects shorter address bits. That is, 2 bits are selected like slave 1 and slave 8. Hereinafter, it is assumed that the slaves 2 to 7 are selected according to the frequency of use.

For example, when CT is "H" as shown in FIG.
Address data A₀~ A₃To the shift register 16
Slave 1 and 8 have addresses of 3 bits or more
Even if data is input, as shown in FIG.₀And A₁of
I see only address data. Also, the longest bit number
The slaves 2 to 5 having the shift register 16 are
Figure when short address data of 3 bits or less is input
As shown in 5B, A ₀Shifts only the number of bits from
Secure in Dista 16.

In the slave 1 and the slave 8 having the shortest 2-bit shift register 16 as described above, for example, when A ₀ and A ₁ overlap with other slaves, there is a possibility that a plurality of slave devices will be in operation simultaneously. Therefore, as shown in FIG. 4, when A ₀ and A ₁ are “00” and “11”, A ₂ and A ₃ are determined not to come, and when A ₀ and A ₁ are “10”, A ₂ and A ₃ are _It is defined that "0" or "1" of 3 comes, and A ₀ A ₁ is "0".
When “1”, A ₂ and A ₃ are “00” “01” “10” “1”
1 "can be taken.

That is, the predetermined N-bit address length may be hierarchically selected so that the upper bits are selected to be the minimum m bits (2 bits) or more and the lower bits are allocated. For example, if N = 8 bits, the above 4 bits are set to "00".
00 "and" 1111 "are defined as the shortest address data, and the lower 4 bits are not added. When the above 4 bits are" 0001 ", 1 bit of the lower digit is added to make 5 bits of the address data of each slave. If the number of bits of the shift register 16 is determined and set, the inconvenience that a plurality of slaves 1 to 8 operate simultaneously does not occur.

As described above, each shift register 16 stores the data, the latch circuit 17 latches it, and the comparison circuit 18 compares the address data.
8A causes the timing control circuit 19 to output a control signal (CE signal and LOAD signal in FIG. 3) for operating the slaves 1 to 8 such as the D / A 15A to operate the slave device 15, and subsequently to transfer the D / A. Will be performed.

In the above-described embodiment, the slave device 15 has a plurality of independent D / A 15A, A / D 15B, P /
The case where the S.REG15C, ..., S / P.REG15N, etc. are operated by selecting a variable length address has been described, but the configuration shown in FIG. 6 can also function as a variable length address system.

That is, in FIG. 6, the slave devices 21A ... 21
N is a functional device select address for selectively operating the I / F 16A, and various parts connected to these I / F 16A ... 16N in a hierarchical structure, such as D / A 15A _1.
15A _n1 , A / D 15B _1, 15A _n2 , P / SR
EG15C ₁・ ・ ・ 15C _n3 , S / P REG15N ₁・ ・ ・
... 15N _nN etc. are selected so that the device address of the device to be operated is selected to a different address length.

That is, as shown in FIG. 6, for example, the slave device 21
A is one I / F 20A and D / A 15A _{1 to} 15A _n
Composed of.

To select the slave device 21A, the CPU 1 first sends an 8-bit address to the serial bus 2.

Next, an 8-bit address is input to the serial bus 2 to select one of the D / A's 15A _{1 to} 15A _n1.
To send to.

[0041] Thus, usually one device at 8 + 8 = 16 bits of the address D / A15A ₁ to 15A _n1 is selected.

As described above, when the I / F 16A is selected by 8 bits, the I / F 20A is valid until the other I / F 20B to 20N are selected.
D is the device after selecting
Only the 8-bit address that selects one of / A15A _{1 to} 15A _n1 needs to be transmitted. In this case the time shorter than simply to deliver 16-bit address since one can be selected in the D / A15A ₁ ~15A _n 8-bit address will be performed.

It is apparent that the same selection as described above can be made for the slave devices 21B to 21N.

Therefore, in the case of the configuration of the present invention, the shorter the address is assigned to the slave device that is frequently accessed, the transmission efficiency of the device is significantly improved, and the address length is increased according to the size of the communication system. Since it can be changed freely, it is possible to provide a highly scalable serial communication system.

[0045]

According to the present invention, a slave device that is frequently accessed is assigned a short address, and a slave device that is used less frequently is assigned a relatively long address. The transmission waiting time is shortened with the redundant address data, and the data transmission efficiency is improved. Further, since the address data length can be changed according to the system to be constructed, a serial communication system that increases the expandability when constructing the system can be obtained.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of a serial communication system of the present invention.

FIG. 2 is an overall system diagram showing an embodiment of a serial communication system of the present invention.

FIG. 3 is a transmission format and control signal waveform diagram of the serial communication system of the present invention.

FIG. 4 is an explanatory diagram of address allocation used in the serial communication system of the present invention.

FIG. 5 is an explanatory diagram of a relationship between a shift register used in the serial communication system of the present invention and an address length.

FIG. 6 is a configuration diagram showing another embodiment of the serial communication system of the present invention.

FIG. 7 is a configuration diagram of a synchronous bus system, which is one of conventional serial communication systems.

FIG. 8 is a configuration diagram of an M bus system, which is one of conventional serial communication systems.

FIG. 9 is a configuration diagram of an I ₂ C and IM bus system, which is one of conventional serial communication systems.

[Explanation of symbols]

 1 CPU 2 Address Bus 15 Slave Device 16 Shift Register 17 Latch Circuit 18 Comparison Circuit 19 Timing Control Circuit

Claims (1)

[Claims] 1. A serial communication system for exchanging data between a plurality of peripheral parts connected to a microcomputer via a serial bus, wherein the microcomputer communicates with the plurality of peripheral parts via the serial bus. A serial communication method characterized in that the number of bits of transmitted address information is divided into layers and made variable.