SU1203531A1 - Device for exchanging data between two computers - Google Patents

Description

The invention relates to computer technology and can be used in two computer systems for organizing inter-machine information exchange. 5

The purpose of the invention is to reduce the time of exchange of control information.

In FIG. 1 shows a structural ’diagram of the proposed device; in FIG. 2 is a block diagram of an address correspondence analysis unit; in FIG. 3 ~ block diagram of a block for generating exchange signals; in FIG. 4 is a structural diagram of the node issuing Rabo 15 and the subscriber; in FIG. 5 is a block diagram of a command receiving unit; nafig. 6 is a block diagram of a state byte issuing unit; in FIG. 7 is a structural diagram of an exchange control unit 20; in FIG. 8 is a structural diagram of a condition byte driver; in FIG. 9 is a block diagram of a signal conditioner subscriber requirement; in FIG. 10 is a structural diagram 25 of a single pulse shaper.

The device for exchanging data (Fig. 1) contains four nodes 1-4 of the amplifiers of the receivers, four nodes of 5-8 amplifiers of the transmitters, the first 9 and second 10 nodes of the formation of the address, the first 11 and second 12 nodes of the address comparison, the first 13 and second 14 switches , the first 15 and second 16 blocks of the formation of exchange signals and block 35 17 analysis of the correspondence of addresses.

Moreover, the inputs of nodes 1-4 are connected respectively to the information and control inputs 18-21 of the device, the outputs of nodes 5-8 to information ⁴⁰ and control outputs 22-25 of the device. The first control inputs of blocks 15 and 16 are connected respectively by buses 26 and 27 with the outputs of nodes 1 and 2, the first information inputs ^{45 by} buses 28 and 29 are with the outputs of nodes and 4, the inputs of the address recognition signal by circuits 30 and 31 are with the outputs of nodes 11 and 12 , the first control outputs with buses 32 and 33 - with inputs of ⁵⁰ nodes 5 and 6, the first information outputs with buses 34 and 35 - with the first inputs of switches 13 and 14, the second information outputs with buses 36 and 37 - with the second information 55 inputs of blocks 16 and 15 The output of node 9 is connected to bus 38 with a second information input of node 11 and a second input m of the switch 13, the output of which is connected by a bus 39 to the input of the node 7- The output of the node 10 is connected by a bus to the second information input of the node 12 and the second input of the switch 14, the output of which is connected by a bus to the input of the node 8. The first information inputs of nodes 11 and 12 are connected respectively buses 42 and 43 with the outputs of nodes 3 and 4. The first and second inputs of block 17 are connected respectively by circuits 44 and 45 with the outputs of nodes 8 and 4, and the first and second groups of inputs of block 17 with buses 46 and 47 with second groups of control outputs of blocks 15 and 16, its first and second outputs are circuits 48 and 49 ~ from the second with the inputs of the switches 13 and 14, the first and second groups of outputs with buses 50 and 51 - with the second groups of control inputs 15 and 16.

Block 17 analysis of the correspondence of addresses (Fig. 2) contains three registers 52-54, three delay elements 55-57, the first 58 and second 59 comparison nodes, the first 60 and second 61 dynamic triggers, the first 62 and second 63 elements And, the first 64 and the second 65 elements are NOT, a single pulse shaper 66, an OR element 67 and a switch 68, the output of which is connected to the information input of the register 52. Moreover, the output of the register 52 is connected to the first inputs of the nodes 58 and 59, the circuit 48 with the first and the circuit 49 with the second the outputs of the unit, the first and second inputs of which are connected respectively by circuits 44 and 45 to the information inputs of the registers 53 and 54. The output of the register 53 is connected to the second input of the switch 68 and the second input of the node 58, the output of which is connected to the first circuit 69 of the bus 50, connected to the first group of outputs of the block. The output of the register 54 is connected to the first input of the switch 68 and the second input of the node 59, the output of which is connected to the first circuit 70 of the bus 51 connected to the second group of outputs of the block. The first circuit 71 of the bus 46 connected to the first group of inputs of the block is connected to the clock inputs of the register 53 and the trigger 60, the single output of which is connected to the first inputs of the elements 62 and 67, the first control input of the switch 68, the second circuit 72 of the bus 50 and the third circuit 72 g

bus 51. The first 73 circuit of bus 47 connected to the second group of inputs of the block is connected to the clock inputs of register 54 and trigger 61, the single output of which is connected to the second inputs of elements 62 and 67, the second control input of switch 68, the second circuit 74 of bus 51 and third a circuit 74 of the bus 50. The second circuit 75 and 76 of the bus 46 and 47 are connected respectively to the zero input of the trigger 60 and the first zero input of the trigger 61. The output of the element 62 is connected via the delay element 55 and the driver 66 to the second zero input of the trigger 61 and through the element 64 with the first input of element 63, WTO 56 whose second input connected to the output of delay element. The output of element 67 through delay elements 56 and 57 and element 65 is connected to the third input of AND 63, the output of which is connected to the clock input of register 52. The zero output of trigger 60 is connected to the information input of trigger 61, the zero output of which is connected to the information input of trigger 60.

Block 15 (16) for generating exchange signals (Fig. 3) contains a node 77 for issuing a signal, a subscriber operation unit 78, a status byte unit 79, an exchange control unit 80, an instruction decoder 81, a command register 82, a comparison unit 83, a shaper 84 status bytes and a signal driver 85. A subscriber's demand, the inputs of which are connected respectively by buses 86-88 and the first circuit 89 (90) of bus 37 (36) with the first outputs of nodes 77, 79 and 80 and the second information group of the block inputs. From the first to the fourth outputs of the shaper 85 are connected respectively by circuits 91 and 92, a bus 32 (33) and a circuit 93 (94) with the first inputs of the node 77 and the shaper 84, the first output of the block and the second circuit of the bus 36 (37) connected to the second group information outputs of the block, the first group of control inputs of which is connected to the second input of the node 77 by the bus 26 (27) and the first inputs of the nodes 78-80. The first group of information inputs of the block bus 28 (29) is connected to the first input of the decoder 81 and the third circuit of the bus 36 (37). Block address recognition signal input circuit

1203531 *

30 (31) is connected to the third input of node 77. From the second to fourth outputs of node 77 are connected respectively by bus 95, circuits 96 and 71 (73) g; with the second input of node 78 and the first bus circuits 34 (35) and 46 (47), respectively connected to the first corpse of information and the second group of control outputs of the unit, the second group of control inputs of which is connected by bus 50 (51) to the third input of node 78 and the second input of the node 79. The outputs of the node 78 are connected respectively by circuits 97, 99, 100 and a bus 98 with a quarter ™ input of the node 77, the third input of the node 79, the second input of the decoder 81 and the clock input of the register 82, the output of which is connected to bus 101 (102) with the second input 2θ of the node 80, the first input of the node 83 and the fourth circuit of the bus 36 (37). From the second to the seventh outputs of the node 79 are connected respectively by a circuit 103, a bus 104, circuits 105, 75 (76) and

90 (89) and bus 106 with the fifth input of node 77, the third input of node 80, the second bus circuit 34 (35), the second bus circuit 46 (47), the first bus circuit 36 (37), and the second input the driver 84, the output of which is connected to the third circuit 107 of the bus 36 (35). The second to fourth outputs of the node are connected respectively by bus 108, circuit 109 and bus 110 (111) to the fourth input of node 79, the fourth bus circuit 34 (35) and the fifth bus circuit 36 (37). The fourth 102 (101), fifth 111 (110) and third 29 (28) bus circuits 37 (36) are connected respectively to the second input of node 83, ^{40, the} fourth input of node 80 and the fifth bus circuit 34 (35). The output of the decoder is connected to the information input of the register 82. The output of the node 83 circuit 112 is connected to the fourth input of the node 78.

⁴⁵ The second circuit 94 (93) of the bus 37 (36) is connected to the fifth input of the node 80.

The signal output unit 77 The subscriber’s operation (Fig. 4) contains triggers 113-117, formers 118-121 for night pulses, AND 122125 elements, the first 1.26 and the second 127 HE elements and the OR element 128, the output of which is connected to the first the input of element And 122 and the first circuit 129 of the bus 55 86 connected to the first output of the node. Moreover, the first input of the node circuit 91 is connected to the first input of the element And 123, the output of which through the shaper 118 is connected to a single input of the trigger 113. The first circuit 130 of the bus 26 (27) connected to the second input of the node is connected to the first input of the element And 124, the second input of the element 123 and through the element HE 126 with the first input of the AND element 125, the output of which through the former 119 is connected to the single input of the trigger 114 and the circuit 71 (73) with the fourth output of the node. The second circuit 131 of the bus 26 (27) is connected to the second input of the AND element 125 and through the element NOT 127 with the third input of the And element 123 and the second input of the And element 122-, the output of which through the former 121 is connected to the unit inputs of the triggers 116 and 117. The third and the fourth inputs of the node are connected respectively by circuits 30 (31) and 97 with the third input of the And element 125 and the zero input of the trigger 116, the output of which is connected by a circuit 96 to the second circuit of the bus 86 and the third output of the node. The fifth input of the node circuit 103 is connected to the zero inputs of the triggers 113, 114, 115 and 117, with the third circuit of the bus 86 and the first circuit of the bus 95 connected to the second output of the node. The output of the trigger 113 is connected to the second circuit 132 of the bus 95 and the first input of the OR element 128, the second input of which is connected to the output of the trigger 115. The output of the trigger 114 is connected to the second input of the element And 124, the output of which is connected via the former 120 to the single input of the trigger 115. The output the trigger 117 is connected to the third circuit 133 of the bus 95.

The node 78 receiving commands (Fig. 5) contains, triggers 134-137, shapers 138-141 single pulses, elements AND 142-148, elements NOT 149152, first 153 and second 154 delay elements, first 155 and second 156 OR elements, outputs which are connected through the corresponding formers 138 and 139, respectively, with a single input of the trigger 134 and the input of the delay element 153. The output of the delay element 153 is connected to a single input of the trigger 135 and circuit 97 with the first output of the node. The third circuit 74 (72) of the bus 50 (51) connected to the third input of the node is connected to the first inputs of the elements And 142 and 143 and through the element NOT

149 with the input of the And element 144. The third circuit 157 of the bus. 26 (27) connected to the first input of the node is connected to the first input of the And element 145, the output of which is connected to the first inputs of the And elements 146 and 147. The first circuit 103 of the bus 95 connected to the second input of the node, connected to the zero inputs of the triggers 134-137. The second circuit 132 of the bus 95 is connected to the second input of the AND element 146 and through the element NOT 150 to the second input of the AND element 147, the output of which through the former 140 is connected to the single input of the trigger 136, the second input of the And element 144 and then through the delay element 154 by the circuit 100 s fourth node output. The third circuit 133 of the bus 95 is connected to the second input of the AND element 145. The output of the trigger 136 is connected to the first inputs of the elements 148 and 156, the second inputs of the elements And 142 and 143 and the circuit 99 with the third output of the node. The first circuit 69 (70) of the bus 50 (51) is connected to the third inputs of the elements And 142 and 143 and through the element NOT 151 to the second input of the element And 148. The zero output of the trigger 135 is connected to the fourth inputs of the elements And 142 and 143 and the third inputs of the elements And 146148. The single output of the trigger 135 is connected to the first circuit 158 of the bus 98 connected to the second output of the node. The second 159 and third 160 bus bus circuits 98 are connected respectively to the outputs of the triggers 134 and 137. The fourth input of the node circuit 112 is connected to the fifth input of the AND element 143 and through the element NOT 152 to the fifth input of the AND element 142, the output of which is connected to the first input of the element OR 155. The output of the AND element 143 through the former 141 is connected to the first single input of the trigger 137, the second single input of which is connected to the output of the And element 144. The outputs of the And elements 146 and 148 are connected, respectively, to the second inputs of the OR elements 156 and 155.

ι

The node 79 issuing the status byte (Fig. 6) contains triggers 161-166, shapers 167-171 single, pulses, elements AND 172-1 78, elements NOT 179-183 and elements OR 184187. Moreover, the first bus circuit 130

120353 V

26 (.27) connected to the first input of the node is connected through the element NOT 179 to the first input of the AND element 172, the output of which is connected to the first circuit 188 of the bus 87 connected to the first output of the node. The third circuit 157 of the bus 26 (27) is connected through the element 180 to the first input of the element And 173, the output of which through the former 167 is connected to the single input of the trigger 161. The fourth circuit 189 of the bus 26 (27) is connected to the first input of the element And 174 and through the element NOT 181 with the second input of the element And 173 and the first inputs of the elements And 175-177, the second inputs of which are connected to a single output of the trigger 162. The second circuit 72 (74) of the bus 50 (51) is connected to the first input of the element And 178, the output of which is the circuit 90 (89) is connected to the sixth output of the assembly. The second _and third circuit of the bus 98 connected to the third input of the node are connected respectively to the first and second circuit of the bus 106 connected to the seventh output of the node, the second and fifth outputs of which respectively are connected by the circuits 103 and 75 (76)> to the output; element OR

184. The first circuit 158 of bus 98 is connected to the first input of the OR element

185, the second input of which through the first circuit 190 of the bus 108 is connected to the fourth input of the node. The second circuit 159 of the bus 98 is connected to the third input of the AND element 176 and through the element NOT 182 to the third input of the AND element 1 77. The third circuit 160 of the bus 98 is connected to the third input of the element

And 175 and through the element NOT 183 with the fourth inputs of the elements AND 176 and 177. The second circuit 191 of the bus 108 is connected to the single input of the trigger 164 and the first input of the OR element 186, the output of which is connected to the single input of the trigger 165. The output of the trigger 161 circuit 105 is connected to the fourth node output, the second bus circuit 87 and the second input of the element And 174, the output of which through the former 168 is connected to the zero input of the trigger 161 and the single input of the trigger 162. The zero output of the trigger 162 is connected to the third input of the And 173, the fourth and fifth inputs of which are connected respectively only with the output of the OR element 185 and the zero output of the trigger 166. The output of the And 175 element through the former 169 is connected to the single input of the trigger 166, the second input of the And 178 element and the first input of the OR element 187, the output of which is connected to the zero input of the trigger 162. The output of the And element 176 through the former 170 is connected to the first input of the OR element 184, the second inputs of the OR elements 186 and 187 and the single input of the trigger 163, the output of which is connected to the second input of the AND element 172. The output of the And 177 element through the former 171 is connected to the third input of the OR element 18 7, the second input of the OR element 184, the zero inputs of the triggers 163-166 and the first circuit 192 of the bus 104 connected to the third output of the node. The outputs of the triggers 164 and 165 are connected respectively to the third 193 and fourth 194 circuits of the bus 106. The single output of the trigger 166 is connected to the second circuit 195 (196) of the bus 104.

The exchange control unit 80 (Fig. 7) contains triggers 197-202, single pulse shapers 203-208, AND elements 209-219, OR elements 220-223, the first 224 and the second 225 elements NOT. Moreover, the fourth circuit 189 of the bus 26 (27) connected to the first input of the node is connected to the first inputs of the elements And 209 and 210 and through the element NOT 224 with the first inputs of the elements And 211 and 212. The third circuit 157 of the bus 26 (27) is connected to the first the inputs of the elements And 213 and 214, the outputs of which are connected respectively to the first and second input of the OR element 220. The first circuit 226 of the bus 101 (102) connected to the second input of the node is connected to the first input of the element And 215, the output of which is connected to the first input of the element OR 221. The second circuit 227 of the bus 101 (102) is connected to the first input of the AND element 219. B the course of the AND 219 is connected to the first input of the OR. 222, the output of which through the former 203 is connected to the first zero inputs of the flip-flops 197 and 198, the second circuit 191 of the bus 108 connected to the second output of the node, and the single input of the trigger 199, the output of which is connected to the first circuit 190 of the bus 108. The third circuit 228 of the bus 101

(102) is connected to the first input of AND element 216, the output of which is connected through the form of a punch 204 to a single input of the trigger 197. The second circuit 195 (196) of the bus 104 connected to the third input of the node is connected to the first circuit of the bus 110 (111) connected to the fourth output of the node, and the first input of the element And 217, the output of which 1 is connected to the second inputs of the elements And 215 and 216. The first circuit 192 of the bus 104 is connected to the first zero inputs of the triggers 200 and 201 and the zero inputs of the triggers 199 and 202. First 1

196 (195), the second 229 (230) and the third 231 (232) circuit of the bus 111 (110) connected to the fourth input of the node are connected respectively to the second input of the element And 217 and the third ²¹ inputs of the elements And 215 and 216. The fourth circuit 233 (234) 111 bus (110) connected to a first input of aND gate 218, whose output is connected through a driver 205 with a single house ² vho- latch 200 and second latch 198. The zero input of fifth circuit 235 (236) 111 bus (110) coupled to the second input of the OR element 222 and through the element NOT 225 with the second inputs 3 (the elements And 211 and 212. The fifth input of the node circuit 94 (93) is connected to the second input I 219. The trigger output is 197. 109 is connected to the third output of the node, the second inputs are 35 of the And 209 and 213 elements and the first input of the OR element 223, the output of which is connected by bus 88 to the first output of the node.The output of the trigger 198 is connected to the second the inputs of the elements 40 AND 210, 214 and the OR element 223. The output of the trigger 200 is connected to the third input of the AND 211 element, the output of which is connected to the second input of the OR element 221. The output of the trigger 201 45 is connected to the fourth circuit 234 (233) of the bus 110 ( 111) and the third input of the element And 212, the output of which through the former 206 is connected to the second zero trigger input 201. Zero 50 output of trigger 202 is connected to the second circuit 230 (229) of bus 110 (111). The output of the element And 209 through the shaper 207 is connected to the second zero input of the trigger 197 and the unit inputs 55 of the triggers 201 and 202. The output of the element And 210 is connected to the second input of the element And 218 and the third circuit 232 (231) of bus 110 (111). Output OR

220 is connected to the third input of the OR element 222 and the fifth circuit 236 (235) _{5 of the} bus 1.10 (111), the Output of the OR element

221 is connected through a former 208 to a single input of a trigger 198 and a second 'zero input of a trigger 200.

Shaper 84 of the status byte (Fig. 8) contains the AND 237-240 elements and the HE 241 element. Moreover, the first input of the node by the circuit 92 is connected to the first input of the And 237 element, the output of which is connected to the first circuit 242 of the bus 107 connected to the node output. The first 159, third 193, and fourth 194 circuits of the bus 106 connected to the second input of the driver are connected respectively to the first inputs of the elements And 238-240, the outputs of which are connected respectively to the circuits 243-245 of the composite circuit 107. The second circuit 160 · bus 106 through element is NOT 241 connected. yen with second inputs of elements

5. And 237-240.

Shaper 85 of the signal The subscriber's request (Fig. 9) contains a trigger 246, an AND element 247, an OR element 248, and an element NOT 249. Moreover, 5, the first circuit 129 of the bus 86 connected to the first input of the shaper is connected to the first circuit of the bus 32 (33), connected to the third output of the shaper, and through the element; NOT 249 with the first entry of an element

And 247, the output of which is connected by a circuit 91 to the first output of the driver and the second circuit of the bus 32 (33). The second circuit 96 of the bus 86 is connected to | the third circuit of the bus 32 (33). The third circuit 103 of the bus 86 is connected to the first zero input of the trigger 246, the single output of which is connected by the circuit 92 to the second output of the driver and the first input of the OR element 248. The first circuit 188 of the bus 87 connected to the second input of the driver is connected to the second input of the OR element 248, the output of which is connected to the second input of the element And 247. The second circuit 105 of the bus 87 is connected to the fourth circuit of the bus 32 (33). The third input of the shaper circuit 88 is connected to the fifth circuit of the bus 32 (33) and the second zero input of the trigger 246. The fourth input of the shaper circuit 89 (90) is connected to a single input of the trigger 246, the zero output of which 1 1st circuit 93 (94) is connected by the fourth output of the shaper .

The single pulse shaper (Fig. 10) contains, for example, AND element 250, element NOT 251 and delay element 252. Moreover, the input of the shaper is connected to the input of the delay element 252, the first and second outputs of which are connected respectively to the first and through the element NOT 251 with the second inputs of the I 250 element. The output of the And 250 element is connected to the output of the shaper.

The device operates as follows.

Inputs 18 and 20 and outputs 22 and 24 of the device are connected to the first computer, inputs 19 and 21 and outputs 23 and 25 to the second computer. Based on the codes generated by the nodes 9 and 10, the proposed device allows you to access the first computer from one of the address groups, starting from address 10010000, and ending with address 1001111, and the second computer, respectively, from address 10100000 to 10101111. Further, to reduce records binary records binary codes are written in hexadecimal codes.

The work of the proposed device, as well as the well-known ^ is possible only in the system: one computer - the device is the second computer. The proposed and well-known devices require coordinated actions from two computers. Any information transmitted through the adapter has a specific direction of transmission and its specific purpose. The direction of information transfer is determined by the type of command, and the purpose of the information is determined by the value of the bits of the command modification. To solve these problems, each of the computers has special programs. In a system with a known adapter, these programs solve the indicated problems after receiving the command code in response to the Refine command byte command. In the system with the proposed device, these programs are based on address correspondence tables with commands for accessing the device. So, for example, the program in the first computer has the following correspondence table: the address 90 ^ _b corresponds to the Write command with code C) ₁₆ in the modification bits; ^{j to} address 9¼ Write command with the code at address 1203531 12 sou 92 ^ - write command with the code 2 ^; address 93 ₁₆ - Write command with code 3 _ίέ,; address 94 ₄ & command Read with code 0 ₄ b; ade pety 95 _ife - command Read from.

code 1 ₁₆ ; address. 96 _1b - command ^ Read with code 2 _<6 ; address 97 ₁₆ command Read with code 3 ₁₆ ; address 98 _<6 - command 10 with the code O. _{! 6} for the second computer; address 99 ^ _6th command Command with code 1 ₁₆ - · for the second computer; address 9A; ₆ Management command with code 2 _1b for the second computer; address 9B _{46 -} command 15 yes Management with code 3 ₁₆ for the second computer; address 9C _1b - Management command with code 0 _4fc , from the second computer; address 9D ^ -``command 'Management with code 1 ₁₆ from the second computer;

address 9Ε _ί6 - _h team management code 2 _ί6 from the second computer; address 9G _4b - command. Management. with code 3 _d6 from the second computer;

The program in the second computer in this case has the following correspondence table: the address A0 ₁₆ corresponds to the Read command with code O ₅₆ in the modification bits; address A1 ^. - command Read with code 1 _1t> ; address 30 A2,] _fe - command Read with code 2 to address A3 _{4 &} - command Read with code 3 _ί6 ; address - A4 ^ '- command

Write with code 0 ₄₆ ; address A5 (^ Write command with code; address A6 ,, - command Write ³⁵ p ' ⁶ * with code 2 ^; address A7 _{4 &} - command

Write with code 3 ^ ₆ ; to the address Αδ ^^ 'com'anda Management with code 0 _L6 - from.

'first computer; address A9- (b ~ command Management with code 1 _4b from the first computer; address AA.j $ - command Management with code 2 | _b from the first computer; address AB ₁₆ - command Management 'with code 3 ₄₆ - from the first computer; address $ 5 AC _i6 command Management with code for the first computer; address адресуΛγθ “command Management with code 1 _ifc for the first computer; address AE ₁₆ - command Management with code 2 _{46 50} for the first computer ;, address AG ^ - - command Management with code 3 ₍₆ for the first computer, suppose that during the operation of the first computer there is a need to transfer an array of information to the second

COMPUTER. The purpose of this information corresponds to code 3 ₁₆ in the modification bits of the command. The program of the first computer organizing the exchange through the device determines that it is necessary to issue the command Write ^μ with the code 3 ^ ₆ in the modification bits of the command to the device, and on the basis of the table described it displays it at 93 _4e? .

The device receives this address at input 20 (Fig. 1), and at input 18 through node 1 and then through circuit 26, an identification signal is received from block 1.5 to block 1.5. The high order bits of the received address through node 3 and further along circuit 42 are transferred to node 11, where the data of the address bits is compared with the device’s own address, which is set by node 9. At the same time, the lower order bits of the received address from the output of node 3 are sent via chain 44 to block 17 on information input register 53 (Fig. 2).

Since the high order bits of the received address (code 9 ₁₆ ) correspond to the device address (code 9 ₁₆ ), the node 11 (Fig. 1) generates an address recognition signal in circuit 30. Based on this signal and the Address signal from the channel received through the circuit 131 (Fig. 4) from the bus 26, the And element 125 of the node 77 (Fig. 3) of the block 15 (Fig. 1) generates a single level, on the leading edge of which the shaper 119 (Fig. 4) produces a single pulse as follows. When applying to the input of the shaper of a single level, similar levels appear first on the first and then on the second outputs of the delay element 252 (Fig. 10). Since the appearance of these levels is spaced in time, unit inputs are present for some time at the inputs of the And 250 element, which means that a unit level is established at its output and the output of the shaper. By the end of the total leading edge delay time, the unit level from the second input of the delay element 252 after the element HE 251 inverts the zero level to the second input of the AND element 250, which then stops outputting the unit level to the output of the driver. So, on the leading edge of a single level entering the input, the shaper produces a single pulse. All other single pulse shapers work in a similar way.

Formed by the shaper 119 (Fig. 4), the pulse sets the trigger state to a single state 114 and enters block 17 (Fig. 1) along the circuit 71 from the bus 46 (Fig. 3). Where <he enters the least significant bits of the address (code 3 ^ ₆ ) into register 53 (Fig. 2) and sets trigger 60 to unity, since the input level receives a single level from the zero output of trigger 61, which is in the original, zero condition. After that, the unit level from the single output of the trigger 60 allows the contents of the register 53 to pass through the switch 68 to the information input of the register 52, and also enters through the OR element 67, then through the delay element 56 to the second input of the And 63 element, at the first and third inputs of which this time unit levels are present. At the second input, the unit level comes after inverting the zero level from the output of the AND element 62, blocked by the zero level from the single output of the trigger 61. At the third input of the And 63 element, the unit level has a certain time equal to the delay time of the leading edge of the unit level in the delay element 57. As a result of this, the And 63 element generates a signal which enters into the register 52 a 3 ^ ₆ code received at its information input. The delay element 56 provides a signal from the output of the And 63 element by the time the specified code arrives at the information input of the register 52. After that, the same codes 3 arrive at the inputs of the node 58; ₆ , and he determines their equality and along the chain 50 gives a unit level.

The next step in the initial sampling is the input through input 18 (Fig. 1) through node 1 via bus 26 and then to node 77 (Fig. 3) of block 15 (Fig. 1) through circuit 130 (Fig. 4) to the first input of element And 124 signals Sampling from the channel. The second input of this element receives a single level from the output of the trigger 114. As a result, the element And 124. gives a single level, on

120353t the basis of which the driver 120 generates a single pulse. This pulse sets the trigger 115 to a single state. The unit level from the output of this trigger through the 5th element OR 128 is fed to the input of the And 122 element and through the circuit 129 of the bus 86 (Fig. 3) to the former 85, where the subscriber works through the node 32 (Fig. 9) through the node 10 5 (Fig. 1) and then exit 22 to the first computer.

Next, the node 77 (Fig. 3) of block 15 monitors the reset signal Address from the channel using elements 122 and 127 (Fig. 4). After resetting the signal Address from the channel, the element NOT 127 produces a unit level, which is fed to the second input of the element, And 122. The first input of this element has already received a single level from the output of the OR element 128. The element And 122 forms the unit level at which the shaper 121 produces a single pulse. This pulse sets the triggers 116 and 117 to a single state. A single level from the output of the trigger 116 through the circuit 96 from the bus 34 (Fig. 3) enters the switch 13 (Fig. 1). Based on this level, the switch 13 outputs the code 9 ^ ₆ generated by the node 9, as the upper bits of the address code, and as the lower bits of the address code, the 3 ^ ₆ code, which arrives on ³⁵ circuit 48 from register 52 (Fig. 2) of the block 17 (Fig. 1). The code 93 ₁₆ compiled in the manner described at the output of the switch 13 via circuit 39 through node 7 at output 24 as a device address code 40 is transferred to the first computer. At the same time, the specified level from the output of the trigger 116 (Fig. 4) through the circuit 96 from the bus 86 enters the former 85 (Fig. 3), where on the bus 32 (Fig. 9) and 45 then through the node 5 (Fig. 1) output 22 as an accompanying device address address code signal. The address from the subscriber enters the first computer. A single level from the output of the trigger 117 (Fig. 4) ⁵⁰ along the circuit 133 of the bus 95 enters the node 78 (Fig. 3) and connects it to work.

The next step in the initial sampling is the receipt by the device of the first computer command. The command code for 55 input 20 (Fig. 1) through the node 3 and then on the circuit 28 is supplied to the first input of the decoder 81 (Fig. 3) of block 15 (Fig. 1). This command code accompanies the control signal from the channel, which, at the input 18 through the node 1 and then on the bus 26, enters the block 15. The control signal from the channel through the circuit 157 (Fig. 5) of the bus 26 receives in node 78 ( Fig. 3) element And 145 (Fig. 5), which by this time is connected to work by a single level on the circuit 133 of the bus 95 from the output of the trigger 117 (Fig. 4) of the node 77 (Fig. 3). As a result of this, the unit level from the output of the element And 145 (Fig. 5) goes to the first input of the element And 147. The second input of this element receives the unit level after the element HE 150 inverts the zero level received by the node 78 through the circuit 132 of the composite circuit 95 from the output located in the initial (zero) state of the trigger 113 (Fig. 4) node 77.

On the. the third input of the element I. 147 (Fig. 5) receives a single level from the zero output of the trigger 135 located in the initial (zero) state. Based on these levels, the element And 147 gives a single level, according to which the shaper 140 generates a single pulse. The . the pulse sets the trigger 136 to a single state and after the passage of the And 144 element, the trigger 137. The passage of this signal through the And 144 element provides a single level that goes to the first input of the And 144 element after the element NOT 149 inverts the zero level received through circuit 74 of the bus 50 s the output is located in the initial zero state of the trigger 61 (Fig.2) of the node 17 (Fig. 2).

A single level from the output of the trigger 136 (Fig. 5) enters the circuit 99 to the second input of the decoder 81 (Fig. 3) and connects it to work. The result of decryption of the received command is fed to the information input of the register 82. A single pulse from the output of the driver 140 (Fig. 5) through the delay element 154 and then along the circuit 100 is fed to the clock input of the register 82 (Fig. 3) and enters the result of the decryption of the command into the register. The decoded command from the output of the register 82 is supplied to the first input of the node 83, to the second input of the node 80 through the circuit 101 of the composite circuit 36 (Fig. 1), to the second input of the node 83 ί8 (Fig. 3) of the block 16 (Fig. 1). In addition, a single level from the output of the trigger 136 (Fig. 5) enters through the 'OR element 156 to the input of the shaper 139, which forms a single pulse through it. This pulse after the delay in the delay element 153 sets the trigger 135 and enters the circuit 77 into the node 77 (Fig. 3) where it resets the trigger 116 (Fig. 4). Resetting the trigger 116 means stopping the device issuing to the first computer using the switch 13 (Fig. 1) on the circuit 39 through the node 7 on the output 24 of the address code and using the shaper 85 (Fig. 3) on the circuit 32 (Fig. 1) and further through node 5 on the output 22 signal Address from the subscriber. With the installation of trigger 135 (Fig. '5), the unit level from its single output via circuit 158 from bus 98 enters node 79 (Fig. 3) and connects it to work. The last step in the initial sampling is the delivery of a status byte to the first computer. This work in the device performs the node 79 of the block 15 (Fig. 1). The single level from the output of the trigger 135 (Fig. 5) through the circuit 158 of the bus 98 in the node 79 (Fig. 6) enters through the element OR 185 to the fourth input of the element And 173. The third and fifth inputs of this element receive unit levels from the zero outputs of in the initial (zero) state, respectively, of flip-flops 162 and 166. The second input of the And 173 element receives a single level from the output of the element NOT 181, since it is input to circuit 189 of bus 26 and then through node 1 (Fig. 1) at input 18 the signal from the channel is not coming from the first computer. In this state, the And T73 element (Fig. 6) monitors the control signal reset from the channel, which is received from the first computer at input 18 (Fig. 1) through node 1 along component circuit 26 and then in block 15 to node 79. In this the node named signal on the circuit 157 (Fig. 6) through the element NOT 180 is fed to the first input of the element And 173.

After resetting the control signal from the channel, the element NOT 180 forms a unit level, as a result of which at all the inputs of element Y 173 there are unit levels, on the basis of which it outputs a unit

7 'level. At this level, the driver 167 generates a single pulse, which is set by the trigger 161. The single level from the output of the trigger 161 along the circuit 105 of the bus 34 (Fig. 3) enters the switch 13 (Fig. 1) and allows the transfer of the status byte, which forms the driver 84 ( Fig. 3). In this case, the specified driver on the circuit 160 (Fig. 8) of the bus 106 receives a single level from the output of the trigger 137 (Fig. 5) of the node 78 (Fig. 3). In the former, the described level after inverting by the element NOT 241 is supplied to the second inputs of the elements And 237-240 and blocks their operation. As a result of this, these elements, respectively, along the circuits 242245 of the bus 104, which in turn enters the bus 34 (Fig. 3), give zero levels to the switch 13 (Fig. 1). This means that the switch 13 by. circuit 39 through node 7 at output 24 produces a status byte from one zeros. At the same time, a single level from the output of the trigger 161 (Fig. 6) along the circuit 105 of the bus 87 enters the former 85 (Fig. 3), where without conversion via the bus 32 (Fig. 9) through the node 5 (Fig. 1) at the output 22 is transmitted to the first computer as an accompanying status byte signal Management from the subscriber.

After that, the node 79 (Fig. 6) enters the standby state of the response signal from the first computer. This signal will be the Information signal from the channel, which is input 18 (Fig. 1) through node 1 via bus 26 to block 15 and informs it of the receipt of the status byte. In block 15 (Fig. 3), this signal enters node 79, where, through circuit 189 (Fig. 6), element I 174 is connected to operation. The second input of this element receives a single level from the output of trigger 161. As a result, element And 174 gives a single level at which the shaper 168 generates a single pulse. This pulse resets the flip-flop 161 and sets the flip-flop to one state 162. The zero level from the zero output of the trigger 162 blocks further operation of the cell 1 and 73. A single layer with a single output latch 162 is supplied to the second inputs of AND gates 175 ~ 177 _(. After resetting the flip-flop 161 the switch 13 (Fig. 1) on the circuit 39 through the node 7 and then on the output 24 stops issuing the status byte to the first computer, and the former 85 (Fig. 3) on the circuit 32 through the node 5. (Fig. 1) and then on the output 22 - control signal from the subscriber. Still earlier, after setting the trigger 137 (f Ig. 5) a unit level from the trigger output through the circuit 160 of bus 98 in node 79 (Fig. 6) connects the I 175 element to operation and after inverting this level with the HE 183 element, the I 176 and 177 elements are blocked by the zero level. Next, the I 175 and 177 elements with the help of the element NOT 181 monitors the signal reset Information from the channel After the reset of the named signal the element NOT 181 gives a single level, on the basis of which the element And 175 also gives a single level. At this level, the shaper 169 generates a single pulse. This pulse in the node 79 sets the trigger .166 to a single state, arrives at the second input of the AND element 178 and through the OR element 187 resets the trigger 162. At the first input of the And 178 element, the unit level is received from the set to the single state of the trigger 60 (Fig. . 2) on the circuit 72 of the bus 50 (Fig. 1). As a result of this, the OR element 178 (Fig. 6) permits the passage of a single pulse into the circuit 90 of the bus 36 (Fig. 3). This pulse arrives in block 16 (Fig. 1) and sets in. shaper 85 (Fig. 3) trigger) 246 (Fig, 9).

Further operation of the device depends on the actions taken by the second computer. The following cases are possible: the second computer has not made an attempt to issue a command to the adapter; the second computer has so far begun to issue a command to the address AS ”6; the second computer has so far begun to issue a command at the address AZ ./$ These cases are listed depending on the probability of their occurrence. In the same sequence they are considered.

In the first case, all the circuits of block 16 55 (Fig. 1), except for trigger 246 (Fig. 9), are in the initial state. Triggers 113 and 115 (Fig. 4) have zero states 1203531. Based on these states, the OR element 128 forms a zero level, which, through the circuit 129 of the composite circuit 86, enters the shaper 85 (Fig. 3) after the element HE 249 (Fig. 9) inverts the unit to the first input of the And element 247 as a unit level. a single output of the trigger 246 on the circuit 92 is supplied to the former (Fig. 3) to the first input of the And 247 element (Fig. 8), which is designed to issue the Warning sign. At the same time, the unit level 15 from the single output of the trigger 246 (Fig. 9) through the OR element 248 is fed to the second input of the And 247 element, as a result of which the And 247 element produces a unit level. This level 20 on the circuit 91 connects the element And 123 (Fig. 4) to work in the node 77 (Fig. 3), and through the bus 33 (Fig. 9) through the node 6 (Fig. 1), the output 23 enters the second computer as a signal 25 Subscriber demand.

The second computer, after analyzing the received signal, begins to produce a sequence of sample signals input by the subscriber. For this purpose, this computer generates a sample signal without issuing an address. Lack of signal from the channel address leads for installation in the circuit 131 (Figure 4). Zeroth level bus 27, which blocks · Equipment ^- the AND gate 125 and after inversion by NOT unit 127 receives the level at the inputs of AND gates 122 and 123. The signal sample of input 19 (Fig. 1) through node 2 along

The 4Q bus 27 in block 16 enters the node (Fig. 3), where it is received by the And 123 element on the circuit 130 (Fig. 4). Based on this signal, the And 123 element gives a single level, 45 at which the former 118 generates a single pulse . This pulse sets the trigger 113 to a single state. The single level from the output of the trigger 113 through the circuit 132 of the composite circuit 95 in the node 78 (Fig. 3) is supplied to the second input of the And element 146 (Fig. 5) and blocks the operation of the And element through the element NOT 150 147. In addition, this level from the output of the trigger 113 (Fig. 4) through the OR element 128 through the circuit 129 of the bus 86 in the driver 85 (Fig. 3) without conversion as a signal

1 Nenta enters the bus 33 (Fig. 9), and through the element NOT 249 blocks the operation of the element And 247. As a result, the element And 247 stops issuing a unit level. This means that on the circuit 33 through the node 6 (Fig. 1) at the output 23, the driver 85 (Fig. 3) stops issuing the Subscriber's demand signal to the second computer and starts to issue the Subscriber's operation signal.

This is followed by the issuance by the block 16 (Fig. 1) to the second computer of the adapter address. This operation in block 16 is carried out by the node 77 (Fig. 3) by analogy with the issuance by the corresponding node of the block 15 (Fig. 1) of the adapter address in the first computer at the initial sampling. In node 77 (Fig. 3) of block 16 (Fig. 1), the And 122 element (Fig. 4) receives a single level at the first input from the output of the OR element 128. Since the second computer did not give an Address signal from the channel, it 19 (Fig. 1) through a node 2 via a bus 27 and then in a block 16 to a node 77 (Fig. 3), instead of this signal, a zero level is received, which in a node 77 via a circuit 131 (Fig. 4) after inversion by the element HE 127 enters unit level to the second input of the element And 122. As a result, the element And 122 produces a single level at which the driver 121 generates a single pulse. This pulse sets the flip-flops 116 and 117 to single states. A single level from the output of the flip-flop 116 through the circuit 96 of the bus 35 (Fig. 3) enters the switch 14 (Fig. 1). Based on this level, the switch 14 outputs the code A ₃₆ , formed by the node 10, as the most significant bits of the address and the least significant bits of the address code 3 ₄₆ , which enters the switch along the circuit 49 from the recorder 52 (Fig. 2) of block 17 (Fig. . 1). Compiled in the manner described at the output of the switch 14, the address Α3ι ₆ through the circuit 41 through the node 8 at the output 25 enters the second computer. At the same time, the specified level from the output of the trigger 116 (Fig. 4) through the circuit 96 of the bus 86 enters the former 85 (Fig. 3), where without conversion on the bus 33 (Fig. 9) and then through the node 6 (Fig. 1) output 23 as a signal accompanying the device address code

531, 22

The address from the subscriber goes to the second computer. A single level from the output of the trigger 117 (Fig. 4) through the circuit 133 of the mud 95 enters the node 78 (Fig. 3) and connects it to work.

In response to the transmitted address, the device in the described sequence receives a control signal from the channel from the second computer. This signal at the input 19 (Fig. 1) through the node 2 on the bus 27 and then in the node 78 (Fig. 3) of the block 16 (Fig. 1) through the circuit 157 (Fig. 5) enters the element And 145. At the second input this element receives a single level through the circuit 133 from the output of the trigger 117 (Fig. 4). As a result of this, the And element 145 (FIG. 5) provides a unit level to the first input of the And element 146. At the third input of the And 146 element, a single level is received from the zero output of the trigger 135 located in the initial (zero) state. Based on the data of the levels and the level previously received at the second input on the circuit 132 from the output of the trigger 113 (Fig. 4), the And element 146 (Fig. 5) gives a single level, which is transmitted through the OR element 156 to the input of the shaper 139. A single pulse generated by this shaper after a delay in the delay element 153 sets the trigger 135 to a single state and enters the node 77 through the circuit 97 (Fig. 3 ), where it resets t igger 116 (FIG. 4). Resetting trigger 116 means stopping the adapter issuing to the second computer using switch 14 (Fig. 1) along circuit 41 through node 8 at output 24 of the address code and using shaper 85 (Fig. 3) along circuit 33 (Fig. 1) and further through node 6 on the output 23 signal Address from the subscriber. A single level from the output of the trigger 135 (Fig. 5) through the circuit 158 of the bus 98 enters the node 79 (Fig. 3), where through the element OR 185 (Fig. 6) connects the element And 173 to work.

Next uzez? 79 (Fig. 3) of block 16 (Fig. 1) organizes the transfer of the status byte to the second computer. Connected to the operation of the element And 173 (Fig. 6) on the remaining inputs receives the following levels. In the absence of a signal, Information from the channel from the second computer at input 19 (Fig. 1), node 2 transmits a zero level through composite circuit 27 and then to node 78

120,353;

(Fig. 3) of block 16 (Fig. 1) along circuit 189 (Fig. 6) to the input of the HE 181 element. Based on this level, the HE 181 element gives a single level to the second input of the And 173 element. The third and fifth inputs of this element receive unit levels from the zero outputs of the triggers 162. and 166, which are in the initial (zero) state, respectively. In this state, the And 173 element, using the NOT 180 element, monitors the signal reset. The control from the channel, which comes from the second computer at the input 19 (Fig. 1) through the node 2 on the bus 27 and then in the node 79 (Fig. 3) of the block 16 · (Fig. 1) on the chain 157 (Fig. 6) on the input of the element is NOT 180. After the signal from the channel is reset, the element NOT 180 gives a single level to the first input of the driver 168. As a result of this, at the inputs of the element And 173 there are unit · levels and it contains a unit level at which the shaper 167 forms a single pulse. This pulse sets the trigger 161 to a single state. The single level from the output of the trigger 161 on the circuit 105 of the bus 35 (Fig. 3) enters the switch 14 (Fig. 1) and allows the transfer of the status byte, which forms the shaper 84 (Fig. 3). In this case, the element And 237 is connected to operation in the driver 84 (Fig. 8). Since the trigger 137 (Fig. 5) is in the initial (zero) state, then the zero level from the output of this trigger along the chain

160 bus 98 and further without conversion in the node 79 (Fig. 6) through the composite circuit 106 enters the former 84 (Fig. 3) where it is integrated by the element NOT 241 (Fig. 8). Unit level with element output

NOT 241 goes to the second inputs of the elements AND 237-240. Based on this, the shaper 84 along the circuit 242 of the bus 107 forms only the Attention sign, which is sent via the bus 35 (Fig. 3) to the switch 14 (Fig. 1), which transfers it along the 4Ί circuit through the node 8 at the output 25 to the second computer . At the same time, a single level from the trigger output

161 (Fig. 6) connects the element And 174 to work and through the circuit 105 of the bus 87 enters the former 85 (Fig. 3), where without conversion on the bus 33 (Fig. 9) through the node 6 (Fig. 1) at the output 23 is transmitted to the second computer as a Control 5 signal from the subscriber to accompany the status byte.

After that, the node 79 (Fig. 3) of the block 16 (Fig. 1) enters the standby state from the second computer of the signal 10 Information from the channel. This task in node 79 (Fig. 6) is performed by the And 174 element connected to the work. Signal Information from the channel is received through input 19 (Fig. 1) through node 2 15 via bus 27 and then in node 79 (Fig. 3) of block 16 (Fig. 1) along the circuit 189 (Fig. 6) to the first input of the element

And 174, Based on this signal, the And 174 element gives a single level 20, according to which the shaper 168 generates a single pulse. This pulse resets the trigger 161 and sets the trigger 162 to a single state. After resetting the trigger 25 161, the switch 14 (Fig. 1) through the circuit through the node 8 at the output 25 stops transmitting the status byte to the second computer, and the shaper 85 (Fig. 3) circuit 33 through the node 6 30 (Fig. 1) at the output 23 - signal

Management from the subscriber. A single level with a single output of the trigger 162 (Fig. 6) is supplied to the second inputs of the elements And 175-177. In the described sequence of ₃₅ triggers

134 and 137 (Fig. 5) of the node 78 do not change their state and remain in the initial (zero) state. The zero level from the output of the trigger 137 through the circuit 160 of the composite circuit 98 in the node 79 (Fig. 3) blocks the operation of the AND 175 element (Fig. 6) and, after inversion by the HE 183 unit, the unit receives the _45th right inputs of the And 176 and 177 elements. The zero level from the output of the trigger 134 (Fig. 5) along the circuit 159 of the bus 98 in the node 79 (Fig. 3) blocks the operation of the AND element 176 (Fig. 6) and after inverting _{50 by the} element NOT 182, the unit level goes to the third input of the element

And 177. From the described it follows that the element And 177 remains unblocked. which with the help of element ₅₅ NOT 181 monitors the reset signal

Information from the channel. After resetting this signal in circuit 189, the zero level is set, and the element

NOT 181 issues a unit level to the first input of the element NOT 177. As a result of this, the element NOT 177 produces a unit level at which the driver 171 generates a single pulse. This impulse sets the circuits operating on the second computer to their initial state. At node 79, this pulse confirms the initial state of the triggers 163166, through the OR element 187 flushes the trigger 162, through the circuit 192 of the bus 104 enters the node 80 (Fig. 3) and through the OR element 184 in the circuit 76 and 103. At the node 80 (Fig. 7) this pulse supports the initial state of the triggers 199-202. On the chain 76 (Fig. 6) of the bus 47 (Fig. 3), it enters the block 17 (Fig. 1), where it confirms the initial state of the trigger 61 (Fig. 2). On the circuit 103 (Fig. 6), this pulse enters the node 77 (Fig. 3), where it confirms the initial state of the trigger 114 and 115 (Fig. 4), resets the triggers 113 and 117 and enters the buses 86 and 95. On the bus 86 this pulse enters the former 85 (Fig. 3), where it resets the trigger 246 (Fig. 9). On the bus 95 (Fig. 4) it enters the node 78 (Fig. 3), where it confirms the initial state of the triggers 134, 136 and 137 (Fig. 5) and resets the trigger 135. Resetting the trigger 113 (Fig. 4) means the termination of delivery to the second computer of the signal. The operation of the subscriber through the OR element 128 through the circuit 129 of the bus 86 and then through the driver 85 (Fig. 9) along the composite circuit 33 through the node 6 (Fig. 1) at the output 23.

The device enters the standby state in the second computer, which, when processing the signal of the Subscriber’s demand, received the Attention flag and address A3 ₁₆ . By the sign of Attention, the second computer finds out that one of the active devices is accessing it, by the high order bits of the address (Α _ί6 ) the second computer determines that this device is the first computer, and by the low order bits of the address (3fg) using its address mapping table with the call teams determines for what specific purpose the first computer is accessing and what actions need to be taken. In this case, the first computer requires that the second computer

531 26 issued the command Read with code 3 ^ in the modification bits. So, with the transmission of the Attention flag, all the information necessary for organizing the inter-machine exchange of information is transmitted and there is no need to issue a command Refine the command byte. The second computer starts issuing the corresponding command Read, accompanied by its address A3 ₁₆ .

The sequence of initial sampling signals from the second computer is received and processed by the device in the same way as the described initial sampling from the first computer. The device receives code A3 ₁₆ at input 21 (Fig. 1) through node 4. High-order bits (A ₁₆ ) go to node 12 via circuit 43, where they are compared with the device’s own address (A ₁₆ ) for the second computer formed by node 10 and transmitted to the node 12 on the chain 40. As a result of the comparison, the node 12 on the chain 31 generates an address recognition signal. The least significant bits (3 ₄₆ ) of the received code in circuit 45 are sent to block 17 to the information input of register 54 (Fig. 2).

The device receives the signal from the channel at input 19 (Fig. 1) through node 2 and then on bus 27 to block 16. Here, this signal is processed by node 77 (Fig. 3). The signal Address from the channel in the node 77 (Fig. 4) through the circuit 131 of the bus 27 is fed to the second input of the AND element 125. The first input of this element receives a single level from the output of the element NOT 126, which determines the absence of the Sampling signal in the circuit 130, and the third input of the element And 125 on the circuit 31 receives an address recognition signal. As a result of this, the And element 125 provides a unit level at which the driver 119 generates a single pulse. This pulse sets the trigger 114 and enters the block 17 (Fig. 1) through the circuit 73 of the bus 47 (Fig. 3), where it enters into the register 54 (Fig. 2) the value of the least significant bits of the received address (3 ^). Since by this time trigger 60 is set to a single state, the zero level from the zero output of this trigger goes to the information input of trigger 61. Based on this, the pulse received through circuit 73 of bus 47 does not change the state of trigger 61. This means that all other elements of block 17, except node 59, remain in the same state. Node 59 compares the contents of registers 54 and 52 and, since each of them stores code 3 _(th) , it outputs a unit level along circuit 51 — a signal of correspondence of addresses received from two computers.

A single level from the output of the trigger 114 (Fig. 4) connects the And 124 element to operation, which begins to monitor the appearance of the Sampling signal in the circuit 130 of the bus 27. With the appearance of _{! 5} this signal, the And element 124 provides a unit level at which the driver 120 generates a single pulse. This pulse sets the trigger 115. A single level from the output of the trigger 115 through the element OR 128 connects the element And 122 to work and on the circuit 129 of the bus 86 through the shaper 85, (Fig. 9) on the bus 33 through the node 6 (Fig. 1) at the output 23 as a signal The work of the subscriber enters the second computer.

Connected to the · operation, the element And 122 (Fig. 4) with the help of the element I. 127 monitors the signal reset. The address from the channel in the circuit 131. After the reset of this signal, the element And 127 gives a single level, on the basis of which the element And 122 also gives a single level. At this level, the driver 121 generates a single pulse, which sets the triggers 116 and 117. The single level from the output of the trigger 116 through the circuit 96 of the bus 35 (Fig. 3) enters the switch 14 (Fig. 1), which transfers the code A, ₆ through it generated by the node 10, and the code stored in the register 52 (Fig. 2). These codes, respectively, along the circuits 40 and 49 (Fig. 1) and then through the switch 14 through the circuit 41 through the node 8 at the output 25 enter the second computer as the code A3 _{16 of the} adapter address. At the same time, a single level from the output of the trigger 116 (Fig. 4) along the circuit 96 of the bus 86 through the driver 85 (Fig. 9) via the bus 33 through the node 6 (Fig. 1) at the output 23 enters the * second computer as a signal Address from subscriber.

A single level from the output of the trigger 117 (Fig. 4) along the circuit 133 of the bus 95 is fed to the input of the element And 145

1203531 28 (Fig. 5) in the node 78 'and connects it to work. Element And 145 begins to monitor the appearance of the control signal from the channel, which accompanies the code received from the second computer command. The command code is received at input 21 (Fig. 1) through node 4 through circuit 29 to the first input of decoder 81 (Fig. 3) in block 16 (Fig. 1).

The signal from the channel enters the input 19 through the node 2 through the composite ash 27 and then in block 16. through the circuit 157 (Fig. 5) 'to the first input of the element And 145 of the node 78. As a result, this element gives a single level. The I 147 element operates at this level, since a unit level arrives at its second input after the element HE 150 inverts the zero level from the output of the trigger 113 in the initial (zero) state (Fig. 4) and to the third input the unit level from the zero output of the trigger ₂₅ 135 (FIG. 5) in the zero state. On a single level from the output of the element And 147, the shaper 140 forms a single pulse.

This pulse sets the trigger 136 to a single state. The single 30th level from the output of this trigger on the circuit 99 goes to the second input of the decoder 81 (Fig. 3), which starts to decrypt the received command. The same pulse from the output 35 of the shaper 140 (Fig. 5) after.

the delay in the delay element 154 along the circuit 100 is fed to the clock input of the register 82 (Fig. 3) and enters the result of the decryption of the 4θ command by the decoder 81. After that, the contents of the register 82 of the block 16 through the circuit 102 are fed to the first input of the node 83, the second input of the node 80 and on the bus 37 in block 15 (Fig. 1) to the second 45 input node 83 (Fig. 3). As a result of this, both nodes 83 of blocks 15 and 16 (Fig. 1) compare the decoded commands received at their inputs for their correspondence to one another. The node 50 83 (Fig. 3) of the block 15 ’(Fig. 1) compares the Write command with the Read command and issues a single level on the circuit 112 (Fig. 3). The node 83 of block 16 (Fig. 1) compares the 5S command Read with the Write command and also issues a unit level along the circuit 112 (Fig. 3). In block 15 (Fig. 1), the generated level is not used in this case.

In block 1 b, a similar level goes to the fifth input of the element And 143 (phi1 *. 5) and after inverting the element NOT 152 to the zero level blocks the operation of the element And 142. The first input of the element And 143 receives a single level along circuit 72 of the composite circuit 51 with a single the output of the trigger 60 (Fig. 2) of block 17 (Fig. 1). The same level in circuit 72 (Fig. 5) after inverting the element NOT 149 to the zero level blocks the operation of the And 144 element. The second input of the And 14’3 element receives a single level from the output of the trigger

136. At the third input of element And 143, a unit level is supplied via circuit 70 of bus 51 from the output of node 59 (Fig. 2), which determined the correspondence of addresses found by two computers. At the same time, this level in circuit 70 (Fig. 5) after inverting the element HE 151 to the zero level blocks the operation of the And 148 element. The fourth input of the And 143 element receives a single level from the zero output of the trigger 135, which is in the zero state, to which the driver 141 generates a single pulse. This pulse sets the trigger

137, which controls the issuance of a null status byte.

The inputs of the And 142 element receive the same levels as the corresponding inputs of the And 143 element. The And 142 element is blocked only at the fifth input, to which a single level arrives when there is a violation of consistency between two computers, i.e. node 83 (Fig. 3) in a similar situation determines the discrepancy received from two computers commands and chain 112 produces a zero level. This level blocks the operation of the AND element 143 (Fig. 5) and, after inverting the element NOT 152 as a unit level, connects the And element 142 to work. In this case, the And element 142 issues a unit level that enters through the OR element 155 to the input of the shaper 138. Such an operation devices, in a coordinated system should not occur, and the element And 142 more controls the degree of coordination of the system of two computers and the device than is involved in a particular job. The operation of the device after connecting the shaper.

ι38 is described when considering the subsequent operation modes of the device.

When the device is operating in a coordinated computer system, the element And 142 'is blocked, and the element And 143 works. As a result of this work, the trigger 137 is set to a single state.

In addition to the described, a single level from the output of the trigger 136 enters through the OR element 156 to the input of the shaper 139, which as a result of this generates a single pulse15. This pulse after the delay in the delay element 153 sets the trigger 135 to a single state and, through the circuit 97, enters the node 77 (Fig. 3) where it resets the trigger 20 116 (Fig. 4). The reset of this trigger means the cessation of the issuance of the adapter address 14 and the driver 85 (Fig. 3) of the Address signal from ABO25 to the second computer with the switch 14 (Fig. 1).

The single level from the output of the trigger 135 (Fig. 5) through the circuit 158 of the bus 98 enters through the OR element 185 (Fig. 6) to the fourth input 30 of the And element 173. The second input of the element receives the single level from the output of the element NOT 181, which determines ( the lack of a signal in the circuit 189 ^! Information from the channel ”, the third and fifth inputs of the And 173 element receive unit levels from the zero outputs of the triggers 162 and 166, respectively, in the initial (zero) state. In this state, the And element is 173 s using the element NOT 180 monitors the reset signal Control from the channel in 157. After resetting this signal, the element NOT 180 gives a single level to the first input of the element ₄₅ and 173, on the basis of which the element And 173 also gives a single level, and the shaper 167 generates a single pulse as a result.This pulse sets the trigger 161.

A single level from the output of the trigger 161 on the circuit 105 of the bus 35 (Fig. 3) enters the switch 14 (Fig. 1), which at this level gives 55 status bytes prepared by the driver 84 (Fig. 3) from the zeros on the circuit 35 through the switch 14 (Fig. 1), through circuit 41 through node 8 to exit 25 to the second computer. On the other hand, this level is from the output of trigger 161 (Fig. 6) along circuit 105 of bus 87 and then through former 85 (Fig. 9) bus 33 through the node 6 (Fig. 1) at the output 23 enters the second computer as a control signal from the subscriber.

A single level from the output of the trigger 161 (Fig. 6) connects the element And 174, which begins to monitor the receipt of the signal information from the channel. This signal is received from the second computer via input 19 (Fig. 1) through node 2 via bus 27 to node 79 (Fig. 3) of block 16 (Fig. 1), where, through circuit 189 (Fig. 6), it enters the first input of the element And 174. As a result of this, this element gives out a unit level at which the shaper 168 forms a single impulse. This pulse resets the trigger 161 and sets the trigger 162 to a single state. With the reset of the trigger 161 through the switch 14 (Fig. 1), the output of the status byte to the second computer is stopped, and the signal from the subscriber is stopped through the former 85 (Fig. 3). With the installation in a single state of the trigger 162 (Fig. 6), the operation of the element And 173 is blocked and the element is connected to the work. . .

And 175-177. On the circuit 160 of the bus 98 from the output of the trigger 137 (Fig. 5) to the third input of the And 175 element (Fig. 6), a single level is received, which, after the element HE 183 inverts to the zero level, blocks the And 176 and 177 elements, i.e., from the above elements continues to work, only the AND element 175. He uses the element NOT 181 to monitor the reset signal Information from the channel. After resetting the named signal, the element NOT 181, and then the AND 175 element, give single levels. On a single level from the output of the element And 175 shaper 169 generates a single pulse. This pulse sets the trigger 166 to a single state, arrives at the second input of the And 178 element and, through the OR element 187, resets the trigger 162. At the first input of the And 178 element through the circuit 74 of the composite circuit 51, the trigger has a single output 61 '(Fig. 2) level and blocks the operation of the element And 178 (Fig. 6). As a result of this, no pulse is supplied to circuit 89. When the trigger 166 is set to a single state, the zero level from the zero output of this ₅ trigger goes to the fifth input of the And 173 element. Although the trigger 162 is reset at this time, the And 173 element remains blocked.

A single level with a single _ί0 output of the trigger 166 of the node 79 (Fig. 3) of the block 15 (Fig. 1) through the circuit 195 (Fig. 6) of the bus 104 is supplied to the first input of the element And 217 (Fig. 7) of the node 80 (Fig. 3) ) block 15 (Fig. 1) and then U on bus 110 (Fig. 6), then on bus 36 (Fig. 3) to block 16 (Fig. 1), where it is received at the second input by AND element 217 (Fig. 7) node 80 (Fig. 3). A single level with a single output ₂₀ and a trigger 166 (Fig. 6) of the node 79 (Fig. 3) of the block 16 (Fig. 1) through the circuit 196 (Fig. 6) of the bus 104 is supplied to the first input of the And element 217 (Fig. 7) node 79 (Fig. 3) of block 16 (Fig. 1) ₂₅ and then through Qina 111 (Fig. 6), and then through bus 37 (Fig. 3) to block 15 (Fig. 1), where it receives the second input element And 217 (Fig. 7) of the node 80 (Fig. 3). Both elements And 217 (Fig. 7) of nodes 80 (Fig. 3) of blocks 15 and 16 (Fig. 1) receive unit levels at both inputs and, therefore, both elements And 217 (Fig. 7) produce unit levels, connecting both node 80 (Fig. 3) to work.

⁴ · 'In block 15 (Fig. 1) _ from the register (Fig. 3), a unit level arrives at node 80 through circuit 226 (Fig. 7) of bus 101 (Fig. 3), which indicates that block 15 (Fig. 1) ) accepted command ⁴³ Write. This level goes to the first input of the element And 215 (Fig.7). The second input of this element receives the unit level from the output of the And 217 element. The third input of the element ^{45 of the} And 215 element goes through the circuit 229 of the bus 111, which is part of the bus 37 (Fig. 3), the unit level comes from the zero output located in the zero (initial) the state of the trigger 202 (Fig. 7) ^{50 of the} node 80 (Fig. 3) of the block 16 (Fig. 1). This level indicates that the exchange has not yet begun. Based on all the described levels, the AND element 215 (Fig. * 7) of the node 80 (Fig. 3) of the block 15 (Fig. 1) gives a single level, which through the OR element 221 (Fig. 7) is supplied to the input of the shaper 208. This the shaper at this level generates a single pulse, which sets the trigger 198 to a single state. The single level from the output of the trigger 198 goes to the second inputs of the elements And 210 and 214 and through the OR element 223 to the circuit 88. On the circuit 88 (Fig. 3) this level enters through the shaper 85 (Fig. 9) through the composite circuit 32 through the node 5 (Fig. 1) at the output 22 in the first e VM as a signal Information about the subscriber. This signal for a computer is a request for a data byte.

Byte of data from the first computer at input 20 through node 3 through circuit 28 through block 15 (Fig. 3) via bus 36 (Fig. 1) through block 16 (Fig. 3) via bus 35 enters switch 14 (Fig. 1) . Accompanying byte of data signal signal Information from the channel from the first computer is received through input 18 through node 1 via bus 26 to node 80 (Fig. 3) of block 15 (Fig. 1), where it is received on the first input through circuit 189 (Fig. 7) element And 210. Since the second input, this element has already received a unit level, then according to the received signal, the element And 210 gives a unit level. This level is supplied to the second input of the element And 218 and along the circuit 232 through the bus 110 included in the bus 36 (Fig. 3), in block 16 (Fig. 1). In block 16, this level receives the element And 216 (Fig. 7) of the node 80 (Fig. 3) at the third input. At the first input of the element And 216 (Fig. 7) along the circuit 228 of the bus 102, a single level is received from the output of the register 82 (Fig. 3). This level indicates that block 16 (FIG. 1) has received the Read command. The second input of the And 216 element (Fig. 7) receives a single level from the output of the And 217. At these levels, the And 216 element gives a single level at which the shaper 204 generates a single pulse. This pulse sets the trigger 197 to a single state. A single level from the output of the trigger 187 connects the elements And 209 and 213 to work, enters the circuit 109 and through the OR element 223 to the circuit 88. This circuit is supplied via circuit 109 of bus 35 (Fig. 3) to the switch 14 (Fig. 1) and allows transmission

1203531 34 previously received data byte in chain 41, after which this data byte! through node 8 at the output .25 enters the second computer. On the circuit 88 (Fig. 3), the described level through the driver 85 on the bus 33 (Fig. 9) and then through the node 6 (Fig. 1) at the output 23 enters the second computer as a signal Information from the subscriber. For the second computer 'θ, this signal is a message about the transmission of a data byte to it. The computer receives a byte of data and informs the adapter about this by the signal Information from the channel. This signal is input

19 through node 2 via bus 27 to block 16. In block 16, it is received via circuit 189 (Fig. 7) and element 209 of node 80 (Fig. 3). This element is already connected to work with the receipt of the specified signal gives a single level at which the shaper 207 (Fig. 7) generates a single pulse. This pulse sets flip-flops 201 and 202 to one state and resets flip-flop ^{25 to} trigger 197. Resetting flip-flop 197 means that levels 0 and 0 have arrived at circuit 109, as a result of which switch 14 (Fig. 1) stops transmitting the data byte, and after ³⁰ the shaper 85 (Fig. 3) and then through the node 6 (Fig. 1) stops issuing the signal Information from the subscriber. The zero level from the zero output of the trigger 202 (Fig. 7) along the circuit 229 of the bus 111 included in the bus 37 (Fig. 3), arrives from block 16 (Fig. 1) in block 15 to the third input of the And element 215 (Fig. 7) ) node 80 (Fig. 3) and blocks the operation of this 40 element. A single level from the output of the trigger 201 (Fig. 7) of the node 80 (Fig. 3) of the block 16 (Fig. 1) is supplied to the third input of the element And 212 (Fig. 7) and through the circuit 233 of the bus 111, which is part of the bus

37 (Fig. 3), to block 15 (Fig. 1) and to the first input of element And 218 (Fig. 7) of node 80 (Fig. 3). The second input of the And 218 element (Fig. 7) has already received a single level from the output of the And 210 element. As a result of this, the And 218 element gives a single level, according to which the shaper 205 generates a single pulse. This pulse resets the trigger 198 and sets the trigger 200 to a single state. With the reset of the trigger 198, zero levels are established in circuits 88 and 232.

The zero level of the circuit 88 means that through the driver 85 (Fig. 3) on the bus 32 through the node 5 (Fig. 1) at the output 22, the device stops issuing the signal Information from the subscriber to the first computer. The zero level of the circuit 232 (Fig. 7) is supplied to the third input of the And element 216 of the assembly 80 (Fig. 3) of the block 16 (Fig. 1).

After that, both nodes 80 (Fig. 3) of blocks 15 and 16 (Fig. 1) go into standby mode for signal drops Information from the channel from the corresponding computers. In node 80 (Fig. 3) of block 15 (Fig. 1), the And signal 211 (Fig. 7) monitors the reset of the named signal using the element NOT 224. In node 80 (Fig. 3) of block 16 (Fig. 1) signal reset Information from the channel in this case is monitored by the And 212 element (Fig. 7) using the HE 224 element. Both nodes 80 (Fig. 3) perform this work independently of one another.

After resetting the signal, Information from the channel of the first computer in circuit 189 (Fig. 7) of node 80 (Fig. 3) of block 15 (Fig. 1) sets the zero level, which, after inversion by the element NOT 224 (Fig. 7), is transmitted to the unit level by the first input of the AND element 211. The second input of this element receives a single level after the element NOT 225 inverts the zero level coming through the circuit 235 of the bus 111 entering the bus 37 (Fig. 3) from the output of the OR element 220 (Fig. 7) node 80 (Fig. 3) of block 16 (Fig. 1). The OR element 220 (Fig. 7) gives a zero level, since its inputs receive zero levels from the outputs of the And 213 and 214 elements, which are blocked by a zero level from circuit 157. A control signal from the channel that no time period. At the third input of the And 211 element, a single level has already arrived from the output of the trigger 200. Based on the listed levels, the And 211 element gives a single level, which passes through the OR element 221 to the input of the shaper 208.

After the reset, the signal ^ Information from the channel of the second computer likewise in circuit 189 (Fig. 7) of node 80 (Fig. 3) of block 16 (Fig. 1) sets the zero level, which after inverting the

1203531 36 by coping NOT 224 (Fig. 7) with a unit level NOT 224 (Fig. 7) as a unit level arriving at the first input of the And 212 element. At the second input of this οπές moment, the unit level is received after the element NOT 225 inverts the zero level coming through the bus circuit 236 110 included in the bus 36 (Fig. 3), from the output of the element 10 OR 220 (Fig. 7) of the node 80 (Fig. 3) of the block 15 (Fig. 1). The OR element 220 (Fig. 7) produces a zero level under the same conditions as the corresponding element of block 16 (Fig. 1). At 55, the third input of the And 212 element (Fig. 7) has already received a single level from the output of the trigger 201. Based on these levels, the OR element 212 provides a single level at which the shaper 206 generates a single pulse. This pulse resets the trigger 201. With the reset of the trigger

201 from its output, the zero level enters through the specified circuit to the first input of the And element 218 of the node 80 (Fig. 3) of the block 15 (Fig. 1). This ends the cycle of transmitting a data byte from the first to the second computer. After this cycle, in node 80 (Fig. 3) of block 15 (Fig. 1), the trigger 200 (Fig. 7) remains in a single state ³⁰ , and in node 80 (Fig. 3) of block 16 (Fig. 1) - trigger

202 (Fig. 7), which remains in this state until the end of the exchange, and therefore the And element 215 of the node 80 (Fig. 3) of the block 15 (Fig. 1) remains blocked for this period. The next cycle of transmitting a data byte through the device from the first computer to the second begins immediately 40 with the arrival at the input of the former 208 (Fig. 7) of a single level. At this level, this shaper forms a single pulse. Further work of nodes 80 (Fig. 3) of blocks 15 and 16 (Fig. 1) for data exchange is carried out in the described sequence.

The termination of the exchange is possible at the initiative of any computer. In response to 50 transmitted by the device signal Information from a computer subscriber for this purpose gives a control signal from the channel. In the described exchange, in block 15 (FIG. 1), an indication of 55 termination of the exchange is monitored by element And 214 (FIG. 7) of node 80 (FIG. 3), and in block 16 (FIG. 1), element And 213 (FIG. 7) node 80 (Fig. 3). These elements are connected to this work after installation in a single state, respectively, of the trigger 198 (Fig. 7) of the node 80 (Fig. 3) from block 15 (Fig. 1) and the trigger 197 (Fig. 7) of the node 80 (Fig. 3) of the block 16 (Fig. 1). '

If, for example, * the end indication is received from the first computer, then the Channel control signal passes through input 18 through node 1 via bus 26 to node 80 (Fig. 3) of block 15 (Fig. 1), where it is received by chain 157 (Fig. 7) And 214 element. After that, And 214 element gives a single level through the OR element 220 to the circuit 236 and then through the OR element 222 to the input of the former 203. On the circuit 236 of the bus 110, which is part of the bus 36 (Fig. 3 ), this level enters the node 80 of block 16 (Fig. 1). Here from also through the element OR 222 (Fig. 7) is fed to the input of the shaper 203.

If the indication of the end of the exchange comes from the second computer, then the Control signal from the channel passes through input 19 (Fig. 1) through node 2 via bus 27 to node 80 (Fig. 3); block 16 (Fig. 1), where it is received by circuit 157 (Fig. 7) of element 213. This element gives a unit level in the same way through element OR 220 to circuit 235 and then through element OR 222 to the input of former 203. Circuit 235 of the bus 111 included in the bus 37 (Fig. 3), the specified level enters the node 80 of block 15 (Fig. 1). Here he also through the element OR 222 (Fig. 7) enters the input of the shaper 203.

As a result of issuing instructions on the termination of the exchange of any of the computers, unit levels are received at the inputs of both formers 203 of nodes 80 (Fig. 3) of blocks 15 and 16 (Fig. 1). At these levels, these shapers form single pulses, which are reset at their nodes by triggers 197 and 198 (Fig. 7), set the triggers 199 to a single state, and through the chain 191 of the bus 108 enter the corresponding nodes 79 (Fig. 3), where they are installed single state triggers 164 (Fig. 6) and through the elements OR 186 triggers 165.

A single level from the output of trigger 199 (Fig. 7) of node 80 (Fig. 3) of block 15 (Fig. 1) along circuit 190

1203531 38 (Fig. 7) of the bus 108 enters through the OR element 185 (Fig. 6) to the fourth input of the And 173 element. The second input of the And 173 element receives a unit level from the 5 · output of the HE 181 element, which indicates the absence at the moment signal Information from the channel in the circuit 189. The third and fifth inputs of the element And 173 receive unit levels in the zero state. In this state, the And 173 element, using the NOT 180 element, monitors the reset of the Channel control signal. With the reset of this signal in circuit 157, the zero level is set. After it is inverted by the element NOT 180, the unit level goes to the first input of the element And 173, which, as a result of this, gives a unit level. At this level, the driver 167 generates a single pulse, which sets the trigger 161 to a single state. A single level from the output of this trigger enters the circuit 105 of buses 87 and 34 (Fig. 3). On the bus 34, this level connects the switch 13 (Fig. 1) to transmit the status byte. The status byte is generated by the driver 84 based on the single states of the triggers 164 and 165 (Fig. 6) and the cool state of the trigger 137 (Fig. 5). The zero level from the output of the trigger 137 through the circuit 160 of the bus 98, which is part of the bus 3 ^s 106 (Fig. 6), enters the former 84 (Fig. 3), where after inversion by the element HE 241 (Fig. 8), the unit level goes to the second inputs of the elements And 237-240. Single levels from the outputs of the triggers 164 and 165 (Fig. 6), respectively, through the circuits 193 and 194 of the composite circuit 106 are supplied to the first inputs of the elements And 239 and 240 (Fig. 8). As a result of this, the unit level from the output of the And 239 element as a feature Channel ended on circuit 244 and the unit level from the output of the And 240 element as a feature of the VU terminated on circuit 245 are received via bus 107, which is part of the 34 bus (Fig. 3), the switch 13 (Fig. 1), which transmits them in the status byte along the circuit 39 through the node 7 at the output 24 in the first ⁵⁵ computers.

On bus 87 (Fig. 3), the unit level from the output of the flip-flop 161 (Fig. 6) enters through the former 85 (Fig. 9) through the composite circuit 32 through the node 5 (Fig. 1) at the output 22 also to the first computer as an accompanying status byte signal Control from the subscriber.

Next, the element And 174 (Fig. 6) to the second input of which a single level is received from the output of the trigger 161, monitors the receipt of information from the channel on the circuit 189. The adapter receives this signal from the first computer in response to the status byte issued. This signal at input 18 (Fig. 1) through node 1 via bus 26 enters block 15, where it is received via circuit 189 (Fig. 6) in node 79 (Fig. 3) and element 174 (Fig. 6). According to this signal, the element And 174 gives a single level at which the shaper 168 generates a single pulse. This pulse resets the trigger 161 and sets the trigger 162 to a single state. With the reset of the trigger 161, the transmission of the status byte through the switch 13 (Fig. 1) stops, and the control signal from the subscriber through the former 85 (Fig. 3). The zero level from the zero output of the trigger 1'62 (Fig. 6) blocks the operation of the element And 173. The single level from the single output of the trigger 162 goes to the second inputs of the elements And 175-177. Element And 175 is blocked by a zero level, coming through the circuit 160 of the composite circuit 98 from the output of the trigger 137 (Fig. 5), which is in the zero state. The element And 176 (Fig. 6) is blocked by a zero level, coming through the circuit 159 of the composite circuit 98 from the output of the trigger 134 (Fig. 5), also in the zero state. The same levels from the outputs of flip-flops 134 and 137 on the described circuits after inverting the elements HE 182 and 183 (Fig. 6), respectively, are supplied by unit levels to the third and fourth inputs of the I 177 element. In this state, this element uses the HE 181 element to monitor the reset Signal Information from the channel. After resetting the first computer of this signal, a zero level is set in the circuit 1 89 ° and the element NOT 181 gives a single level to the first input of the element And 177. As a result, this element also gives a single level, according to which

1203531 40 the driver 17.1 generates a single pulse. This impulse is the impulse of setting the unit .15 (Fig. 1) to its initial state. At node 79 (Fig. 6), it arrives at the zero inputs of flip-flops 163-166 and through the OR element 187 to the zero input of flip-flop 162, as well as to circuit 192 of bus 104 and through OR element 184 v, 0 of circuit 75 and 103. In a single Triggers 162, 164, and 165 are in state. They assume a zero state. The bus 104 receives a pulse at the zero inputs of the triggers 199-202, 5 (Fig. 7) of the node 80 (Fig. 3) and resets them to the zero (initial) state. On the circuit 75 of the bus 46, the pulse is supplied to the zero input of the trigger 60 (Fig. 2) of the block 17 (Fig. 1) and 2Q resets it to the zero state.

On the circuit 103 (Fig. 3), this pulse is supplied to the zero input of the triggers 113-117 (Fig. 4) of the node 77 (Fig. 3), as well as to the buses 86 and 95 (Fig. 4).

The specified pulse sets the triggers 114-117 to the zero (initial) state. The bus 86 sends a pulse to the zero input of the trigger 246 (Fig. 9) of the driver 85. On the ₃₀ bus 95 (Fig. 3) it enters the zero inputs of the triggers 134-137 (Fig. 5) of the node 78 (Fig. 3). The pulse resets the triggers 135 and 136 (Fig. 5) to the zero (initial) state. After this, the block 15 (Fig. 1) comes to the initial state.

Similarly, the node 79 (Fig. 3) of the block 16 (Fig. 1) works, which also arranges for the output to the second computer of a status byte with the signs Channel has finished and the control unit has finished ”and after issuing them, it ensures the installation of the nodes of block 16 in the initial state. This completes the execution of the Write command received from the first computer, and the Read command received from the second computer. In this case, the execution of these commands does not require the issuance of an additional team Clarify command bytes as ⁵⁰ all the information a second 'computer receives the code addresses upon receipt sign Attention.

The device works similarly if it receives the Read command from the first computer when accompanied, for example, by address 95, < ₆ . In this case, the device sends the Warning sign with the address to the second computer

A5 _1fe , in response to which it receives the Write command, followed by the address A5 ^. This easily determines the second computer from the correspondence table. The difference in the operation of the device in this case is in the direction of exchange and its provision. The work performed by the node 80 (Fig. 3) of the block 15 (Fig. 1) performs the node 80 (Fig. 3). block 16 (Fig. 1) and vice versa, the work performed by the node 80 (Fig. 3) of the block 16 (Fig. 1) performs the node 80 (Fig. 3) of the block 15 (Fig. 1).

The device works similarly when first receiving a command from the second computer. In this case, the Attention flag with the corresponding address is transmitted to the first computer by the device.

Upon receipt, for example, of the Control command from the first computer when accompanying it, for example, with the address 9B _{, the} device in the described sequence receives it and sends the Attention flag when tracking the address AB _1b to the second computer. Block 15 after receiving the command goes into the idle state of the result of the transmission of the sign Attention to the second computer. This work in block 15 is performed by the node 80 (Fig. 3), in which a single level from the register 82 (Fig. 3) is supplied through the circuit 227 (Fig. 7) of the bus 101. This level indicates that block 15 (FIG. 1) has received a control command. He goes to the first input of the element And 219 (Fig. 7). After issuing the sign Attention to the second computer, the block 16 (Fig. 1) in this sequence returns to its original state, including trigger 246 (Fig. 9) of the former 85 (Fig. 3). A single level from the zero output of the trigger 246 (Fig. 9) along the circuit 94 of the bus 37 is fed to the second input of the And element 219 (Fig. 7) of the assembly 80 (Fig. 3) of the block 15 (Fig. 1). As a result of this, the unit level from the output of the element And 219 (Fig. 7) through the OR element 222 is fed to the input of the former 203. The latter generates a single pulse, which sets the trigger 199 to a single state and enters the node 79 through the circuit 191 of the bus 108 (Fig. 7). 3). Here he sets in the described sequence the triggers 164 and 165 (Fig. 6), the Unit level from the output of the trigger 199 (Fig. 7) along the bus circuit 190

1203531 ⁴²

108 also enters the node 79 (figure 3) and connects it to the work of issuing a status byte. In the described sequence, the node 79 ₅ provides for the delivery to the first computer of a status byte with the sign Channel has finished and the control unit has finished, and then the block 15 (Fig. 1) is set to its initial state.

With the sign “Caution” in the address code, the AV device provides the transfer to the “second computer of all control information, which the second computer easily decrypts according to the correspondence table. The need to issue a command Refine the byte of the command in this case, too. To transfer control information from the second computer to the first one, addresses 2o are allocated from addresses intended for issuing control information from the first to the second computer. The transfer of such commands is carried out in a similar way.

With the frequent exchange of information through the device, there is a possibility of simultaneous issuance of commands by two computers. So, for example, during the period when the device receives the Command ³⁰ from the first computer to record. When accompanied by its address 93 _{от 6} , the command Control is _sent from the second computer when it is accompanied by its address AC _{) 6} .

Reception of the “Write” command from the first

The computer is carried out in the described sequence. At the same time, at this time, the device receives the address of AC _1b from the second computer. The most significant bits of the addresses go to node 12. As a result of comparing them with the code A _1b generated by node 10, node 12 generates an address recognition signal. This signal on the circuit 31 enters the node 77 (Fig. 3) of the block 16 (Fig. 1) to the third input of the And element 125 (Fig. 4). Accompanying the address signal The address from the channel on the circuit 131 also enters the node 77 (Fig. 3) of the block 16) to the second input of the And element 125 (Fig. 4). The first input of this element receives a single level from the output of the element NOT 126, which determines the absence in the circuit 130 of the signal Sampling from the channel. Based on the described levels, the item

And 125 gives a single level at which the shaper 119 generates a single pulse. This pulse ust43 fills the trigger 114 and enters the circuit 73 of the composite circuit 47 (Fig. 3) to the clock inputs of the trigger 61 (Fig. 2) and the register 54.

In this case, two cases are possible.

By the time the pulse arrives in circuit 73, trigger 60 is set to a single state. In this case, the information input of trigger 61 receives a zero level from the zero output of trigger 60. Based on the received pulse, the least significant bits of address C are entered into register 54 in the described sequence, and trigger 61 retains its zero state.

A situation is possible when the arrival of a pulse along circuit 73 coincides in time with the arrival of a similar pulse along circuit 71 from block 15 (Fig. 1). In this case, the information inputs of triggers 60 and 61 (Fig. 2) receive unit levels from the zero outputs of the answering system. venno flops 61 and 60. By means of said pulses to the register 53 3 is written code _46, code 54 into register _46, and sets both the trigger and 61. It is for this node is not operating situation. To exclude it, in block 17 there are elements 62 and 64, delay element 55, and driver 66, which provide priority for the commands of the first computer. After the triggers 60 are set to a single state and unit outputs are supplied to the inputs of the And 62 element, single levels are received, on the basis of which this element gives a single level. This level, after some delay in the delay element 55, enters the input of the shaper 66. At this level, the shaper 66 generates a single pulse that resets the trigger 61. For the time until the trigger 61 is reset, the unit level from the output of the And 62 element after the HE 64 inverts the zero level to the first input of the And 63 element and blocks its operation. After resetting the trigger 61 at the output of the And 62 element, a zero level is set, which means that from the output of the element

NOT 64 receives a single level, which connects the AND 63 element to work. Further operation of block 17 is carried out in the described sequence. A single level from a single output of trigger 60 allows

1203531 44 passage through the switch 68 of the contents of the register 53, and the zero level from the single output of the trigger 61 blocks the passage through the switch 68 of the contents of the register 54. The pulse generated by the And 63 element, enters the code received from the output of the switch 68 into the register 52. From described it is seen that regardless of 10 from the time of receipt of the command from the second computer, the final state of block 17 is the same.

The case when the signal to the circuit 73 comes before the signal to the circuit 71,,

55 is analogous to the first case described ,, if computers are interchanged.

In the end result, registers 52 and 53 memorize the 3 ^ code, and register 54 - code C., 6 · Node 58 gives ^{20 a} single level, which indicates that the same code is stored in registers 52 and 53, and node 59 gives zero a level that indicates that different codes are stored in modes 52 and 54.

Further, in block 16 (Fig. 1), the And element 124 (Fig. 4) of the .77 node (Fig. 3) monitors the appearance in the circuit 130 (Fig. 4) of the signal The sample from the channel and with its ³⁰ arrival gives a single level, according to to which the driver 120 generates a single pulse. This pulse is set by trigger 115. With the installation of this trigger, block 16 35 (Fig. 1) issues a subscriber operation signal to the second computer. After that, the And 122 element (Fig. 4), using the NOT 127 element, monitors the signal reset. The address from the channel in the circuit 131. With the 40 reset of the named signal, the And 122 element gives a single level at which the driver 121 generates a single pulse. This pulse sets the triggers 116 and 117 to the single state of the trigger45. The single level from the output of the trigger 116 provides the A3 ^ ₆ code through the switch 14 (Fig. 1) and the signal 50 Address from the subscriber through the driver 85 (Fig. 3). A single • level from the output of the trigger 117 (Fig. 4) connects the node 78 to the work (Fig. 3).

At node 78, the element And element 145 begins work (Fig. 5), which monitors the receipt of a signal along circuit 157

Channel control from the second

COMPUTER. This signal accompanies to the ⁴⁵ Manda, which is fed to the input of the decoder 81 (Fig. 3). With the arrival of the control signal from the channel, the element * AND 145 (Fig. 5) issues a unit level to the first input of the element And 147. The second input of this element receives a single level from the output of the element NOT 150, which determines in circuit 132 a zero level from the output of trigger 113 (Fig. 4).

At the third input of the element And 147 (Fig. 5), a single level is supplied from the zero output of the trigger 135. As a result, the And 147 element contains a single level at which the driver 140 gives a single pulse. This pulse sets trigger 136 to a single state. A single level from the output of the trigger 136 on the circuit 99 connects to the work of the decoder 81 (Fig. 3). At the same time, this level connects the elements AND 142, 143 and 148 (Fig. 5) to the operation, and the former 139 through the OR 156 element. In addition, the pulse from the output of the former 140 goes to the second input of the And 144 element. The And 142 and 143 elements are blocked the zero level coming in on the circuit 70 from the output of the node 59 (Fig. 2). The AND element 144 (Fig. 5) is blocked by the zero level from the output of the element NOT 149, which determines in circuit 72 a unit level coming from the single output of the trigger 60 (Fig. 2). The AND element 148 remains unblocked (Fig. 5). The second input of this element receives a unit level after inverting the zero level in circuit 70 with the element NOT 151. The third input receives a single level from the zero output of trigger 135. Based on these levels, the AND element 148 implements a single level, which is transmitted through the OR element 155 to the input shaper 138. The operation of block 16 (Fig. 1) described before connecting to the shaper 138 (Fig. 5) is further carried out in the same way as in this case.

The pulse from the output of the shaper 140 after a certain delay in the delay element 154 along the circuit 100 is fed to the clock input of the register 82 (Fig. 3) and organizes the recording of the decryption result of the received command in the register. Formed

1203531 46 by the shaper 138 (Fig. 5), the pulse sets the trigger 134 to a single state, and the pulse generated by the shaper 139 after a delay in the delay element 153 sets the trigger 135 to a single state and enters the circuit 97. This circuit enters the node 97 77 (FIG. 3) and resets trigger 116 (FIG. 4). With the reset of the trigger 116 in the described sequence, the issuance of the second computer addresses and signal Address from the subscriber stops.

With the installation of the trigger 135 (Fig. 5), the node 79 is connected to the operation (Fig. 3). The single level from the single output of the trigger 135 (Fig. 5) through the circuit 158 through the OR element 185 (Fig. 6) is supplied to the fourth input of the And 173 element, which with the arrival of this level begins to monitor with the help of the element NOT 180 the reset in the signal circuit 157 Management from the channel. With the reset of this signal, the And 173 element gives a single level. At this level, the driver 167 generates a single pulse, which sets the trigger 161 to a single state. The single level from the output of this trigger on the circuit 105 enters the buses 87 and 35 (Fig. 3). On the bus 35, he connects the switch 14 (Fig. 1) to issue to the second computer a status byte generated by the formulator 84 (Fig. 3). In the former 84 (Fig. 8) in this case, the second inputs of the elements AND 237-240 receive a single level, which gives the element NOT 241 based on the inversion of the zero level in the circuit 160 from the output of the trigger 137 (Fig. 5). At the first input of the element And 237 (Fig. 8) is supplied through the circuit 92 a single level from the output of the trigger

246 (Fig. 9). At the first input of the element And 238 (Fig. 8), a single level enters the circuit 159 from the output of the trigger 134 (Fig. 5). At the first inputs of the elements And 239 and 240 (Fig. 8) they get obtuse along the chains 193 and 194 Zero levels from the outputs of the triggers 164 and 165 (Fig. 6). As a result of this, the driver 84 (Fig. 3) implements the status sign in the status byte along the circuit 242 (Fig. 8) using the And 237 element Attention and along the circuit 243 using the And 238 element the Sign is busy.

1

On the bus 87 (Fig. 3), a single level from the output of the trigger 161 (Fig. 6) enters through the driver 85 (Fig. 9) as a control signal from the subscriber. Further, from the second computer to node 79 (Fig. 3), a signal is received via circuit 189 (Fig. 6). Information from channel5, on the basis of which element And 174 produces a single level. At this level, shaper 168 generates a single pulse. This pulse resets the trigger 161 and sets the trigger 162 to a single state. With the reset of the trigger 161, the device stops issuing the status byte and the control signal from the subscriber to the second computer.

A single level from a single output of the trigger 162 connects the elements to work. And 175-177. However, in this case, the And 175 element is blocked by a zero level in the circuit 160 from the output of the trigger 137 (Fig. 5), and the And 177 element (Fig. 6) is blocked by the zero level from the output of the HE 182 element, which inverts a unit level ^{in the} circuit 159 from the output trigger '134 (Fig. 5). The same level goes to the third input of the AND 176 element (Fig. 6) .. The fourth input of this element receives a single level from the output of the HE 183 element, which inverts the zero level of the circuit 160. The I 176 element remains unblocked. The driver 170 produces a single pulse. This pulse sets the trigger 163 to a single state, resets the trigger 162 through the OR element 187, through the element OR, 186 sets the trigger 165 to the single state and enters the circuits 103 and 76 through the OR 184 element. It enters the node 77 through the circuit 103 (Fig. 4), then to the node 78 (Fig. 5) and the driver 85 (Fig. 9) In these nodes, this pulse resets the triggers 114, 115, 117 (Fig. 4) 134, 135, 136 (Fig. 5) and 246 (Fig. 9). On the chain 76, it enters the block 17 (Fig. 2), where it confirms the zero state of the trigger 61. With the reset of the trigger 115, the device stops issuing the Subscriber's work signal to the second computer. On this pic 15

He is using the element NOT 181 for resetting the Informakanal signal in the circuit 189. After this signal, the element And 176 is the unit level at which the sequence of signals of the initial sample given by the second computer ends. In the second computer, the device in the status byte reports that it is busy for processing the Control command and indicates with a sign Attention that it is necessary to carry out actions to process the command received by the device from the first computer. The type of this command is determined by the second computer by the address АЗ ^ transmitted to it in the described sequence of signals and stored in the computer in the table of correspondence of addresses to commands. In this case, after removing the employment of the second computer, it is also not necessary to issue a command Refine the command byte. The specified task, the node 79 (Fig. 3) of the block 16 (Fig. 1) carries out using ^ triggers 163 and 165 (Fig. 6), set to a single state when processing a sequence of signals.

A single level from the output of the trigger 163 goes to the second input of the And 172 element. The first input of this element receives a single level in the period when the element NOT 179 determines the absence of the Sampling signal from the channel in the circuit 130 of the bus 27. During this period, the element And 172 gives a single level, '' which the shaper 85 enters through the circuit 188 of the bus 87 (Fig. 3). Here, through the OR element 248 (Fig. 9), it enters the second input of the And 247 element. At its first input, the unit level from the output of the element DOES NOT determine the zero level in the circuit 129 of the OR bus 128 (Fig. 4) from ditches 113 and 115. As a result, the element And 247 (Fig. 9) gives a unit level. This level on the circuit 91 of the bus 33 (Fig. 1) through the node 6 at the output 27 enters the second computer as a signal Request from the subscriber. At the same time, the unit level from the output of the element And 247 (Fig. 9) through the circuit 91 is supplied to the first input of the element And 123 (Fig. 4) of the node 77 (Fig. 3). The third input of the And 123 element (Fig. 4) receives a single level from the output of the element NOT 127, which determines the absence of the Address signal from the channel in the circuit 131. In this state, the And 123 element monitors the appearance of the Sampling signal from the channel. Next, the operation of block 16 (Fig. 1)

249, which level, 86 through the exits by tread the trigger element

1 is carried out in the same way as when connecting the device to a second computer on his own initiative to issue a sign Warning, the difference lies in the contents of the issued status byte. If in the first case a status byte with the Attention flag is issued, which forms the And 237 element (Fig. 8) based on the unit level coming along the circuit 92 from the single output of the trigger 246 (Fig. 9), then in this situation, the driver 84 (Fig. 3) using the element And 240 (Fig. 8) gives the sign of VU finished on the basis of a single level, coming through the circuit 194 from the output of the trigger 165 (Fig. 6). After completing this sequence of signals, block 16 (Fig. 1) returns to its initial state and is ready to accept the Read command with address Α3 _ί6 from the second computer.

With a very frequent exchange through the device, situations are possible where, when two computers simultaneously access the device, the latter determines the correspondence of addresses and commands when receiving commands. For example, when receiving the Write command from the first computer while tracking address 93 from the second computer, the device receives the Read command when tracking address A3 ₁₆ . In this case, block 15 (FIG. 1) operates as indicated. Block 16 works similarly. Their work differs only in that in the node. 78 (Fig. 3) of block 15 (Fig. 1), trigger 137 (Fig. 5) sets the signal from the output of element And 144, and in a similar unit of block 16 (Fig. 1), trigger 137 (Fig. 5) is installed using the element And 143 and shaper 141. At the first input of element And 143, a single level is supplied along circuit 72 from the single output of trigger 60 (Fig. 2), to the second input from the output of trigger 136 (Fig. 5), to the third input, along circuit 70 s the output of node 59 (Fig. 2), which determines the correspondence of addresses in registers 52 and 54, to the fourth input from the zero output of trigger 135 (Fig. 5), to the fifth input, through circuit 112 from the output of node 83 '(fi . 3), which defines the correspondence received from the two teams computers. As a result of this, the element And 143 (Fig. 5) gives a unit level at which the shaper

531

141 forms a single pulse.

This impulse sets trigger 137 to a single state.

In addition, in the node 79 (Fig. 3) of the block 15 (Fig. 1), the element And 178 (Fig. 6) is connected to the work by a single level, which is supplied through the circuit 72 from the single output of the trigger 60 (Fig. 2). Based on this, the element And 178 (Fig. 6) transmits a pulse from the output of the driver 169 to the circuit 9Q. This pulse enters the former 85 (Fig. 3) of the block 16 (Fig. 1) and sets the trigger 246 to a single state. At the node 79 (Fig. 3) of the block 16 (Fig. 1), the And element 178 (Fig. 6) in in this case, it is blocked by the zero level coming in through the circuit 74 from the single output of the trigger 61 (Fig. 2). As a result of this, a metal pulse from the output of the shaper 169 (Fig. 6) does not carry out these actions.

When issuing status bytes in a computer, blocks 15 and 16 (Fig. 1) provide, due to the single states of triggers 137 (Fig. 5), the formation of zero status bytes. A single level from the output of flip-flop 137 through the circuit 160 enters the former 84 (Fig. 3) and, after inverting with the element HE 241 (Fig. 2) a zero level, blocks the operation of the And 237240 elements. Regardless of what is in block 16 (Fig. 1) the input of element And 237 (Fig. 8) through circuit 92 receives a single level from the output of trigger 246 (Fig. 9), the blocked elements in both blocks in circuit 242-245 give zero levels, which indicates the absence of all signs. Otherwise, the initial sampling, data exchange, termination of the exchange is carried out in the described sequence.

Thus, for the proposed device, three basic commands are enough: Write, Read, Control. The need for a command Refine a command byte completely disappears. For computers when working with the proposed device to exclude the use of the Refine command byte command, there is no need to temporarily coordinate the exchange through the device. Information about the type of command and its modification is transmitted in the address code. This is ensured by the ability of the device to respond to a group of addresses and determine the correspondence of addresses received from two computers.

The proposed device responds to a group of 16 addresses. If for compiling a table of correspondence of addresses to commands they are not enough, then you can easily expand them by reducing the capacity of nodes 9 ~ 12 (Fig. 1) and simultaneously increasing the capacity of U registers 52-54, nodes 58 and 59, and

1203531 52 of the switch 68 (Fig. 2). Given that the codes of the commands Write MMMMMMM 01, Read -MMMMMMM 10, Control - MMMMMMM 11, where M is 5 bits of modification, then the bits of nodes 9-12 (Fig. 1) can be set to two, and the bits of registers 52-54 (Fig . 2), nodes 58 and 59 and switch 68 - equal to six .-. 'In this case, the correspondence tables contain 1 maximum number of commands.

Figure 1

Fig 2

Fie. 5

Fig b

1203531.

7

^{FIG. 8} FIG. 9

FIG. YU

Claims (2)

one first and second address generation nodes are connected to the second groups of information inputs of the first and second address comparison nodes and groups of control inputs of the first and second switches, respectively, the second groups of information outputs of the first and second exchange signal generation blocks with the second groups of information inputs of the second and the first block of forming the exchange signals, respectively, characterized in that, in order to reduce the time of exchange of control information, a block of analysis of the corresponding addresses, the first and second outputs of which are connected to groups of control inputs of the first and second switches, respectively, the first and second inputs of the address matching block are connected to the output groups of the third and fourth nodes of the amplifiers of the block receivers, respectively, the first five and second groups of outputs of the address matching block are connected with the second groups of control outputs of the first and second blocks of the formation of exchange signals, respectively, the second groups of control outputs of which are connected to the first oh and the second group of inputs of the address analysis block 2. The device according to claim 1, characterized in that the address analysis block contains three registers, two comparison nodes, a switch, two triggers, three delay elements, a single pulse generator, two AND elements, two NOT elements, an OR element, and the first register is connected to the first inputs of the first and second comparison nodes and is the first and second outputs of the block, the information inputs of the second and third registers are the first and second inputs of the block, respectively, the single output of the first trigger and the output of the first node a comparing unit to form a first group of outputs, a single output of the second flip-flop and the output vto1 the second comparison node forms the second group of outputs of the block, while the single outputs of the first and second triggers are also connected to the second and first groups of outputs of the block, respectively, the sync input and the zero input of the first trigger and the sync input and the first zero input of the second input , while the sync inputs of the first and second triggers are connected to the sync inputs of the second and third registers, respectively, the output of which is connected with the second input of the second comparison node and the first information input of the switch, the second information input connected to the second input of the first comparison node and the output of the second register, the single output of the first trigger is connected to the first input of the OR element, the first input of the first AND element, and the first control input of the switch, the output of which is connected to the information input of the first register, the synchronization connected to the output of the second element I, the first input of which is connected to the output of the first element NOT whose input is It is united with the output of the first element I and the input of the first delay element, the output connected to the input of the single pulse generator, the output of which is connected to the second zero input of the second trigger, the single output connected to the second control input of the switch, the second input of the first element I and the second input the OR element, whose output is connected to the input of the second delay element, the output connected to the second input of the second element AND, and the input of the third delay element whose output is connected to the input of the second ele cient NOR output connected to a third input of the second AND gate, the zero output of the first flip-flop is connected to data input of the second flip-flop, the zero output of which is connected to the data input of the first trigger. The invention relates to computer technology and can be used in two computer systems for organizing me and an information exchange. The purpose of the invention is to reduce the time for the exchange of control information. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of the address analysis block; in fig. 3 is a block diagram of an exchange signal generation unit; in fig. 4 is a block diagram of the subscriber's Work node; in fig. 5 - block diagram of the command receiving node; in fig. 6 is a block diagram of a state byte output node; in fig. 7 is a block diagram of the exchange control node; in fig. 8 is a block diagram of a state byte former in FIG. 9 is a block diagram of a signal conditioner subscriber requirement; in fig. 10 is a block diagram of a single pulse driver. The device for data exchange (Fig. 1) contains four nodes 1-4 of receiver amplifiers, four nodes 5-8 of transmitter amplifiers, first and second 10 nodes forming the first 11 and second 12 address comparison nodes, the first 13 and second 14 switches, the first 15 and the second 16 blocks of forming the exchange signals and the block 17 of address correspondence analysis. Moreover, the inputs of the nodes 1-4 are connected respectively to the information and control inputs 18-21 of the device; the outputs of the nodes 5-8 are connected to the information and control outputs 22-25 of the device. The first control inputs of blocks 15 and 16 are connected by buses 26 and 27 respectively to the outputs of nodes 1 and 2, the first information inputs by buses 28 and 29 to the outputs of nodes 3 and 4, the inputs of the address recognition signal by chains 30 and 31 to the outputs of nodes 11 and 12, first control outputs by buses 32 and 33 with inputs of nodes 5 and 6, first information outputs by buses 34 and 35 with first inputs of switches 13 and 14, second information outputs by buses 36 and 37 with second information inputs of blocks 16 and 15. The output of the node 9 is connected to the bus 38 with the second information input of the node 11 and the second 5 ° 5 0 pbw input of the switch 13, the output of which is connected by bus 39 to the input of node 7. The output of node 10 is connected by bus 40 with the second information input of the node 12 and the second input of the switch 14, the output of which is connected by bus 41 with the entrance of node 8. The first information inputs of nodes 11 and 12 are connected respectively by buses 42 and 43 The outputs of nodes 3 and 4. The first and second inputs of block 17 are connected respectively by chains 44 and 45 to the outputs of nodes 5 and 4, and the first and second groups of inputs of block 17 are connected by buses 46 and 47 to the second blocks of control 1x of outputs of blocks 15 and 16, its first and second outputs by chains 48 and 49, with second inputs of switches 13 and 14, the first and second groups of outputs by buses 50 and 51, with second groups of control inputs 15 and 16. The address analysis block 17 (Fig. 2) contains three registers 52-54, three delay elements 55-57, the first 58 and second 59 comparison nodes, the first 60 and second 61 dynamic triggers, the first 62 and second 63 And elements, the first 64 and 65 second elements are NOT, a single pulse shaper 66, element 1-Ш1 67 and switch 68, the output of which is connected to the information input of the register 52. Moreover, the output of the register 52 is connected to the first inputs of nodes 58 and 59, chain 48 to the first and chain 49 with the second outputs of the block, the first and second inputs of which are connected respectively to the circuits 44 and 45 to the information inputs of the registers 53 and 54. The output of the register 53 is connected to the second input of the switch 68 and the second input of the node 58, the output of which is connected to the first circuit 69 of the bus 50 connected to the first group of outputs of the block. The output of the register 54 is connected to the first input of the switch 68 and the second input of the node 59, the output of which is connected to the first circuit 70 of the bus 51 connected to the second group of outputs of the block. The first circuit 71 of bus 46 connected to the first group of block inputs is connected to the synchronous inputs of register 53 and flip-flop 60, the single output of which is connected to the first inputs of elements 62 and 67, the first control input of switch 68, the second circuit 72 of bus 50 and the third chain 72 bus 51, the first 73 bus circuit 47 connected to the second group of block inputs is connected to the synchronous inputs of the register 54 and the trigger 61, the unit output of which is connected to the second inputs of the elements 62 and 67, the second nodal collector input of the switch 68, the second circuit 74 of the bus 51 and the third circuit 74 of the bus 50. The second circuit 75 and 76 of the bus 46 and 47 are connected respectively to the zero input of the trigger 60 and the first zero input of the trigger 61, the output of the element 62 is connected through the delay element 55 and the driver 66 to the second zero input of the trigger 61 and through the element 64 with the first input of the element 63 w The input of which is connected to the output of the element 56 of the delay. The output of the element 67 through the elements 56 and 57 of the delay and the element 65 is connected to the third input of the element 63, the output of which is connected to the synchronous input of the register 52, the zero output of the trigger 60 is connected to the information input of the trigger 61, the zero output of which is connected to the information input ( trigger 60. Block 15 (16) of forming the exchange signals (Fig. 3) contains a signal output node 77 The subscriber’s operation command reception unit 78, output control state byte node 79, exchange control decoder node V, command decoder 81, command register 82, comparison unit 83, driver 84 bytes of state and signal generator 85 Requirement of a subscriber whose inputs are connected respectively by buses 86-88 and the first chain 89 (90) of bus 37 (36) with the first outputs of nodes 77, 79 and 80 and the second information group of inputs of the block, C the fourth outputs formativat 85 and 85 are connected respectively 91 and 9 by bus 32 (33) and circuit 93 (94) with the first inputs of node 77 and shaper 84, the first output of the block and the second chain of bus 36 (37) connected to the second group of information outputs of the block, the first group of control inputs of which bus 26 (27) is connected to the second input of the node 77 and the first inputs of the nodes 78-80. The first group of information inputs of the block bus 28 (29) connected to the first input of the decoder 81 and the third circuit of the bus 36 (37). Signal block address identification signal input 203531 4 30 (31) is connected to the third input of node 77. From the second to the fourth outputs of node 77, they are connected by bus 95, chains 96 and 71 (73) .J, respectively, to the second input of node 78 and the first tires 34 (35) and 46 ( 47), connected respectively to the first group of information and the second group of control outputs of the block, the second 10, a group of control inputs of which are connected by bus 50 (51) to a third input of node 78 and a second input of node 79. The outputs of node 78 are connected, respectively, by chains 97, 99, 100 and (5 bus 98 with a quarter input of the node 77, the third input of the node 79, the second input of the decoder 81 and the synchronous input of the register 82, the output of which is connected to the second input by bus 101 (102) 20 of the node 80, the first input of the node 83 and the fourth circuit of the tire 36 (37); From the second to the seventh outputs of the node 79 are connected respectively by a chain 103, a bus 104, chains 105, 75 (76) and 25 90 (89) and the bus 106 with the fifth input of the node 77, the third input of the node 80, the second chain of the bus 34 (35), the second chain of the tire 46 (47), the first chain of the tire 36 (37) - and the second input of the form. d the pad 84, the output of which is connected to the third circuit 107 of the bus 36 (35). Second to fourth node outputs 80 are connected respectively by bus 108, a chain 109 and a length of 110 (111) with the fourth input of node 79, the fourth chain of bus 34 (35) and fifth tire chain 36 (37). The fourth 102 (101), the first 111 (110) and the third 29 (28) bus circuits 37 (36) are connected respectively to the second input of the node 83,  the fourth input of node 80 and fifth chain tires 34 (35). Decoder output 81 connected to the information input of the register 82. The output of node 83 by the circuit 112 connected to the fourth input of node 78.  A second circuit 94 (93) of bus 37 (36) is connected to the fifth input of node 80. The node 77 of the signal The subscriber operation (Fig. 4) contains triggers 113-117, fibrators 118-121 night pulses, elements AND 122-125., The first 1.26 and second 127 elements NOT and the element OR 128, the output of which is connected to the first input is evil ment And 122 and the first chain 129 tires 55 86 connected to the first output node. Moreover, the first input of the UEL circuit 91 is connected to the first input of the element I 123, the output of which through the driver 118 is connected to, a single input of the trigger 113. The first circuit 130 of the bus 26 (27) connected to the second input of the node is connected to the first input of the element AND 124, the second input of the element 123 and through the element HE 126 to the first input of the element 125, the output which through the driver 119 is connected to a single input of the trigger 114 and the chain 71 (73) with the fourth output node. The second circuit 131 bus 26 (27) is connected to the second input element And 125 and through the element NOT 127 to the third input element And 123 and the second input element And 122-, the output of which through the imager 121 is connected to the single inputs of the trigger 116 and 117. The third and The quarter inputs of the node are connected, respectively, by chains 30 (31) and 97 to the third input of the element AND 125 and the zero input of the trigger 116, the output of which by circuit 96 is connected to the second circuit of the bus 86 and the third output of the node. The fifth input of the node by the chain 103 is connected to the zero inputs of the flip-flops 113, 114, 115 and 117, to the third circuit of the bus 86 and the first circuit of the bus 95 connected to the second terminal of the node. The output of the trigger 113 is connected to the second circuit 132 of the bus 95 and the first input of the element OR 128, the second input of which is connected to the output of the trigger 115. The output of the trigger 114 is connected to the second input of the element AND 124, the output of which through the driver 120 is connected to the single input of the trigger 115. The output trigger 117 is connected to the third circuit 133 of the tire 95. The command reception unit 78 (FIG. 5) contains, triggers 134-137, shapers 138-141 single pulses, elements AND 142-148, elements NOT 149-152, first 153 and second 154 delay elements, first 155 and second 156 elements OR , the outputs of which are connected through the respective shaper 138 and 139, respectively, with a single input trigger 134 input element 153 delay. The output of the delay element 153 is connected to the single input of the trigger 135 and the circuit 97 to the first output of the node. The third circuit 74 (72) of bus 50 (51) ,, connected to the third input of the node is connected to the first inputs of the elements 142 and 143 and through the element NOT 149 to the input of the element 144. The third chain 157 of bus 26 (27) connected 5 to the first input of the node is connected to the first input of the AND element 145, the output of which is connected to the first inputs of the AND elements 146 and 147. The first circuit 103 of the bus 95 connected to the second 10 input of the node is connected to the zero inputs of the trigger 134-137. The second circuit 132 bus 95 is connected to the second input element And 146 and through the element 150 to the second input element And 147, the output of which through the driver 140 is connected to the single-unit input of the trigger 136, the second input element And 144 and then through the element 154 delay circuit 100 with the fourth 0 output node. The third circuit 133 of the bus 95 is connected to the second input of the AND element 145. The trigger output 136 is connected to the first inputs of the elements 148 and 156, the second inputs of the And 142 and 143 elements, and the circuit 99 to the third output of the node. The first circuit 69 (70) of bus 50 (51) is connected to the three inputs of the And 142 and 143 elements and through the NOT 151 element to the second input of the And 148 element. The zero output of the trigger 135 is connected to the fourth inputs of the And 142 and 143 elements and the third inputs elements And 146-148. Single trigger trigger output 135 2 is connected to the first circuit 158 of the bus 98 connected to the second output of the node. The second 159 and third bus circuit 160 are connected to the outputs of the flip-flops 134 and 137, respectively. The fourth input of the node is connected by the circuit 112 to the fifth input of the AND 143 element and through the HE element 152 to the fifth input of the AND 142 element, whose output is connected to element input 5 OR 155. The output element And 143 through the driver 141 is connected to the first single input of the trigger 137, the second single input of which is connected to the output of the element And 144. Outputs g elements And 146 and 148 are connected respectively. stately. with the second inputs of elements OR 156 and 155. I The status byte output node 79 (FIG. 6) contains the triggers 161-166; 5 the formers 167-171 are single. pulses, elements AND 172-178, elements NOT 179-183 and elements OR 184-187. Moreover, the first tire chain 130 26 (.27) connected to the first input of the node is connected via the element NOT 179 to the first input of the element AND 172, the output of which is connected to the first circuit 188 of the bus 87 connected to the first output of the node. The third circuit 157 of bus 26 (27) is connected via the element NOT 180 to the first input of the element AND 173, the output of which is connected via the driver 167 to the single input of the trigger 161. The fourth circuit 189 of the bus 26 (27) is connected to the first input of the element And 174 and through the element HE 181 with the second input of the element AND 173 and the first inputs of the elements AND 175-177, the second inputs of which are connected to the single output of the trigger 162. The second circuit 12 (1 f) of the bus 50 (51) is connected to the first input of the element And 178 , the output of which is connected by a circuit 90 (89) to the sixth output of the node. A second third of the bus circuit 98 connected to the third input of the node is connected respectively to the first and second chain of the bus 106 connected to the seventh output of the node, the second and fifth outputs of which are respectively connected to the 103 and 75 (76) circuits by the ic output; STI item 184.First, the circuit 158 of bus 98 is connected to the first input of the element OR 185, the second input of which is connected via the first circuit 190 of the bus 108 to the fourth entry of the node. A second circuit 159 of the bus 98 is connected to the third input of the AND element 176 and through the element HE 182 to the third input of the element I 1,177. The third circuit 160 of the bus 98 is connected to the third input of the element 175 and through the element HE 183 with quarter inputs of the elements 176 and 177. The second circuit 191 of the bus 108 is connected to the single input of the trigger 164 and the first input of the element OR 186, the output of which is connected to the single input trigger 165. The trigger 161 output is connected to the fourth output of the node by the circuit 105, the second bus circuit 87 and the second input of the AND element 174, the output of which is connected via the driver 168 to the zero input of the trigger 161 and the single trigger input 162, the zero output of the trigger 162 is connected to the third input ale enta AND 173, the fourth and fifth inputs of which are connected respectively with the output of the element OR 185 to zero five 5 O 5 0 trigger output 166. At output of the element AND 175 through the driver 169 is connected to a single input of the trigger 166, the second input of the element AND 178 and the first input of the element OR 187, the output of which is connected to the zero input of the trigger 162. The output of the element AND 176 through the driver 170 is connected with the first input of the element OR 184, the second inputs of the elements 1 SHI 186 and 187 and the single input of the trigger 163, the output of which is connected to the second input of the element AND 172. The output of the element AND 177 through the driver 171 is connected to the third input of the element OR 187 , zero t ziggerov passages 163-166 and the first circuit 192 bus 104 connected to the third - the output node. The outputs of the flip-flops 164 and 165 are connected respectively to the third 193 and fourth 194 chains of the bus 106. The single output of the trigger 166 is connected to the second chain 195 (196) of the bus 104. The exchange control node 80 (FIG. 7) contains triggers 197-202, shapers 203-208 of single pulses, AND elements 209-219, OR elements 220-223, the first 224 and the second 225 elements are NOT. Moreover, the fourth circuit 189 of bus 26 (27) connected to the first input of the node is connected to the first inputs of elements AND 209 and 210 and through the element HE 224 to the first inputs of elements AND 211 and 212. The third chain 157 of bus 26 (27) is connected to the first the inputs of the elements 213 and 214, the outputs of which are connected respectively to the first and second input of the element OR 220. The first circuit 226 of bus 101 (102) connected to the second input of the node is connected to the first input of the element 215, the output of which is connected to the first input of the element OR 221. A second circuit 227 of bus 101 (102) is connected to the first input of the element AND 219. The output element And 219 is connected to the first input element OR. 222, the output of which through the driver 203 is connected to the first zero inputs of the flip-flops 197 and 198, the second circuit 191 of the bus 108 connected to the second output of the node, and the single input of the trigger 199 whose output is connected to the first circuit 190 of the tire 108. The third circuit 228 of the bus 101 (102) is connected to the first input of the element 216, the output of which is connected via a single input 204 to a single input of the trigger 197. The second circuit 195 (196) of the bus 104 connected to the third input of the node is connected to the first circuit of the bus 110 (.111), connected to the fourth output of the node, and the first input element And 217, the output of which is connected to the second inputs of the elements 215 and 216. The first circuit 192 of the bus 104 is connected to the first zero inputs of the trigger 200 and 201 and the zero inputs of the trigger 199 and 202. First 196 ( 195), the second is 229 (230) and the third is 231 (232) of the bus circuit 111 (110) connected to the fourth input at the node, they are connected respectively to the second input of the AND element 217 and the third inputs of the AND elements 215 and 216. The fourth circuit 233 (234) of the bus 111 (110) is connected to the first input of the AND element 218, the output of which through the imaging unit 205 is connected to a single input the trigger 200 and the second zero input of the trigger 198. The 235 (236) bus circuit 111 (110) is connected to the second input of the OR element 222 and through the HE element 225 with the second inputs of the AND 211 and 212 elements. (93) is connected to the second input element And 219. The output of the trigger circuit 197. 109 is connected to the third output of the node, the second inputs of the elements AND 209 and 213, and the first input of the element OR 223, the output of which is connected by bus 88 to the first output of the node. The output of the trigger 198 is connected to the second inputs of the elements AND 210, 214 and the element OR 223. The output of the trigger 200 is connected to the third input of the element 211, the output of which is connected to the second input of the element OR 221. The output of the trigger 201 is connected to the fourth circuit 234 ( 233) bus 110 (111) and the third input element And 212, the output of which through the shaper 20b is connected to the second zero input of the trigger 201. The zero output of the trigger 202 is connected to the second circuit 230 (229) of the bus 110 (111). The output element And 209 through the shaper 207 is connected to the second zero input of the trigger 197 and one, the second inputs of the flip-flops 201 and 202. The output of the element And 210 is connected to the second input of the element And 218 and the third circuit 232 (231) Shiky 110 (i11}. The output element OR 220 connected to the third input of the element 1/1 Ш 222 and the fifth chain 236 (235) spikes 1.10 () and the output of the element OR 221 through shaper 208 is connected to a single input trigger trigger 198 and the second zero input trigger 200, The 84 state byte shaper (FIG. 8) contains AND 237-240 elements and an HE element 241. Moreover, the first input of the node is connected by a circuit 92 to the first input of an AND 237 element, the output of which is connected to the first chain 242 of the bus 107 connected to the node. The first 159s, the third 193, and the fourth 194 of the bus circuit 106, connected to the second input of the imager, are connected respectively to the first inputs of the AND 238-240s elements whose outputs are respectively connected to the chains 243-245 of the composite chain 107. The second circuit 160 of the bus 106 through the HE element 241 connected to the second inputs of the elements And 237-240. Shaper 85 signal Requirement of the subscriber (Fig. 9) contains a trigger 246, element AND 247j element IlTTPi 248 and element NOT 249, Moreover, the first circuit 129 of bus 86 connected to the first input of the driver is connected to the first circuit of bus 32 (33) 5 connected to the third output the driver, and through the element NOT 249 with the first input of the element Pi 247, the code of which is connected to the first output of the driver and the second circuit of the bus 32 (33) by a circuit 91. The second circuit 96 of the tire 86 is connected to a tr, a chain of bus 32 (33). The third circuit 103 of the bus 86 is connected to the first zero input of the trigger 246, the unit output of which is connected to the second output of the driver and the first input of the OR element 248. The first circuit of the bus 87 connected to the second input of the driver 87 is connected to the second input of the OR 248 element the output of which is connected to the second input of the element 247. The second circuit 105 of the bus 87 is connected to the fourth circuit of the bus 32 (33). The third driver circuit 88 is connected to the bus circuit 32 (33) and the second zero input trigger 246. The fourth driver input circuit 89 (90) is connected to the single trigger input 246, zero output The first chain 93 (94) is connected to the fourth output of the farmer. Single pulse shaper. (Fig. 10) contains J for example; the element And 250, the element NOT 251 and the element 252 delay. Moreover, the input of the imaging unit is connected to the input of the delay element 252, the first and second outputs of which are connected respectively to the first and through the element NO 251 to the second inputs of the AND 250 element The device works as follows. Inputs 18 and 20 and outputs 22 and 24 of the device are connected to the first computer, inputs 19 and 21 and outputs 23 and 25 to the second computer. Based on the codes generated by nodes 9 and 10, the proposed device allows the first computer to access it by one of the groups addresses starting with address 10010000 and ending with address 1001111, and the second computer, respectively, from address 10100000 at address 10101111. Next, in order to reduce the records of binary records, binary codes are written in hexadecimal codes. The operation of the proposed device as well as the known one is possible only in the system: one computer - device - second computer, the proposed and known devices require coordinated actions from two computers. Any information transmitted through the adapter has a certain direction of transmission and its specific purpose. The direction of information transfer is determined by the type of command, and the purpose of the information is determined by the value of the command modification bits. To solve these problems, each computer has special programs. In a system with a known adapter, these programs solve the indicated tasks after receiving the command code in response to the Refine command byte command. In the system with the proposed device, these programs are based on the address matching tables with the instructions for accessing the device. For example, the program in the first computer has the following table of correspondence; address 90;:, corresponds to the command Write with code 0 in the modification bits; address - command Write with code 1,, g;, adress 03S3112 su 92 - command Write with code 2; address 93 - the command Write with code 3.,; address - the command Count with code О; ad-e pehy 95 - command Count with code 1,; address. 9b - the command Count with code 2,; address 97 - command Read with code 3; Address 98 - Management team 10 with a code of 0.6 for the second computer; address 99 -, Management command with the code for the second computer; address 9A. (6 - Management command with code 2, for the second computer; address 9B - coman. 15 Control with code 3 for the second computer; address, - Management command with code O ,,, from the second computer; 9D - command Management with code 1 | from the second computer; 20 to address 9Е - Management command with code 2 from the second computer; address, - command. Control - with code 3 from the second computer; Program in the second computer in this 25 case has the following correspondence table: to the address of the joint-stock company, the corresponding command is Read with code 0, in the modification bits; address A1 .. - command Read with code 1; address 30 command Read with code to address AZ - command Read with code; address-A4 - command Write with code 0; A5 address - command Write with code 1,; 2 to address A6 - the command Write with code 2; address AU team Write with code Z.); Address AS com Anda Management with code, -ot. first computer; address A9i6 - team Q Management with code 1 from the first computer; Address AA /) Management command with code 2 | b, from the first computer; ABig address - Management command with the code from the first computer; address 5 Control command with code 0 for the first computer; the AD address is the Management command with code 1 for the first computer; the address .. is the Control command with the code for the first computer; and the address U is the Control command with the code 3, for the first computer. Suppose that in the course of operation of the first computer, an error arises: transferring an array of information to the second computer. The purpose of this information corresponds to code 3, in the command modification bits. Organizing exchange through the device, the program of the first computer determines that it is necessary to issue a Write command with a code in the modification bits of the command, and, based on the described table, issue it to the address. The device receives this address via input 20 (Fig. 1), and input 18 through node 1 and further along circuit 26 to block 1.5 receives the identification signal Address from the channel. The higher bits of the received address are transmitted through the node 3 and further along the chain 42 to the node 11, where the data of the address bits are compared with the device’s own address, which specifies the node 9. At the same time, the lower bits of the received address from the output of the node 3 go through the circuit 44 block 17 to the information input of the register 53 (Fig. 2). Since the higher bits of the received address (code) correspond to the device address (code 9), the node 11 (Fig. 1) generates an address recognition signal in the circuit 30. Based on this signal and the signal Address from the channel received through circuit 131 (FIG. 4) from bus 26, AND 125 of node 77 (FIG. 3) of block 15 (FIG. 1) generates a single level, on the leading edge of which the driver 119 (FIG. 4) produces a single pulse as follows. When a single level driver is applied to the input, similar levels appear first on nepBOMs and then on the second outputs of delay element 252 (Fig. 10). Since the occurrence of these levels is separated in time, unit levels are present at the inputs of the AND 250 for some time, and hence a unit level is established at its output and output of the former. By the end of the total front-edge delay time, the unit level from the second input of the delay element 252 after the element NE 251 is inverted by the zero level arrives at the second input of the AND element 250, which then stops producing a single level at the output of the imager. So, on the leading edge of a single level entering the input, the driver generates a single pulse. All work in a similar way. 0353-, other shapers single pulses. The impulse formed by the shaper 119 (Fig. 4) sets 5 to one state the trigger 114 and along the chain 71 from the bus 46 (Fig. 3) enters the block 17 (Fig. 1). Zdeg he puts the lower bits of the address (code 3) in the register 53 (Fig. 2) and 10 sets to one state the trigger 60, since its information input receives a single level from the zero output of the trigger 61, which is in the initial, 15 zero state. After that, the unit level from the unit output of the trigger 60 permits the passage through the switch 68 of the contents of the register 53 to the information 20 input register 52, and also enters through the element OR 67, then through the element 56 of the delay at the second input element And 63s on the first and third inputs of which at this time present 5 levels of unit. At the second input, the unit level arrives after inverting the zero level from the output of the And 62 element blocked by the zero level from the single output of the trigger 61. At the third input of the K 63 element unit there is a certain time equal to the delay time of the leading edge of the unit level in the delay element 57. As a result of this element And 63 generates a signal, which enters in the register 52 code 3, received at its information input. The delay element 56 delays the arrival of the signal from the output of the element 63 at the moment of arrival of the specified code to the information input of the register 52. After this, the same codes 3 are received at the inputs of the node 58, and it determines their equality and outputs a unit level o five 0 five The next stage of the initial sample is the arrival at the entrance 18 (FIG. 1) through node 1 via bus 26 and further to node 77 (FIG. 3) of block 15 (FIG. 1) via circuit 130 (FIG. 4) to the first input of signal sample I 124 from the channel. To the second entrance This element receives the unit level from the output of the trigger 114. As a result, the element And 124. produces a single level on the basis of which shaper 120 produces a single pulse. This pulse sets the trigger 115 to one state. The unit level from the output of this trigger through the OR element 128 enters the input of the element AND 122 and the circuit 129 of the bus 86 (Fig. 3) to the imager 85, where the bus 32 (Fig. 9) is supplied as a signal The subscriber’s work through the node 5 (Fig 1) and then exit 22 in the first computer. Next, the node 77 (Fig. 3) of block 15 monitors the reset of the Address signal from the channel using elements 122 and 127 (Fig. 4). After resetting the signal from the channel, the element NOT 127 generates a unit level, which is fed to the second input of the element 122. The first input of this element has already received a unit level from the output of the element OR 128. The element I 122 forms a unit level at which shaper 121 gives a single pulse. This impulse sets the triggers 116 and 117 to one state. The unit level from the output of the trigger 116 along circuit 96 from bus 34 (Fig. 3) enters switch 13 (Fig. 1). Based on this level, the commentator 13 outputs the code 9, generated by node 9 5 as the high bits of the address code, and as the lower bits of the address code, code 3 ,, which enters via circuit 48 from register 52 (Fig. 2) of block 17 ( Fig. 1). Code 93 composed in the manner described at the switch 13 output;) via circuit 39 through node 7 to output 24 as the device address code is transferred to the first computer. Simultaneously, the specified level from the output of trigger 116 (Fig. 4) via circuit 96 from bus 86 enters shaper 85 (Fig. 3), where bus 32 (Fig. 9) and then through node 5 (Fig. 1) on output 22 as the accompanying code of the device address signal the Address signal from the subscriber enters the first computer. A single level from the output of the trigger 117 (Fig. 4 along the circuit 133 of the bus 95 enters the node 78 (Fig. 3) and connects it to work The next step in the initial sampling is to receive a command from the first computer. The command code at the input 20 (Fig. 1) through the node 3 and further along the chain 28 enters the first input of the decoder 81 (Fig. 3) of the block 15 five , .. five five 0 (Fig. 1). This command code accompanies the control signal from the channel, which via input 18 through node 1 and further along bus 26 enters block 15. The control signal from the channel via circuit 157 (fig. 5) bus 26 receives at node 78 (fig 3) element 145 (fig. 5), which by that time was connected to operation by a single level along the circuit 133 of bus 95 from the output of trigger 117 (fig. 4) of node 77 (fig. 3). As a result, the unit level from the output of element AND 145 (Fig. 5) enters the first input of element AND 147. The second input of this element receives the unit level after the NE element 150 inverts the zero level received by node 7S via the chain 132 circuit 95 from the output in the initial (zero) state of the trigger 113 (Fig. 4) of the node 77. At the third input of the element 147 (Fig. 5), a single level arrives from the zero output in the initial (zero) state of the trigger 135. Based on these levels, the element And 147 gives the unit ur the ram along which shaper 140 forms a single pulse. The . the impulse sets the trigger 136 to the single state and after the passage of the AND 144 trigger 137. The passage of this signal through the AND 144 provides a single level that arrives at the first input of the AND 144 after inverting the HE 149 element of the zero level obtained through the circuit 74 tires 50 from the exit in the initial zero state of the trigger 61 (figure 2} of node 17 (figure 2). The unit level from the output of the trigger 136 (FIG. 5) goes through circuit 99 to the second input of the decoder 81 (FIG. 3) and connects it to work. The result of decoding the received command enters the information input of the register 82. A single pulse from the output of the imaging unit 140 (FIG. 5) through the delay element 154 and further along the chain 100 enters the synchronous input of the register 82 (FIG. 3) and records the result of the command decryption into the register. The interpreted command from the output of the register 82 goes to the first input of the node 83, to the second input of the node 80 through the chain 101 of the composite circuit 36 (Fig. 1), to the second input of the node 83 one (Fig. 3) of block 16 (Fig. 1). In addition, a single level from the output of the trigger 136 (Fig. 5) enters through the OR element 156 to the input of the imaging unit 139, which forms a single pulse through it. This pulse after a delay in the delay element 153 sets the trigger 135 and enters the node 77 through the circuit 97 (FIG. 3) where the trigger 116 (FIG. 4) resets. Resetting the trigger 116 means stopping the device from issuing to the first computer using switch 13 (FIG. 1) through circuit 39 through node 7 on output 24 of the address code and using shaper 85 (FIG. 3) through circuit 32 (FIG. 1) and beyond through node 5 on signal output 22 Address from the subscriber. With the installation of the trigger 135 (FIG. 5), the unit level from its single output along the circuit 158 from the bus 98 enters the node 79 (FIG. 3) and connects it to the works The last stage of the initial sampling is the output of a state byte by the device to the first computer. This work in the device is performed by the node 79 of the block 15 (Fig. 1). The unit level from the output of the trigger 135 (FIG. 5) along the circuit 158 of the bus 98 at the node 79 (FIG. 6) enters through the OR element 185 to the fourth input of the AND element 173. The third and fifth inputs of this element receive the unit levels from the zero outputs being in the initial (zero) state, respectively, of the flip-flops 162 and 166. At the second input of the AND element 173, the unit level comes from the output of the HE element 181, since its input through the circuit 189 of the bus 26 and further through the node (Fig. 1 a) on input 18 does not come from the first computer signal Information from the channel. In this state, the element T73 (Fig. 6) monitors the signal drop. Control from the channel that comes from the first computer via input 18 (Fig. 1) through node 1 via the composite circuit 26 and further in block 15 at node 79. In this node, the named signal along the circuit 157 (Fig. 6) through the element NOT 180 enters the first input of the element AND 173. After the signal is reset, the control from the channel, the NOT 180 element forms a single level, as a result of which all the inputs of the And 173 element have single levels, on the basis of which it is s /; j o j g five " 0 3Vi " level. At this level, the driver 167 forms a single pulse that sets the trigger 161. A single level from the output of the trilg 161 through the bus circuit 105 of the bus 34 (FIG. 3) enters the switch 13 (FIG. 1) and enables the transfer of the status byte that the driver generates 84 (Fig. 3). In this case, the specified driver on the circuit 160 (FIG. 8) of the bus 106 receives a unit level from the output of the trigger 137 (FIG. 5) of the node 78 (FIG. 3). In the former, the described level, after the element 241 is inverted by the element HE, goes to the second inputs of the elements AND 237-240 and blocks their operation. As a result, these elements, respectively, along the chains 242-245 of the bus 104, which in turn is connected to the bus 34 (FIG. 3), output zero levels to the switch 13 (FIG. 1). This means that the switch 13, circuit 39, through node 7, on output 24, issues a state byte of one zeros. Simultaneously, the unit level from the trigger trigger 161 (Fig. 6) through the bus circuit 105 105 enters the driver 85 (Fig. 3), where without conversion via bus 32 (Fig. 9) through node 5 (Fig. 1), The output 22 is transmitted to the first computer as a control of the state byte signal of the control from the subscriber. After that, the node 79 (Fig. 6) enters the state of suspicion of the response signal from the first computer. This signal will be the Information signal from the channel, which is fed to input 18 (Fig. 1) through node 1 via bus 26 to block 15 and informs it of the receipt of the status byte. In block 15 (FIG. 3), this signal enters node 79, where, through circuit 189 (FIG. 6), an AND 174 element is connected to operation. The second input of this element receives a unit level from the output of trigger 161. As a result, AND 174 element provides a single level at which shaper 168 generates a single pulse. This pulse resets the trigger 161 and sets the trigger 162 to one state. The zero level from the zero output of the trigger 162 blocks the further operation of the AND 1 element 73. The single level from the single output of the trigger 162 goes to the second inputs of the AND elements 175-177 After resetting the trigger 161 switch 13 (FIG. 1) on circuit 39 through node 7 and further on output 24 ceases to issue a state byte to the first computer, and driver 85 (FIG. 3) on circuit 32 through node 5 (FIG. 1) and on on output 22 —signal control from the subscriber Still in advance, after trigger trigger 137 (FIG. 5) is installed, a unit level from the trigger output along circuit 160 of bus 98 at node 79 (FIG. 6) is connected to operation element 175 and after inverting this level element HE 183 zero level blocked elements And 176 and 177. Next element AND 175 using the element HE 181 monitors the reset of the signal Infor aci on the channel. After the signal is reset, the HE element 181 outputs a single level, on the basis of which the AND element 175 also outputs a single level. At this level, the driver 169 forms a single pulse. This impulse in node 79 sets the trigger to the single state .166, enters the second input of the element AND 178, and through the element OR 187 resets the trigger 162. At the first input of the element AND 178 receives a unit level from the trigger set to the single state 60 (FIG. 2) along the circuit 72 of the bus 50 (FIG. 1). As a result, the element 11PI 178 (FIG. 6) permits the passage of a single pulse to the circuit 90 of the bus 36 (FIG. 3). This pulse enters the block 16 (Fig. 1) and sets to. shaper 85 (Fig. 3) trigger 246 (Fig, 9). Further operation of the device depends on the actions taken by the second computer. In this case, the following cases are possible: the second computer until the present, its time did not attempt to issue a command to the adapter; the second computer has now started issuing a command to address AC b; the second computer has now started to command the team at the address AZ, /. These cases are listed according to the likelihood of their occurrence. In the same context, they are considered. In the first case, all the schemes of block 1 (Fig. 1), except for trigger 246 (Fig. Are in the initial state. Triggers 113 and 115 (Fig. 4) have zero 5 0 5 5 o S five state Based on these conditions, the OR element 128 forms the zero level, which along the chain 129 of the composite circuit 86 enters the shaper 85 (Fig. 3) after the element is inverted by the HE 249 (Fig. 9) with a unit level at the first input of the AND 247 element. a single output of the trigger 246 through the circuit 92 enters the imaging unit 84 (FIG. 3) at the first input of the AND 247 element (FIG. 8), which is intended to issue an attribute. Attention. At the same time, the unit level from the unit output of the trigger 246 (FIG. 9) through the element OR 248 enters the second input of the element AND 247, with the result that the element AND 247 outputs the unit level. This level along circuit 91 connects to operation at node 77 (FIG. 3) element I 123 (FIG. 4), and via bus 33 (FIG. 9) through node 6 (FIG. 1) on output 23 enters the second computer as signal call subscriber. After analyzing the received signal, the second computer begins to produce a sequence of signals from the sample entered by the subscriber. For this purpose, this computer without issuing an address generates a signal Sample. No signal The address from the channel causes a zero level bus 27 in the circuit 131 (fig. 4), which blocks the operation of the AND 125 element and, after inverting the HE 127 element with a single signal, enters the inputs of the AND 122 and 123 elements. The signal Sampling input 19 (Fig. 1) through node 2 via bus 27 in block 16 enters node 77 (Fig. 3), where it is received by AND 123 on circuit 130 (Fig. 4). Based on this signal, AND 123 produces a unit level, according to which the shaper 118 forms a single pulse. This pulse sets the trigger 113 to one state. The unit level from the output of the trigger 113 through the circuit 132 of the composite circuit 95 at node 78 (FIG. 3) goes to the second input of the AND 146 element (FIG. 5) and through the HE 150 element blocks the operation of the element And 147. In addition, this level from the output of the trigger 113 (Fig. 4) through the element OR 128 through the circuit 129 Igin 86 in the driver 85 (Fig. 3) without conversion as a signal. The subscriber’s operation enters the bus 33 (Fig. 9), And through the element NOT 249 blocks the operation of the element AND 247. As a result, this element And 247 stops issuing the unit ur lamb This means that along circuit 33 through node 6 (FIG. 1) at output 23, driver 85 (FIG. 3) stops issuing the Subscriber's Requirement signal to the second computer and starts issuing the Subscriber’s Work signal. This is followed by the issuance by block 16 (Fig. 1) to the second computer of the adapter address. This operation in block 16 is performed by node 77 (FIG. 3), by analogy with issuing by the corresponding node of block 15 (FIG. 1) the adapter address to the first computer at the initial sampling. In node 77 (fig. 3) of block 16 (fig. 1), the element AND 122 (fig. 4) receives at the first input a unit level from the output of the element OR 128. Since the second computer did not receive the signal Address from the channel. 19 (FIG. 1), instead of this signal, through node 2 via bus 27 and later in block 16, node 77 (FIG. 3) receives a zero level, which in node 77 via circuit 131 (FIG. 4), after the element 127 has been inverted unit level at the second input element And 122. As a result, the element And 122 produces a single foven, according to which the imager 121 forms a single pulse. This impulse sets triggers 116 and 117 to single states. The unit level from the output of trigger 116 along circuit 96 of bus 35 (Fig. 3) enters switch 14 (Fig. 1). On the basis of this level, the switch 14 outputs the code A (, generated by node 10, as the leading bits of the address and as the lower bits of the address code 3,: which enters the switch via the chain 49 from the recorder 52 (Fig. 2) of the block 17 (FIG. 1). Composed in the manner described at the output of the switch 14, the address of the AZ via the circuit 41 through the node 8 to the output 25 enters the second computer.At the same time, the specified level from the output of the trigger 116 (FIG. 4) via the circuit 96 of the tire 86 enters to shaper 85 (Fig. 3, where, without conversion via bus 33 (Fig. 9), and then through node 6 (Fig. 1) to exit 23 ak soprovozhg device address code signal 20353122 Address: from the subscriber enters the second computer. A single ramp level from the output of the trigger 117 (FIG. 4) along the circuit 133 of the bus 95 enters the node 78 (FIG. 3) and 5 connects it to work. In response to the transmitted address, the device in the sequence being ordered receives from the second computer a control signal from the channel. This signal 10 through input 19 (FIG. 1) through node 2 via bus 27 and later at node 78 (FIG. 3) of block 16 (FIG. 1) via circuit 157 (FIG. 5) enters element And 145. This input is given to the second input element ) 5 receives on the circuit 133. The unit level from the output of the trigger 117 (Fig. 4). As a result, AND 145 (Fig. 5) introduces a single level to the first input of AND 146. On 2Q the third input element And 146 arrivals-. There is a single level from the zero output in the initial (zero) state of Trigger 135. Based on the data of the levels and level that previously arrived at the second input through the circuit 132 from the output of the trigger 113 (Fig. 4), the And element 146 (Fig. 5) gives the unit level, which is through the element OR. 156 enters on The 2Q input of the driver 139. The single pulse formed by this driver, after a delay in the delay element 153, sets the trigger 135 to one state and enters the node 77 (Fig. 3), where it flushes the trigger 116 (Fig. 4). Resetting the trigger 116 means termination of the adapter from the second computer using the switch 14 (Fig. 1) through circuit 41 through node 8 on the output 24 of the address code and using shaper 85 (Fig. 3) through circuit 33 (Fig. 1) and further through node 6 on signal output 23 Address from the subscriber. A single level from the output of the trigger 135 (FIG. 5) along the circuit 158 of the bus 98 enters the node 79 (FIG. 3) where the AND element 173 is connected to work through the OR element 185 (FIG. 6). Next, yaej 79 (Fig. 3) of block 16 (Fig. 1) organizes an ascent to the second computer of the status byte. Element I 173 connected to work (Fig. 6) receives the following levels for the remaining inputs. With no signal 55 Information from the channel from the second computer to the input 19 (Fig. 1), node 2 transmits the zero level via the composite circuit 27 and then in node 78 35 40 23. (Fig. 3) of block 16 (Fig. 1) along the chain 189 (Fig. 6) to the input of the element HE 181 On the basis of this level, the element HE 181 outputs the unit level to the second input of the element AND 173. The third and fifth inputs of this element receive unit levels from zero outputs in the initial (zero) state, respectively, of trigger 162. and 166 o In this state, AND element 173, with the help of the HE element 180, monitors the control signal from the channel, which comes from the second computer via input 19 (FIG. 1) through node 2 via bus 27 and further to node 79 (FIG. 3) of block 16- (FIG. 1) via circuit 157 (FIG. “6) to the input of the element HE 180 After the signal is reset, the control from the channel, the element NOT 180, outputs the unit level to the first input of the imager 168. As a result, at the inputs of the element And 173 there are single levels and it gives out a single level, according to which the shaper 167 forms a single pulse. This pulse sets the trigger 161 to one state. The unit level from the output of the trigger 161 along the bus circuit 105 105 (Fig. 3) enters the switch 14 (Fig. 1) and enables the transfer of the state byte that the 8D driver forms (Fig. 3) . In this case, the imaging unit 84 is connected to the operation of the elements And 237 (Fig. 8). Since the trigger 137 (Fig. 5) is in the initial (zero) state, the zero level from the output of this trigger along the circuit 160pshats 98 and further without conversion at node 79 (Fig. 6) through composite circuit 106 enters shaper 84 (Fig. 3) where it is integrated by the element HE 241 (Fig 8). Unit level from item output NOT 241 enters the second inputs of the elements And 237-240. On the basis of this, the driver 84 along the circuit 242 of the bus 107 generates only the Attention sign, which enters the bus 35 (FIG. 3), the switch 14 (FIG. 1), and the latter passes it through the circuit 41 through the node 8 on the output 25 to the second COMPUTER. Simultaneously, the unit level from the trigger output 161 (Fig. 6) connects the element And 174 and the circuit 105 of the bus 87 enters the driver 85 ten 15 20 2S 0353 i24 (Fig. 3), where, without conversion, bus 33 (Fig. 9), through node 6 (Fig. 1), is output 23 to the second computer as Control signal 5 from the subscriber to accompany the status byte. After that, the node 79 (Fig. 3) of the block 16 (Fig. 1) enters the idle state from the second computer signal Information from the channel. This task in the node 79 (Fig. 6) is performed by the AND 174 element connected to work. The information signal from the channel is fed to the input 19 (Fig. 1) through the node 2 via the bus 27 and then at the node 79 (Fig. 3) of the block 16 (Fig. 1) on the circuit 189 (Fig. 6) at the first input of the element AND 174. Based on this signal, the element AND 174 you, tsit single unit by which the imaging unit 168 forms a single pulse. This pulse resets the trigger 161 and sets the trigger state to 162. After resetting the trigger 161 switch 14 (fig. 1) on circuit 41 through node 8 at output 25 stops the state byte to the second computer, and driver 85 (fig. 3) on circuit 33 through node 6 (fig. 1) on output 23 - control signal from the subscriber. Single level with single trigger trigger 162 (Fig. 6) enters the second inputs of the elements And 175-177. In the described sequence, the triggers 134 and 137 (Fig. 5) of the node 78 do not change their state and remain in the initial (zero) state. The zero level from the output of the trigger 137 along the chain 160 of the composite circuit 98 in the node 79 (Fig. 3) blocks the operation of the AND element 175 (Fig. 6) and, after the element is inverted with the HE 183 unit level, enters the fourth inputs of the AND elements 176 and 177. The zero level from the output of the trigger 134 (FIG. 5), through the circuit 159 of the bus 98 in the node 79 (FIG. 3) blocks the operation of the AND element 176 (FIG. 6) and after inverting the HE element 182 with a unit level enters the third input of the AND element 177. From the above it follows that the AND 177, element remains unblocked. which, with the help of HE. 181, monitors the reset of the Information signal from the channel. After resetting this signal in circuit 189, a zero level is established, and the element thirty 35 40 45 55 25 NOT 181 gives the first input of the element NOT 177 a unit level. As a result, the element NOT 177 will pull out a single level, according to which the driver 171 forms a single pulse. This impulse sets the circuits operating on the second computer to the initial state. At node 79, this impulse confirms the initial state of the flip-flops 163-166 through the element. OR 187 resets the trigger 162, along the circuit 192 of the 10D bus enters node 80 (Fig. 3) and through the OR element 184 in circuit 76 and 103. At node 80 (Fig. 7), this pulse maintains the initial state of the trigger 199-202. Along the circuit 76 (Fig. 6) of the bus 47 (Fig. 3), it enters block 17 (Fig. 1), where it confirms the initial state of the trigger 61 (Fig. 2). Through circuit 103 (FIG. 6), this pulse enters node 77 (FIG. 3), where it confirms the initial state of trigger 114 and 115 (FIG. 4), resets triggers 113 and 117, and enters tires 86 and 95. Via bus 86, this pulse enters shaper 85 (FIG. 3), where flushes trigger 246 (FIG. 9). On bus 95 (Fig. 4), it enters node 78 (Fig. 3), where it confirms the initial state of the trigger 134, 136 and 137 (Fig. 5) and resets the trigger 135. Reset trigger 113 (Fig. 4) means the termination Services to the second computer signal The subscriber works through the SHSh 128 element along the circuit 129 of the bus 86 and then through the driver 85 (Fig. 9) along the composite circuit 33 through the node 6 (Fig. 1) through the OUTPUT 23. The device enters the standby state in the second computer, which, during signal processing, the Subscriber’s request received the Attention sign and the address of the AZ. On the basis of the Attention, the second computer recognizes that it is accessed by one of the active devices, by the higher address resolution (A) the second computer determines that this device is the first computer, and by the lower digit address (3) using its table matching the addresses with the access instructions determines the specific purpose of the first computer and what actions need to be taken. In this case, the first computer requires that the second computer 20353126 issued a command Read with code 3 in the modification bits. Thus, with the transfer of the attribute, Attention is transferred to all that is necessary for the organization of the intermachine information exchange and there is no need to issue the REFINE command byte command. The second computer starts to start the corresponding command 10 accompanied by its address AZ. The sequence of initial sampling signals from the second computer is received and processed by the device in the same way as the initial sample described. 5 sample from the first computer. The AZ code is received by the device at the input 21 (Fig. 1) through the node 4. The higher bits () on the circuit 43 arrive at the node 12, where they are compared with 20 with the device’s own address (A) for the second computer formed by node 10 and transmitted to node 12 via circuit 40. As a result of the comparison, node 12 via circuit 31 generates an address identification signal. Fallen bits (3) of the received code through the circuit 45 are received in block 17 to the information input of the register 54 (Fig. 2). The signal Address from the channel is received by the device at input 19 (Fig. 1) through node 2 and further along bus 27 to block 16. Here the data signal is processed by node 77 (Fig. 3). Signal Address from the channel in node 77 (Fig. 4) 35 through the circuit 131 of the bus 27 enters the second input of the AND 125 element. The first input of this element receives a single level from the output of the HE 126 element, which determines the absence of the Sample signal in the 130 circuit, and the third input of the AND 125 element enters through the 31 address identification signal. As a result, the element And 125 gives a single level, 45 in which the driver 119 forms a single pulse. This pulse sets the trigger 114 and the chain 73 of the bus 47 (Fig. 3) enters blssk 17 (Fig. 1), where 50 enters in register 54 (FIG. 2) the value of the least significant bits of the received address (3). Since by this time the trigger 60 is set to one, the zero level 55 from the zero output of this trigger enters the information input of the trigger 61. On the basis of this, the impulse received through the circuit 73 27 bus 47, does not change the state, trigger 61. This means that all other elements of block 17, except for node 59, remain in the same state. Node 59 compares the contents of registers 54 and 52 and, since each of them stores the code 3f, it outputs a single level over circuit 51 — the signal of the correspondence of addresses received from two computers, A single-level level from the output of the trigger 114 (FIG. 4) connects the AND 124 element, which begins to monitor the appearance of the Sample signal in the busbar circuit 27. With the appearance of this signal, the AND 124 element produces a single level, according to which the .120 driver generates a single pulse. This pulse sets the trigger 115. The unit level from the output of the trigger 115 through the element OR 128 connects the element AND 122 and the circuit 129 of the bus 86 through the driver 85, (Fig. 9), through the bus 33 through the node 6 (Fig. 1) to the output 23 as a signal. Work of the subscriber enters the second computer. Element I 122 connected to operation (Fig. 4) using element I. 127 monitors the signal drop. Address from the channel in circuit 131. After resetting this signal, element AND 127 produces a single level, on the basis of which And element 122 also outputs a single level . At this level, the shaper 121 forms a single pulse that sets the triggers 116 and 117. The unit level from the output of the trigger 116 via the circuit 96 of the bus 35 (Fig. 3) enters the switch 14 (Fig. 1), which sends a code A through it, generated node 10, and code 3, stored in register 52 (Fig. 2). These codes, respectively, along chains 40 and 49 (Fig. 1) and then through switch 14, through circuit 41, through node 8, at output 25, enter the second computer as the AD addressee adapter code. Simultaneously, the unit level from the output of the trigger 116 (FIG. 4) along the circuit 96 of the bus 86 via the driver 85 (FIG. 9) via the bus 33 through the node 6 (FIG. 1) on the output 23 enters the second computer as an Address signal from subscriber. A single level from the output of the trigger 117 (Fig. 4) along the circuit 133 of the bus 95 It enters the input element And 145 20 035,3128 (Fig. 5) at node 78 and connects it to work. Element AND 145 begins to monitor the occurrence of the Control signal from the channel that accompanies the code received from the second computer command. The command code arrives at the input 21 (Fig. 1) through the node 4 through the circuit 29 to the first input of the decoder 81 (Fig. 3) in block 16 (Fig. 1). 0 Signal The control from the channel enters input 19 through node 2 via composite circuit 27 and further in block 16. via circuit 157 (Fig. 5) to the first input of AND element 145 of node 78. As a result of this, this element outputs a single level . Element 147 operates at this level, since its second input receives a single level after the element NO 150 inverts the zero level from the output in the initial (zero) state of trigger 113 (Fig. 4) and the third input from zero level trigger out 25 135 (FIG. 5), which is in the zero state. At a single level from the output of the element 147, the shaper 140 forms a single pulse. This impulse sets the trigger 136 to a single state. A single level from the output of this trigger along circuit 99 goes to the second input of the decoder 81 (FIG. 3), which begins to decrypt the received command. The same impulse from the output 5 shaper 140 (FIG. 5) after. the delays in the element 154 of the delay along the circuit 100 enters the synchronous input of the register 82 (FIG. 3) and records in it the result of the decryption of the command  About the decoder 81. After that, the contents of the register 82 of block 16 through the chain 102 enters the first input of the node 83, the second input of the node 80 and the bus 37 in block 15 (Fig. 1) to the second  input node 83 (Fig. 3). As a result of this, both nodes 83 of blocks 15 and 16 (Fig. 1) compare the decrypted commands received at their inputs for the correspondence between them. Knot 50 83 (Fig. 3) of block 15 (Fig. 1) compares the Write command with the Read command and goes along circuit 112 (Fig. 3) the unit level. Node 83 of block 16 (Fig. 1) compares 55 the command Read with the command Write and also passes along the chain 112 (Fig. 3) the unit level. In block 15 (Fig. 1) the level formed thirty 29 not used in this case. In block 1b, the analogous level arrives at the five input of the AND 143 element (phi1.5) and after the element 155 is inverted by the NOT 152 zero level blocks the operation of the And 142 element. At the first input of the And 143 element enters the unit level via the circuit 72 of the composite circuit 51 trigger output 60 (Fig. 2) of block 17 (Fig. 1). The same level in circuit 72 (Fig. 5), after the element NO 149 is inverted by the zero level, blocks the operation of the AND 144 element. The second input of the AND 143 element receives a single level from the trigger output 136. The third input of the AND element 143 enters via the circuit 70 of the bus 51 unit level from the output of the node 59 (FIG. 2) which determines the correspondence of the addresses received; two computers. At the same time, this level in circuit 70 (after the element 15 is inverted by the element NOT 15, the zero level blocks the operation of the element 148. The fourth input of the element 143 receives a single level from the zero output of the trigger 135, which is in the zero state, on which driver 141 generates a single pulse. This pulse sets the trigger 137, which controls the issuance of a null status byte. The inputs of the And 142 element come in the same levels as on the corresponding inputs of the And 143 element. The And 142 element is blocked only by the fifth input, to which the unit level arrives when there is a mismatch between the two computers, i.e. The node 83 (Fig. 3) in a similar situation determines the discrepancy of the commands received from the two computers and, via the circuit 112, causes the zero level. This level blocks the operation of the AND 143 element (FIG. 5) and, after the inversion of the HE element 152 by the unit level, connects the AND element 142 to the operation. the device in the coordinated system should not occur, and the AND 142 element more controls the degree of coordination of the system of two computers and devices than it participates in a particular job. Device operation after connecting the imager 03531- About 138 is described when considering subsequent modes of operation of the device. When the device is operated in a matched computer system, the AND 142 element is blocked, and the AND 143 element works. As a result of this work, the trigger 137 is set to one state. 0 In addition to the above, a single level from the output of the trigger 136 enters through the element OR 156 to the input of the imager 139, which as a result of this forms a single infrared pulse. This delay, after a delay in the delay element 153, sets the trigger 135 to one state and enters the node 77 via the circuit 97 (Fig. 3) where the 0 116 trigger (Fig. 4) is reset. Resetting this flip-flop means stopping the output of the adapter's address and shaper 85 (FIG. 3) of the signal from the subscriber to the second computer by the switch 14 (Fig. 1). The unit level from the output of the trigger 135 (Fig. 5) along the circuit 158 of the bus 98 enters through the element liJIH 185 (Fig. 6) to the fourth input 0 of the element AND 173. The second input of the element receives the unit level from the output of the element HE 181, which defines {the absence in the chain of 189 sigma Information from the channel, on the third. and the fifth inputs of the AND 173 element come in single levels from the zero outputs in the initial (zero) state, respectively, of the flip-flops 162 and 166. In this state, the AND 173 element uses the NOT 180 element to monitor the signal drop. Control from the channel in circuit 157 After resetting this signal, the element NOT 180 transfers the element to the first input. mA 173 is the unit level, on the basis of which the element I 173 also produces a unit level, and the shaper 167, as a result, forms a single impulse. This pulse sets the trigger 161. The unit level from the output of the trigger 161 along the bus 105 circuit 105 (Fig. 3) enters the switch 14 (Fig. 1), which at this level produces a state of zero from the circuit 35 through the switch prepared by the shaper 84 (Fig. 3) 14 (FIG. 1), through circuit 41 through node 8 to exit 25 0 31 in the second computer. On the other hand, this level from the output of the trigger 161 (FIG. 6) along the circuit 105 of the bus 87 and then through the driver 85 (FIG. 9) via the bus 33 through the node 6 (FIG. 1) on the output 23 enters the second computer signal control from the subscriber. The unit level from the output of the trigger 161 (Fig. 6) connects the ITA element AND, which begins to monitor the arrival of the Information signal from the channel. This signal comes from the second computer via input 19 (Fig. 1) through node 2 via bus 27 to node 79 (Fig. 3) of block 16 (Fig. 1) where through circuit 189 (Fig „6) it goes to the first input of the And element 174. As a result of this, this element produces a single level 5 according to which the driver 168 forms a single pulse. This pulse resets the flip-flop 161 and sets the flip-flop 162 to one state. When the flip-flop trigger 161 clears through the switch 14 (Fig. 1), the output of the state byte to the second computer stops, and the signal from the subscriber stops through the shaper 85 (Fig. 3). - With one setting: the other state of the trigger 162 (Fig. 6) blocks the operation of the element AND 173 AND the element is connected to the operation,. And 175-177. The circuit 160 of the bus 98 from the output of the trigger 137 (FIG. 5) to the third input of the element AND 175 (FIG. 6) receives a unit level, which, after the element NO 183 is inverted by the zero level, blocks the elements AND 76 and 177, t, e, of - Only elements AND 175 continue to work on the enumerated elements. It uses the NOT element 181 to monitor the information signal from the channel. After the signal is reset, the element is NOT 181, and then the element AND 175 also adds unit levels. For a single level from the output of the element And 175 shaper 169 forms a single pulse. This impulse sets the trigger 166 to one state, arrives at the second input of the AND element 178, and through the OR element 187 clears the trigger 162. At the first. the input element And 17B through the circuit 74 of the composite circuit 51 from the single output of the trigger 61 (Fig. 2) enters the zero level and blocks the operation of the element And 178 (Fig. 6). AT 0353132 As a result, a pulse is not supplied to circuit 89. With the installation of the trigger 166 in the unit state-zero level from the zero output given,. the trigger arrives at the fifth input of the AND element 173, Although the trigger 162 is reset at this time, the 5 element AND 173 remains blocked. Unit level with a single 1Q of the trigger trigger 166 of node 79 (FIG. 3) of unit 15 (FIG. 1) through circuit 195 (FIG. 6) of bus 104 enters the first input of the AND 217 element (FIG. 7) of node 80 (FIG. 3) of block 15 ( Fig. 1) and further and via bus 110 (Fig. 6), then via bus 36 (Fig. 3) to block 16 (Fig. 1), where it is located at the second entrance of element And 217 (Fig. 7) of node 80 (Lig. 3). The unit level from unit output2 (-, and the trigger 166 (FIG. 6) of node 79 (FIG. 3) of block 16 (FIG. 1)) goes through circuit 196 (FIG. 6) of bus 104 to the first input of AND 217 (FIG. 7) node 79 (fig. 3) of block 16 (fig. 1) jt, and further along qine 111 (FIG. 6), and then via bus 37 (FIG. 3) to block 15, FIG. 1), where it is received by the second input element AND 217 (FIG. 7) of node 80 (FIG. 3). Both elements and 217 .. (Fig. 7) of the VO nodes (Fig. 3) of blocks 15 and 16 (Fig. 1) receive unit levels at both inputs and, therefore, both elements AND 217 (Fig. 7) give unit levels connecting both nodes 80 (Fig. 3) to work.   In block 15 (FIG. 1), a unit level is received from register 82 (FIG. 3) to node 80 via circuit 226 (FIG. 7) of bus 101 (FIG. 3), which indicates that block 15 (FIG. 1) is received l command Write. This level arrives at the first input of the AND 215 element (Fig. 7). The second input of this element receives a single level from the output of the AND element 217. At the third input of the AND element 215, via bus circuit 229 111, which enters bus 37 (Fig. 3 ), a single level comes from a zero code in the zero (initial) state of the trigger 202 (Fig. 7)  node 80 (Fig. 3) unit 16 (Fig. 1). This level. Indicates that the exchange not yet started On the basis of all the levels described, element I 215 (fig. 7) of node 80 (fig. 3) of block 15 (Fig. 1) gives a single level KOTopbtfi through the element OR 221 (Fig. 7) is fed to the input formiro0 five five 33 sump 208. This shaper generates a single pulse at this level, which sets trigger one 198. The unit level from the trigger output 198 goes to the second inputs of the AND elements 210 and 214 and through the OR element 223 to the circuit 88. Through the circuit 88 (FIG. 3) this level enters through shaper 85 (Fig. 9) through composite circuit 32 through node 5 (Fig. 1) at output 22 to the first computer as a signal. Subscriber information ot This signal for a computer is a request for a data byte. Data byte from the first computer via input 20 through node 3 via circuit 28 through block 15 (Fig. 3) via bus 36 (Fig. 1) through block 16 (Fig. 3) via bus 35 enters switch 14 (Fig. 1) . The accompanying byte of the given information signal from the channel from the first computer enters input 18 through node 1 via bus 26 to node 80 (fig. 3) of block 15 (fig. 1), where it receives via circuit 189 (fig. 7) on the first input element I 210. Since the second input has already received a unit level, then the received signal gives element I 21 a unit level. This level arrives at the second input of the element I 218 and through the chain 232 via the bus 110 entering the bus 36 (Fig. 3) in block 16 (Fig. 1). In the block 16, this level receives on the third input element And 216 (Fig. 7) of node 80 (Fig. 3). The first input element And 216 (Fig. 7) on the circuit 228 of the bus 102 receives a single level from the output of the register 82 (Fig. 3). This level indicates that block 16 (Fig. 1) has received a Read command. The second input element And 216 (Fig. 7) receives a single level from the output of the element And 217. For these levels, the element And 216 gives a single level by which the imaging unit 204 forms a single pulse. This pulse sets trigger 197 to a single state. A single level from the output of trigger 187 connects elements AND 209 and 213 to operation, enters circuit 109 and through element OR 223 into circuit 88. Through circuit 109 of bus 35 (Fig. 3), this level enters the switch 14 (Fig. 1) and allows the transfer 0353134 the data byte received earlier in the circuit 41, after which this data byte through the node 8 at the output .25 enters the second computer, via the circuit 88 (Fig. 3) 5 described level through the driver 85 via the bus 33 (Fig. 9) and further node 6 (fig. 1) on output 23 enters the second computer as a signal Information from the subscriber. For a second computer, this signal is a message about s. passing it a byte of data. The computer receives the data byte and informs the adapter about this by the Information signal from the channel. This signal is sent to the input.  5 19 through node 2 on bus No 27 into block 16. In block 16 it receives on circuit 189 (Fig. 7) an element AND 209 of node 80 (Fig. 3). This item is already connected to work and with the receipt of the specified 20 of the signal produces a single level at which the driver 207 (FIG. 7) generates a single pulse. This pulse sets the triggers 201 and 202 to one state and resets the trigger 197. Resetting the trigger 197 means that zero levels have arrived in circuit 109 and 88, as a result of which switch 14 (Fig. 1) stops transmitting the data byte, and 0, the driver 85 (Fig. 3) and then through the node 6 (Fig. 1), the Information signal from the subscriber is stopped. The zero level from the zero output of the trigger 202 (FIG. 7) to 5, the bus 229 circuit 229 entering the bus 37 (FIG. 3) comes from block 16 (FIG. 1) to block 15 at the third input of the AND unit 215 (FIG. 7) of node 80 (FIG. 3) and blocks operation given 0 item The unit level from the output of the trigger 201 (Fig. 7) of the node 80 (Fig. 3) of the block 16 (Fig. 1) goes to the third input of the AND element 212 (Fig. 7) and along the bus circuit 233 111 entering the bus 5 37 (Fig. 3), in block 15 (Fig. 1) and at the first input element And 218 (Fig. 7) node 80 (Fig. 3). The second input element And 218 (Fig. 7) has already entered a single level from the output of the element And 210. As a result of this, the element And 218 produces a single level at which the imaging unit 205 generates a single pulse. This pulse resets trigger 198 and sets trigger one to 200. With resetting trigger 198, zero levels are set in chains 88 and 232. Chain zero level 88 means. that through the shaper 85 (Fig. 3) on the bus 32 through the node 5 (Fig. 1) on the output 22, the device stops issuing an Information signal from the subscriber to the first computer. The zero level of the circuit 232 (Fig. 7) is supplied to the third input of the element And 216 of the node 80 (Fig. 3) of the block 16 (Fig. 1). After that, both nodes 80 (Fig. 3) of blocks 15 and 16 (Fig. 1) go into the mode of waiting for signals to be dumped. Information from the channel from the corresponding computers. In node 80 (Fig. 3) of block 15 (Fig. 1), the element 211 (Fig. 7) is following the reset of the named signal using the HE element 224. In node 80 (Fig. 3) of block 16 (Fig. 1) resetting the signal Information from the channel in this case is monitored by the element AND 212 (FIG. 7) with the help of the HE element 224. Both nodes 80 (FIG. 3) perform this work independently of one another. After resetting the signal from the channel of the first computer in circuit 189 (Fig. 7) of node 80 (Fig. 3) of block 15 (Fig. 1), the zero level is set, which, after the element 224 is inverted by HE 224 (Fig. 7), is sent to the first input of the AND element 211. The second input of this element receives a unit level after the element NO 225 inverts the zero level of the bus 111 through the circuit 235, which enters the bus 37 (Fig. 3), from the output of the OR element 220 (Fig. 7) of node 80 (FIG. 3) Block 16 (Fig. 1) with Element OR 220 (Fig. 7) gives zero zero, since its inputs receive zero levels from the outputs of the elements And 213 and 214, which are blocked by the zero level from the circuit 157. Through this circuit, the node receives a control signal from the channel, which is absent in a given period of time. At the third input of the element And 211, a single level has already arrived from the output of the trigger 200. On the basis of the listed levels, the element And 211 outputs a single level, which is fed through the element OR 221 to the input of the imaging unit 208. After resetting the signal Information from the channel of the second computer, similarly, in circuit 189 (Fig. 7) of node 80 (Fig. 3), fleas 16 (Fig. 1) establish the zero level S which, after inverting the electric Ment HE 224 (Fig. 7) with a unit level of HE 224 (Fig. 7) with a unit level, enters the nepBbtfi input of the AND element 212. The second input of this element receives a single level after the inverting element of the HE 225 of the zero level received through the bus circuit 236 236 , entering bus 36 (Fig. 3), from the output of the OR element 220 (Fig. 7) of node 80 (Fig. 3) of block 15 (Fig. 1). The OR element 220 (Fig. 7) provides the zero level according to the same conditions as the corresponding element of the block 16 (Fig. 1). The third input of the AND 212 element (FIG. 7) has already received a single level from the output of the trigger 201. Based on these levels, the OR element 212 returns the single level by which shaper 206 generates a single pulse. This pulse resets the trigger 201. With the reset of the trigger 201c its output zero level enters the specified circuit at the first input element And 218 node 80 (Fig. 3) unit 15 (Fig. 1). This completes the cycle of transferring the data byte from the first to the second computer. After this cycle, in node 80 (Fig. 3) of block 15 (Fig. 1) the trigger 200 (Fig. 7) remains in one state, and in node 80 (Fig. 3) of block 16 (Fig. 1) a trigger 202 (FIG. 7), which remains in this state until the end of the exchange, and therefore the AND element 215 of node 80 (FIG. 3) of block 15 (FIG. 1) remains blocked for this period. The next cycle of data byte transfer through the device from the first computer to the second begins immediately with the entry of a unit level to the input of the shaper 208 (Fig. 7). At this level, a dainsh shaper forms a single impulse. Further operation of the nodes 80 (Fig. 3) of the blocks 15 and 16 (Fig. 1) on the exchange of data is carried out in the described sequence. The termination of the exchange is possible on the initiative .toboy from the computer. In response to the signal transmitted by the device, Information from the computer subscriber for this purpose receives the Control signal from the channel. In the described exchange, in block 15 (Fig. 1), the indication of the end of the exchange is monitored by element I 214 (fig. 7) of node 80 (fig. 3), and in block 16 (fig. O, element 213 (fig. 7) node 80 (Fig. 3). These elements 37 connected to this work after installation in one state, respectively, of the trigger 198 (FIG. 7) of the node 80 (FIG. 3) from block 15 (FIG. O and the trigger 197 (FIG. 7) of the node 80 s (FIG. 3) of block 16 (Fig. 1). If, for example, an indication of the termination comes from the first computer, then the control signal from the channel passes through input 18 through node 1 10 via bus-26 to node 80 (Fig. 3) of block 15 (Fig. 1), where it receives 157 (FIG. 7) element AND 214. Thereafter, element AND 214 outputs a single level through element OR 220 5 to circuit 236 to then through element OR 222 to the input of the former 203. Along circuit 236 of bus 110 entering bus 36 (FIG. 3), this level enters unit 80 of block 16 (FIG. 1). Here 20 from also through the element OR 222 (Fig. 7) is fed to the input of the shaper 203. If the indication of the end of the exchange comes from the second computer, the signal 25 Controls from the channel passes through input 19 (FIG. 1) through node 2 via bus 27 to node 80 (FIG. 3); block 16 (Fig. 1), where it is received along circuit 157 (fig. 7) of an AND 213 element. This jo element outputs a unit level similarly through the OR element 220 into the chain 235 and further through the OR element 222 to the input of the forwarder 203. 235 tires 111, entering shisha 37 (FIG. 3), the indicated level enters unit 80 of block 15 (fig. 1). Here he also through the element OR 222 (Fig. 7) is fed to the input of the imaging unit 203. As a result of issuing an instruction on the end of the exchange of any of the computers, unit levels are available at the inputs of both formers 203 of nodes 80 (Fig. 3) of blocks 15 and 16 (Fig. 1). For these 45 levels, these shapers form single pulses, which flip-flops 197 and 198 at their nodes (Fig. 7), set the flip-flops 199 50 to one state, and through the circuit 191 of the bus 108 arrive at the corresponding nodes 79 (Fig. 3) where triggers 164 (Fig. 6) are set in one state and triggers 165 through elements OR 186. 55 The unit level from the output of the trigger 199 (Fig. 7) of the node 80 (Fig. 3) of the block 15 (Fig. 1) along the chain 190 35 40  s 120353138 (FIG. 7) the bus 108 enters through the OR element 185 (FIG. 6) on fours 0 50 5 o 50 five 0 the input of the element And 173. The second input of the element And 173 comes from the output of the element HE 181 unit level, which indicates the absence of a signal at the moment Information from the channel in the circuit 189. The third and five inputs of the element And 173 receive unit levels in zero condition. In this state, the AND element 173, with the help of the NOT element 180, monitors the control signal from the channel. With the reset of this signal in circuit 157, a zero level is established. After it is inverted by the element NOT 180, the unit level arrives at the first input of the element I 173, which as a result of this yields the unit level. At this level, the shaper 167 generates a single pulse, which sets the trigger 161 to a single state. The unit level from the output of this trigger enters the circuit 105 of buses 87 and 34 (Fig. 3). On the bus 34, this layer connects the switch 13 (Fig. 1) to transmit the status byte. The status byte forms the driver 84 based on the single states of the triggers 164 and 165 (Fig. 6) and the zero state of the trigger 137 (Fig. 5). Zero level with trigger output 137 on the circuit. 160 of the bus 98 included in the bus 106 (FIG. 6) enters the shaper 84 (FIG. 3), where, after the element is inverted by the HE 241 (FIG. 8), the unit level goes to the second inputs of the AND 237-240 elements. Unit levels from the outputs of the flip-flops 164 and 165 (Fig. 6), respectively, along chains 193 and 194 of the composite circuit 106 are fed to the first inputs of the And 239 and 2DO elements (Fig. 8). As a result, the unit level from the output of the AND 239 element as a sign. The channel has terminated along the chain 244 and the unit level from the output of the element 240. As a sign, the WU has finished along the chain 245 through the bus 107, which is part of the tire 34 (FIG. 3), switch 13 (FIG. 1), which transmits them in the status byte of circuit 39 through node 7 on output 24 to the first computer, On the bus 87 (FIG. 3), the unit Zfoven from the trigger output 161 39 (FIG. 6) enters through the driver 85 (FIG. 9) via the component circuit 32 via node 5 (FIG. 1) on output 22, also into the first computer, as an accompanying byte of the state Control from the subscriber. Next, the element AND 174 (Fig. 6) to the second input of the cottage enters a single level from the output of the trigger 161, monitors the flow of the Information signal through the circuit 189 from the channel. The adapter receives this signal from the first computer in response to the status byte issued. This signal on the input 18 (Fig. 1) through the node 1 via the bus 26 enters the block 15, where it is received via the chain 189 (Fig. 6) in the node 79 (Fig, 3) And 174 element (Fig. 6) To this signal, AND 174 generates a single level at which shaper 168 generates a single pulse. This pulse resets trigger 161 and sets trigger 162 to one state. When trigger 161 clears, transmission stops through switch 13 (FIG. 1). shaper 85 (Fig. 3) - signal control from the subscriber. The zero level from the zero output of the trigger 162 (Fig. 6) b shows the operation of the element AND 173. The unit level from the single output of the trigger 162 goes to the second inputs of the elements AND 175-177. The element 175 is blocked by the zero level coming through the circuit 160 of the composite circuit 98 from the output of the trigger 137 (Fig. 5) located in Element AND element 176 (Fig. 6) is blocked by a zero level, coming through circuit 159 of composite circuit 98 from the output of trigger 134 (Fig, 5), which is also in the zero state. These same levels from the outputs of trigger 134 and 137 by the described chains after inverting, respectively, the elements HE 182 and 183 (FIG. 6 ) the third and fourth inputs of the AND element 177 arrive in single levels. In this state, this element with the help of the HE element 181 monitors the reset of the Information signal from the channel. After resetting the first computer of a given signal, the zero level is set in the 1 89 ° circuit and the HE element 181 outputs a single level to the first input of the AND element 177. In the result of this, this dantile element also produces a single level, according to which 20353140 shaper 17.1 generates a single pulse. This impulse is the impulse of installation of the block, 15 (FIG. 1) to the initial state. In the node 79 g (Fig. 6) it goes to the zero inputs of the flip-flops 163-166 and through the OR element 187 to the zero input of the flip-flop 162, as well as to the circuit 192 of the tina 104 and through the element OR 184 in 10 circuits 75 and 103. In the unit state there are triggers 162, 164 and 165. They assume the zero state. On the bus 104 pulse arrives at the zero inputs of the trigger 199-202 (5 (Fig. 7) of node 80 (Fig. 3) and resets them to the (initial) state. Through the circuit: 75 bus 46 a pulse arrives at the zero input of the trigger 60 (Fig. 2) of block 17 (Fig. 1) and ; iQ resets it to the zero state. The chain 103 (Fig. 3) this pulse is fed to the zero input of the flip-flops 113-117 (Fig, 4) of the node 77 (Fig. 3), as well as into the tires 86 and 95 (Fig. 4). 25 This pulse sets the zero (initial) state of the trigger 114-117. The bus 86 pushes the pulse to the zero input of the trigger 246 (FIG. 9) of the driver 85. Through the bus 95 (FIG. 3) it goes to the zero inputs of the trigger 134-137 (FIG. 5) of the node 78 (FIG. 3), liMnynbc resets the triggers 135 and 136 (Fig. 5) are in the zero (initial) state. After this, unit 15 (FIG. 1) returns to the initial state. Similarly, the node 79 (Fig. 3) of the block 16 (Fig. 1) works, which also organizes the issue of the state byte to the second computer with the signs  The channel has terminated and the VU has terminated and, after issuing them, ensures the installation of the units of the block 16 to the initial state. This completes the execution of the Write command received from the first computer and the Read command received from the second computer. At the same time, the execution of these commands does not require issuing an additional command to specify the command byte, since  About all the necessary information the second computer receives in the address code upon receipt of the attribute Warning. The device works in the same way, if it receives a command from the first computer to read when accompanied, for example, addresses. In this case, the device sends the Attention sign with the address to the second computer. thirty  15 41 A5 sixteen in response to which receives command Write with the accompanying address A5. This easily determines the replay of a computer by the correspondence table. The difference in the operation of the device in this case is in the direction of exchange and its provision. The work performed by node 80 (Fig. 3) of block 15 (Fig. 1) is performed by node 80 (Fig. 3). unit 16 (Fig. 1) and vice versa, the work that was performed by the VO node (Fig. 3) of block 16 (Fig. 1) is performed by node 80 (Fig. 3) of block 15 (Fig. 1). The device works in a similar way when receiving a command from the second computer at the beginning. In this case, the Attention sign with the corresponding address is transmitted by the device to the first computer. When, for example, a control is received from the first computer when it is controlled, for example, address 9B It, the device in the described sequence receives it and sends it to the second computer, an Attention sign that is followed by the address. Block 15, after receiving the command, enters the state of waiting for the transfer of the attribute Attention to the second computer. This operation in block 15 is performed by node 80 (FIG. 3), in which a unit level from register 82 (FIG. 3) enters the circuit 227 (FIG. 7) of bus 101. This level indicates that block 15 (Fig. 1) has received a control command. He arrives at the first input element And 219 (Fig. 7). After issuing the attribute, the Attention to the second computer unit 16 (Fig. 1) in the specified sequence comes to its initial state, including the trigger 246 (Fig. 9) of the former 85 (Fig. 3). The unit level from the zero output of the trigger 246 (FIG. 9) along the circuit 94 of the bus 37 arrives at the second input of the AND element 219 (FIG. 7) of the node 80 (FIG. 3) of the block 15 (FIG. 1). As a result, the unit level from the output of the AND 219 element (FIG. 7) through the OR element 222 enters the input of the imaging unit 203. The latter generates a single pulse that sets the trigger 199 to one and enters along the circuit 191 of the bus 108 and node 79 (FIG. 3). Here he sets in the described sequence the triggers 164 and 165 (Fig. 6), the Uniform level from the output of the trigger 199 (Fig. 7) along the bus circuit 190 03531 2 108 also enters node 79. (Fig. 3) and connects it to the work of issuing state bah. In the sequence described, node 79 5 provides a status byte to the first computer with the sign Finished and WU finished, and then setting the block 15 (Fig. 1) to the initial state. 10 With the Attention sign in the address code AB (the device provides for transmission to the second computer of all control information that the second computer can easily decode using the table corresponding to J5. The need to issue the Refine command byte command and in this case disappears. To transfer the control information from the second computer in the first taps addresses, 20 different from the addresses intended for control information from the first to the second computer. TaKiix commands are transmitted in the same way. With the frequent exchange of information through the device, there is a probability of simultaneously issuing commands to two computers. So, Hanpsn-iep, in the period of reception by the device from the first computer of the Write command, accompanied by its address 93, the Management command comes from the second computer, accompanied by its address AC ,. Receiving team Write from first 35 the computer is carried out in the described sequence. At the same time at this time, the device receives from the second computer address. Older bits of the addresses come from node 12. As a result of comparing them with the code generated by node 10, node 12 generates an address recognition signal. This signal on the circuit 31 enters the node 77 (Fig. 3) unit 16 (Fig. 1) 5 to the third input element 125 (Fig. 4). The address accompanying signal The address from the channel along the circuit 131 also enters node 77 (FIG. 3) of block 16) to the second input of element 125 50 (Fig. 4). At the first entry of this element enters a single level from the output of the element HE 126, which determines the absence in the circuit 130 of the signal from the channel. On 5, based on the levels described, the And 125 element provides a single level, according to which the driver 119 forms a single pulse. This impulse is set43 pours the trigger 114 and enters the circuit 73 of the composite circuit 47 (FIG. 3) at the synchronous inputs of the trigger 61 (FIG. 2) and the register 54. In this case, two cases are possible. By the time the pulse arrives in circuit 73, the trigger 60 is set to one. In this case, the information input of the trigger 61 enters the zero level from the zero output of the trigger 60. According to the received pulse in the described sequence, the lower order bits of the address C are written to the register 54, and the trigger 61 retains its zero state. A possible situation is when the arrival of a pulse along circuit 73 coincides completely with the arrival of a similar pulse along circuit 71 from block 15 (Fig. 1). In this case, the information inputs of the flip-flops 60 and 61 (Fig. 2) receive unit levels from the zero outputs -respectively, flip-flops 61 and 60. Using these pulses, the code 53 is written to the register 53; (, the register 54 is the code and both triggers are set. 60 and 61. This is not a working situation for this node. To eliminate it, in block 17, there are elements 62 and 64, a delay element 55, and a driver 66 that provide priority to the commands of the first computer. After installation in one state triggers 60 and 61c their single outputs to the inputs of the element And 62 receive unit levels, on the basis of which this element produces a single level. After some delay in the delay element 55, this level enters the input of shaper 66. At this level, shaper 66 forms a single pulse 5 which resets trigger 61. For a time until trigger 61 is reset, the unit level from output of element 62 after inverting by element 64 is zero level enters the first input element And 63 and blocks its work. After resetting the flip-flop 61 at the output of the And 62 element, the zero level is set, which means that a single level comes from the output of the NOT 6D element, which connects the And 63 element to the operation. Further operation of block 17 is carried out in the described sequence. A single level with a single trigger output of 60 allows 20 25 5 d jj 35 40 45 50 55 thirty 53 (44 the passage through the switch 68 of the contents of register 53, and the zero level from the single output of the flip-flop 61 blocks the passage through the switch 68 of the contents of the register 54. The impulse formed by the AND 63 element enters the code received from the output of the switch 68 into the register 52. The above description shows that, regardless of the time the command arrived from the second computer, the final state of the block 17 is the same. The case when the signal in circuit 73 comes before the signal in circuit 71,  similar to the first case described. If the computer is swapped. In the final result, registers 52 and 53 remember the code Zze, and register 54 - the code. Node 58 provides a single level, which indicates that the same code is stored in registers 52 and 53, and node 59 outputs a zero level, which indicates that different codes are stored in modes 52 and 54. Next, in block 16 (Fig. 1), the AND element 124 (Fig. 4) of the node .77 (Fig. 3) monitors the appearance of the signal in circuit 130 (Fig. 4). The sampling from the channel and with its arrival produces a unit level, which driver 120 generates a single pulse. This pulse sets the trigger 115. With the installation of this trigger, the block 16 (Fig. 1) outputs to the second computer a signal to the Subscriber. After that, the element AND 122 (FIG. 4) with the help of the element NOT 127 monitors the signal reset. The address is from the channel in the circuit 131. With the reset of the named signal, the element And 122 produces a single level by which the driver 121 forms a single pulse. This pulse sets the triggers 116 and 117 to a single state. The unit level from the output of the trigger 116 provides to the second computer through the switch 14 (Fig. 1) a code and through the driver 85 (Fig. 3) to the Address signal from the subscriber. The unit level from the output of the trigger 117 (Fig. 4) connects the operation of the node 78 (. 3). At node 78, the element begins AND 145 (Fig. 5), which monitors the flow through the circuit 157 of the control signal from the channel from the second computer. This signal accompanies the 45 mandu, which is fed to the input of the decoder 81 (Fig. 3). With the arrival of the signal, the control from the channel element AND 145 (Fig. 5) provides the first input of the element AND 147 with a unit level. The second input of this element receives a single level from the output of the NOT 150 element, which in circuit 132 determines the zero level from the output of trigger 113 (Fig. 4). At the third input of the element 147 (Fig. 5), a single level arrives from the zero output of the trigger 135. As a result, the element 147 introduces a single level at which the driver 140 outputs a single pulse. This pulse sets the trigger 136 to one. A single level from the output of the trigger 136 on the circuit 99 connects the decoder 81 to work (Fig. 3). At the same time, this level connects elements AND 142, 143 and 148 to operation (Fig. 5) and a driver 139 through the element OR 156. In addition, the pulse from the output of the driver 140 enters the second input of the element 144. And elements 142 and 143 are blocked the zero level coming through the circuit 70 from the output of the node 59 (Fig. 2). Element AND 144 (FIG. 5) is blocked by the zero level from the output of the HE element 149, which defines in the circuit 72 a single level coming from the single output of the trigger 60 (FIG. 2). Element I 148 remains unblocked (Fig. 5). The second input of this element receives a single level after inverting the zero level in circuit 70 with an element NOT 151. The third input receives a single level from a zero output of the trigger 135. Based on these levels, AND 148 enters a single level, which through the element OR 155 enters a shaper 138. The operation of block 16 (Fig. 1) described before the shaper 138 (Fig. 5) is connected to the operation is carried out in the same way as in this case. The impulse from the output of the imaging unit 140 after some delay in the element 154 of the delay along the circuit 100 arrives at the synchronous input of the register 82 (FIG. 3) and organizes the recording of the result of the decoding of the received command in the register. Formed 20353146 shaper 138 (Fig. 5) sets the pulse 134 in one state, and the pulse formed by shaper 139, after some delay in the delay element 153, sets the trigger 135 in single state and enters circuit 97. On circuit 97, this pulse arrives node 77 (FIG. 3) and 10 trigger 116 (FIG. 4) are reset. With reset of the trigger 116 in the described sequence, the output to the second computer of the address and the signal Address from the subscriber is stopped. 15 With the installation of the trigger 135 (FIG. 5), the node 79 is connected to operation (FIG. 3). The unit level from the single output of the trigger 135 (FIG. 5) along the circuit 158 through the element OR 185 20 (FIG. 6) goes to the fourth input element AND 173, which, with the arrival of this level, begins to monitor with the help of the element NOT 180 a reset in the circuit 157 of the Control signal from channel 25. With the reset of this signal, the element And 173 produces a single level. At this level, the shaper 167 generates a single pulse, which sets trigger one 161 into a single 2Q unit. The unit level from the output of this trigger along circuit 105 enters the tires 87 and 35 (Fig. 3). On bus 35, he connects the switch 14 (Fig. 1) to issue to the second computer a status byte formed by the forwarder 84 (Fig. 3). Shaper 84 (FIG. 8) in this case, a single level arrives at the second inputs of the AND 237-240 elements, which causes the HE 241 element based on the inversion of the zero level in circuit 160 from the output of trigger 137 (FIG. 5). At the first input element And 237 (Fig. 8) enters the circuit 92 unit level from the output of the trigger 5 246 (Fig. 9). At the first input element And 238 (Fig. 8) enters the circuit 159 unit level from the output of the trigger 134 (Fig. 5). The first inputs of the elements And 239 and 240 (Fig. 8) are received, respectively, through the chains 193 and 194 Zero levels from the outputs of the flip-flops 164 and 165 (Fig. 6). As a result, the shaper 84 (Fig. 3) spits the 55 byte of the circuit 242 (Fig. 8) into the byte using the AND element 237 Attention sign and through the 243 circuit using the AND 238 element sign of Zant. 47 The bus 87 (Fig. 3) unit level from the output of the trigger 161 (Fig. 6) comes through the shaper 85 (Fig. 9) as a signal Control from the subscriber. Next, from the second computer, node 79 (Fig. 3) receives the Information signal from channel 5 through circuit 189 (FIG. 6), on the basis of which And 174 element represents a unit level. At this level, the shaper 168 generates a single pulse. This pulse resets the trigger 161 and sets the trigger 161 to one state. With the trigger 161 reset, the device stops waking up the second byte computer and the subscriber control signal. A single level with a single output trigger 162 connects the elements And 175-177. However, in this case, the element And 175 is blocked by the zero level in the circuit 160 from the output of the trigger 137 (Fig. 5), and the element And 177 (Fig. 6) is the zero level from the output of the HE element 182, which inverts the unit level in the circuit 159 from the output trigger 134 (FIG. 5). The same level goes to the third input of element AND 176 (Fig. 6) .. The fourth input of this element receives a single level from the output of the element HE 183, which inverts the zero level of the circuit 160. The element AND 176 remains unbroken. It is NOT using the element 181 monitors the reset of the Information signal from the channel in circuit 189. After resetting this signal, the AND element 176 triggers a single level, by which the driver 170 carries out a single, - pulse. This pulse sets the trigger 163 to one state, flushes trigger 162 through the OR element 187 through the element. OR 186 installs a trigger 165 into one state and through the element OR 184 enters the chains 103 and 76. Through the chain 103 it enters the node 77 (Fig. 4), then the node 78 (Fig. 5) and the driver 85 ( Fig. 9) In these nodes, this pulse resets triggers 114, 115, 117 (Fig. 4) 134, 135, 136 (Fig. 5) and 246 (Fig. 9). On circuit 76, it enters block 17 (FIG. 2), where it confirms the zero state of trigger 61. With reset of trigger 115, the device stops issuing a subscriber signal to the second computer. On this pic O 5 0 5 about 0 5 five 0 five P. 48 The sequence of signals from the initial sample given by the second computer ends. The second computer informs the device in the status byte that it is used to process the control command and indicates with a sign that it is necessary to take action to process the command received from the first computer. The type of this command is determined by the second computer by the address AZ transferred to it in the described sequence of signals and stored in the computer in the table corresponding to the addresses of the commands. In this case, after removing the occupancy of the second computer, it is also not necessary to issue the command Refine command byte. The indicated task of the node 79 (Fig. 3) of the block 16 (Fig. 1) accomplishes with the help of the flip-flops 163 and 165 (Fig. 6) set to one state during the processing of a sequence of signals The unit level from the output of the trigger 163 arrives at the second input of the element AND 172. The first input of this element receives a unit level during the period when the element NOT 179 determines that there is no signal from the channel in the bus 130 circuit 130. During this period, the element And 172 eliminates a single level, 1 which is connected along the chain 188 of strip 87 to the former 85 (FIG. 3). Here, it goes through the element OR 248 (Fig. 9) to the second input of the element AND 247. Its first input is a unit level from the output of the element NOT 249, which determines the zero level that enters the circuit 129 of bus 86 through the element OR 128 (FIG. 4) from the outputs of the flip-flops 113 and 115. As a result, the AND 247 element (Fig. 9) produces a single level. This level of the circuit 91 bus 33 (Fig. 1) through the node 6 on the output 27 enters the second computer as a signal from the subscriber. At the same time, the unit level from the output of the AND 247 element (Fig. 9) goes through the circuit 91 to the first input of the AND 123 element (Fig. 4) of the node 77 (Fig. 3). The third input of the And 123 element (Fig. 4) goes to the unit level from the code of the element NOT 127, which determines the absence of 131 signals in the circuit. Address from the channel. In this state, the element And 123 monitors the appearance of the signal sample from the channel. Further, the operation of block 16 (FIG. 1) 49 is carried out in the same way as when connecting the device to a second computer on his initiative for an attention sign, the difference lies in the content of the status byte issued. If in the first case, a status byte is issued with the Attention sign, which forms AND 237 (Fig. 8) based on a single level coming through circuit 92 from a single output of a trigger 246 (Fig. 9), then in this situation, the driver 84 (Fig 3) using the element AND 240 (Fig. 8) gives a sign of the TA that ended on the basis of a single level coming along the circuit 194 from the output of the trigger 165 (Fig. 6). Upon completion of this sequence of signals, block 16 (Fig. 1) comes back to its original state and is ready to receive the Read command, while maintaining the address AZ from the second computer. With a very frequent exchange through a device, situations are possible when, when two computers simultaneously access the device, the latter determines when receiving commands the correspondence of addresses and commands. For example, when receiving the command Write from the first computer when the address 93 is followed from the second computer, the device receives the Read command when the address of the AZ is followed. In this case, block 15 (Fig. 1) works as indicated. The block 16 works similarly. Their work differs only in that in node 78 (Fig. 3) of block 15 (Fig. 1) trigger 137 (Fig. 5) sets the signal from the output of the And 144 element, and in a similar node of block 16 (Fig 1) trigger 137 (Fig. 5) is set using element And 143 and shaper 141. At the first input of element And 143, a single level is fed through circuit 72 from a single output of trigger 60 (Fig. 2), to the second input from a trigger output 136 (Fig. 5), to the third input - via the circuit 70 from the output of the node 59 (Fig. 2), which determines the correspondence of addresses in the registers 52 and 54, to the fourth input - from zero The main output of the trigger 135 (Fig. 5), to the fifth input is via the circuit 112c of the input of the node 83 (Fig. 3), which determines the correspondence of the commands received from the two computers. As a result, the element And 143 (Fig. 5) gives a single level, according to which the driver 20353150 141 forms a single impulse. This pulse sets trigger state 137 to one. In addition, in the node 79- (Fig. 3) 5 of the block 15 (Fig. 1) the element And 178 (Fig. 6) is connected to the work by a single level, coming along the circuit 72 from a single output of the trigger 60 (Fig. 2). Based on this element  About And 178 (Fig. 6) passes a pulse from the output of the driver 169 in the circuit 9Q. This pulse enters the shaper 85 (Fig. 3) of the block 16 (Fig. 1) and sets in one state 15 trigger 246. In the node 79 (Fig. 3) of the block 16 (Fig. 1) element And 178 (Fig. 6 ) in this case it is blocked by the zero level, coming through the circuit 74 from the single output of the trigger 20 61 (FIG. 2). As a result of this. A logical pulse from the output of the imaging device 169 (FIG. 6) of the indicated actions does not implement. f 25 When issuing state bytes in a computer, blocks 15 and 16 (Fig. 1), due to single states of the trigger 137 (Fig. 5), form zero state bytes. The unit level from the output of the trigger 137 along the circuit 160 enters the shaper 84 (FIG. 3) and, after the element is inverted by the HE 241 (FIG. 2), the zero level blocks the operation of the AND 237-240 elements, Regardless of what is in the block  16 (Fig. 1) to the input element And 237 (Fig. 8) through the circuit 92 receives a single level from the output of the trigger 246 (Fig. 9), the blocked elements in both blocks in the chain 242-245 issue  zero levels that points to lack of all signs. Otherwise, the initial samples, data exchange, termination of the exchange is carried out in the described sequence.  Thus, for the proposed device, three basic commands are enough: Write, Count, Control. Team Requirement Refine Team Bytes Completely 50 disappears. For a computer, when working with the proposed device, to exclude the use of the Refine command byte command, there is no need for time coordination of the exchange through the device. 55 Information about the type of command and its modification is transmitted in the address code. This is ensured by the ability of the device to respond to a group of users. 511 PU addresses and determine the correspondence of addresses received from two computers. The proposed device responds to a group of 16 addresses. If it is not enough to compile a table of correspondences of addresses to commands, then it is easy to expand them, reducing the size of the nodes (Fig. 1) and increasing simultaneously the size of the registers 52-54, nodes 58 and 59 and and 1 0353152 switch 68 (Fig. 2). If we take into account that the command codes Write - MMMMMM 01, Count - MMMMMM 10, Control - MMMMMM 11, where M is 5 modification bits, then the width of nodes 9-12 (Fig. 1) can be set to two, and the register size 52 -54 (FIG. 2), nodes 58 and 59, and switch 68 are equal to six. In this case, the correspondence tables contain the maximum number of commands. ten 23 Sf 7 / tf ) 97 Fig4 fO (3il 26 (27) Faye. t itH) 159 t FIG. eight Editor O. Yurkovetska Compiled by S. Pestmal Tehred A. Boyko Proofreader A. Obruchar Order 8418/52 Circulation 709 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, st. Project, 4 Fig. / O Subscription