GB1483903A - Data processing systems - Google Patents

Abstract

1483903 Telegraphy SIEMENS AG 16 Sept 1974 [24 Sept 1973] 40207/74 Heading H4P [Also in Division G4] A data processing system includes a central unit comprising a central processor ZP, a store ASP, and an input output unit EAP, the last controlling data transfer between a number of peripherals PGE connected thereto and the central unit and comprising a control unit CCU connected to a chain of processors BL-MUX each of which includes a switching circuit and each of which is adapted, in response to control signals produced by the processor and by the control unit to connect the processor to data channels passing along the chain to the central unit and to prevent any processor further down the chain from responding to the control signals for so long as data exchange over the connected data channels continues. The I/O unit includes a chain of processors each of which may be a block multiplexer BL-MUX connected to associated peripherals via a control unit PST. The connections through the chain include input (relative to the central unit) channels ED, output channels AD, and a number of control lines. As shown in Fig. 3, the output channels AD may be connected via a switching gate S1 to data registers or buffers a. A switch S2 selectively connects either a source in the processor b or the channels ED from processors further along the chain to the channel ED to the central unit. The switches S1, S2 are controlled by unit VE in response to control signals and a comparison of coded signals from the central unit over lines AW1 and a coded signal derived by decoding COD a signal prewired into the processor by virtue of its position in the chain. The first processor in the chain receives a set of binary 1's over lines PNR, the lines passing to the next processor skewed by one bit with the unconnected line receiving binary 0. Thus each processor receives a code indicative of its position in the chain in such a way that processors may be added, up to a maximum number, or removed without requiring any change in their internal structure. The processor itself may select an operation by energizing via gate IG switch S2 and simultaneously energizing request control line ETA. Acknowledgement signals from the central unit are fed to the processors via line SPR and each processor, by gate 064 may block the line to further processors along the chain. It is stated that processors may be selected by lines AW2, one for each processor. Line ETA may also be used to request diagnostic &c. procedures in the central unit WF.