GB1484472A - Arrangements for securing data transfers in a communication system - Google Patents

Abstract

1484472 Data processing systems PLESSEY CO Ltd 16 July 1975 [26 July 1974] 33051/74 Heading G4A Each message supplied by a data processing complex DPE, Fig. 1, includes an address used for routing the rest of the message through a switching network ICM to a particular one of a number of peripheral equipments PE each of which includes two control units PCA, PCB connected to different ports of the switching network so as to be conditioned by a received message to select one of a number of devices P0-P31 served by that PE via interface units PI0-PI31. Gating circuits in the interface units PI are responsive to signals, generated by the control units PCA, PCB from a control bit in a received message, to condition the interface units to receive messages from one or other of the control units PCA, PCB. By software control of the control bit, messages may be sent alternately via PCA and PCB of the addressed PE, or, if either control unit or its associated data path is faulty, via the alternative control unit and data path. The embodiment described uses the 3-line (activity, timing and data) bus and switching network ICM disclosed in Specifications 1,428,407 and 1,394,432. Peripheral control units PCA, PCB, Fig. 3.- When the activity wire AX is raised, timing pulses on TX clock message pulses on DX into a shift register SR until all the message address information has been registered. A check code SMCC is compared at COM1 with a wiredin check code CC to check that the correct route has been taken through the switching network ICM. A register address RA is decoded DC to provide a device select signal A0-A31 and is re-encoded CR for comparison at COM2 with a check code RCC to verify that the correct device selection has been set up. If both code check comparisons are successful, gate G3 is fully enabled to pass on timing signals TX to clock message data pulses on DX into the interface unit PI0-PI31 selected by address wires A0-A31. The control bits C passed on to each interface unit PI0-PI31 from PCA and PCB are compared in the interface unit, Fig. 4 (not shown), which is thereby conditioned to receive message data from PCA, PCB as follows: 00=idle state; 10=No fault, receive from PCA; 01= PCB faulty, receive from PCA; 11 = PCA faulty, receive from PCB.