GB2186103A - A fault finding aid for a computer system - Google Patents

Abstract

An aid for diagnosing addressing errors in computer systems caused by a faulty peripheral interface failing to respond to a centrally generated handshake signal, comprises a selector 300, a signal generator 400 and a presentable store 200 on which a peripheral address may be set, a handshake signal being returned when that peripheral is addressed. The store stores one or more preset test bits forming at least part of a test address and provides at each store output a signal representing binary value of corresponding preset test bit. The selector is connected to the address bus to select one or more address bits from it and to signal the binary value of each selected bit of the corresponding selector output. The generator responds to receipt of a first control signal to provide a second control signal if, and only if, the binary value of each selected bit matches the binary value of a corresponding bit of the test address. <IMAGE>

Description

SPECIFICATION A fault finding aid for a computer system This invention relates to fault finding aids for computer systems and in particular to an aid for tracing addressing errors in computer systems having several peripherals coupled to a common address bus.

It is well known to link several peripherals to the central processor of a computer system by means of shared computer buses. Data is transferred between the processor and the peripherals on a data bus, the interchange being regulated by various control signals transmitted to and from the processor on a control bus. An individual peripheral of the several that share the data bus is selected for data communication with the processor by means of an addressing system.

Each peripheral is assigned an address and linked to the processor by a shared address bus, the processor transmitting the address of the peripheral with which the information is to be exchanged on the address bus. The peripherals are arranged so that only the one with that address will be enabled to communicate on the data bus.

Before communications are started with a peripheral the system program generally performs a check to ensure that the required peripheral is connected to the computer system. A known method of performing this check is to transmit the address of the peripheral on the address bus together with an outgoing handshake signal on a first control line. The peripheral, if it is the one addressed by the processor, responds to the receipt of the outgoing handshake signal by transmitting an ingoing handshake signal to the processor on a second control line. If the ingoing handshake signal is received by the processor within a fixed time from the transmission of the outgoing handshake signal the processing will continue; if not an addressing error will be registered and the processing will stop.

A peripheral may have a fault which causes it to fail to respond to the handshake signal intermittently. This makes tracing of the addressing fault difficult as diagnostic programs are usually unable to determine which peripheral is faulty. The addressing fault may be absent when a peripheral is tested only for the fault to reappear at a later time. One method of tracing the fault is to substitute the interface of each peripheral (which regulates the communications of a peripheral with the buses) in turn with one that is known to be working until the system program runs for some time without the fault occurring. The disadvantage of this method is that a complete set of working interface boards is needed at a computer site to carry out the test.It is an object of the present invention to provide a fault finding aid for tracing intermittent addressing faults more conveniently than the substitution method just described.

According to the present invention there is provided a fault finding aid for a computer system having an address bus, a first and a second control line and a processor in which the processor is arranged to transmit a plurality of bus address bits on the address bus and to transmit and receive a first and second control signal on the first and second control line respectively, the aid comprising:: a pre-settable store arranged to store one or more pre-set test bits forming at least part of a test address and having one or more store outputs, the store being arranged to provide at each store output an electrical signal representative of the binary value of the corresponding pre-set test bit; a selector connectable to the address bus and having one or more selector outputs, the selector being arranged to select one or more selected bits from the bus address bits and provide an electrical signal representative of the binary value of each selected bit at the corresponding selector output; and a signal generator coupled to the store and selector outputs and having a control signal input connectable to the first control line and a control signal output connectable to the second control line, the signal generator being responsive to the receipt of a first control signal to provide a second control signal at the control signal output if and only if the binary value of each of the selected bits matches the binary value of the corresponding bit of the test address.

A particular embodiment of the invention will now be described by way of example only with reference to the accompaying drawings in which: Figure 1 is a schematic block diagram of a computer system; and Figure 2 is a circuit diagram of an embodiment of the invention for use with the computer system of Fig. 1.

Referring to Fig. 1, a computer system 100 configured as a flight simulator has a processor 102 coupled to an address bus 104 having address lines A0-A17, a data bus 106, a first control line 108 denoted MSYN and a second control line 110 denoted SSYN. The buses 104, 106 and the control lines 108 and 110 are also coupled to interfaces 11, 12, 13, and 14 which mediate the transfer of information between the processor 102 and a keyboard 122, a printer 124, a video display unit (VDU) 126, a disc 128 and a radar simulator 130. The keyboard 122 and the printer 124 share the interface 11 whereas the peripherals 126 to 130 have separate interfaces 12 to 14 respectively. The processor 102 is also linked to a memory store 132.Each interface 11-14 has two, two-byte (word) memories associated with each peripheral to which it is linked that is each peripheral 122-130 has associated with it two word memories individually addressable by the processor 102. One of the word memories contains two bytes of status information, the other two bytes of data memory. In this embodiment the word memories have pre-determined 18-bit addresses as shown in Table 1, the peripheral address bits being denoted PO-P17.

Table 1 I Peripheral | word address (hexadecimal) Keyboard 777560 777562 Printer 777564 777566 VDU 777570 777572 Disc 777574 777576 777600 I Radar Simulator 1 777602 In the computer system of Fig. 1 each peripheral memory has its five most significant bits of the 18-bit address as binary 1s. The least significant bit P0 is ignored by each interface since the processor only accesses memory at two-byle intervals and bit P1 distinguishes between the status and data buffers or a given peripheral, thus each peripheral is distinguishable from another soley by the values of bits P2-P12 of their addresses.

Each interface 11-14 is arranged so that it will return an SSYN (ingoing handshake signal) control signal on the SSYN control line 110 when it receives a MYSN (outgoing handshake signal) signal on the MSYN control line 108 if any one of the addresses associated with the peripherals to which it is linked is transmitted at the same time on the address bus 104 by the processor 102. A failure of one of the interfaces 11 to 14 to respond correctly to an MSYN signal addressed to one of the peripherals to which it is linked will cause an addressing error.

In the computer system shown in Fig. 1, a binary value of 1 on one of the address bus lines AO-A17 and the presence of an MSYN or SSYN signal is represented by grounding the appropriate address line AO-A17 of the address bus 104, control line 108 or control line 110, respectively. An address bit of binary value 0 and the absence of an MSYN and SSYN signal is represented by a +5 volt signal on the appropriate address bus line AO-A17 or control line 108, 110 respectively.

Referring now to Fig. 2 a fault finding aid 150 comprises a store 200, a selector 300 and a signal generator 400.

The store 200 comprises eleven switches S2, S3 to S12 each connected between a respective store output 202, 203-212 and a +5 volt rail 220. Each of the store outputs 202, 203-212 is also connected to a ground rail 230 by a respective one of the twelve 1k ohm resistors 232. If any one of switches S2-S12 is open the corresponding store output 202-212 will be grounded (representing a stored binary 0 binary value of in contradistinction to the convention on the computer address line) and if closed will be at +5 volts (representing a stored binary value of 1). Because the peripherals of the computer system 100 of Fig. 1 with which the aid illustrated in Fig. 1 is to be used are each associated with two consecutive word addresses starting at an even boundary and the peripheral address bits P13-P17 are always binary 1 it is only necessary in this instance to provide the aid 150 with means for pre-setting bits P2 to P12 of the peripheral address to be tested which are set by the switches S2-S12 of the store 200, respectively. However it is to be understood that the entire peripheral address including bits P13 to P17 constitutes the test address. Other aids embodying the invention for use with other computer systems may have stores in which different test address bits are presettable.

The selector 300 selects various address bits from the address bus 102. It has sixteen terminals T2, T3-T17 connectable to the address lines A2-A17 of the address bus 104 on which the processor 102 transmits bits 2 to 17 of a peripheral address. The terminals T3-T17 are each connected directly to the input of a respective one of inverters 13, 14-117, the terminal T2 being connected to the input of inverter 2 via a switch S13. Outputs 302, 303-370 of the inverters 12 to 117 constitute the selector outputs. The inverters are implemented on SN74LS240 integrated circuits.

The selector 300 is pre-settable by means of the switch S13 to selects bits 2-17 or bits 3-17 of the address bits on the address bus (for switch S13 closed and opened respectively), the inverters 12 to 117 providing at their respective outputs 302-317 a +5 volt signal representative of a binary value 1 if the corresponding address line is at ground, or is at ground representative of a binary value 0 if the corresponding address line is at +5 volts. If switch S13 is open the selector output 302 will float.

The signal generator 400 has a terminal T19, constituting the control signal output, connectable to the SSYN control line 110 of the computer system 100. The terminal T19 is connected to a +5 volt rail 402 via inverters 119, 120 and 1k ohm resistor 404 in series. The input to inverter 120 is also connected to an inverter 121 via a switch S14. The input of inverter 121 is connected to a +5volt rail 402 by means of resistor 406. The input of inverter 121 is denoted T.

When switch S14 is open, the input to inverter 120 will rise to +5 volts causing the terminal T19 to be set to +5 volts representing an absence of SSYN signal on the control line 110. If however the SSYN control line 110 is grounded because of the presence of an SSYN signal properly generated by a peripheral interface then T19 will be brought to ground and will not prevent the other SSYN signal being transmitted to the processor 102.

The +5 volt rail 402 holds the input to inverter 121 at +5 volts if input T is not grounded in which instance the output of the inverter 121 will ground the input of the inverter 120 thus causing the terminal T19 to ground so transmitting an SSYN signal on the control line 110. If however input T is grounded no SSYN signal will be transmitted.

Connected to the input T are the outputs of thirteen, two-input, exclusive NOR logic gates (comparators) X2, X3-X14. The comparators X2-X14 are implemented on SN74LS266 integrated circuits which have open collector outputs so that any one having a ground output will bring input T to ground thus preventing an SSYN signal being transmitted to the control line 10 via the terminal T19 when an MSYN signal is received at terminal T18. If the outputs of all the comparators X2-X14 are set at +5 volts then input T will remain at +5 volts so generating an SSYN signal at terminal T19. Each of the comparators X2-X14 has a ground output if its inputs do not match and a +5 output if its inputs do match.

A terminal T18 connectable to the MSYN control line 108 of the computer system 100 is connected to the input of an inverter 118 whose output forms one of the input pairs of a comparator X14. The other input of comparator X14 is tied to a +5 volt rail 408 thus the output of the comparator X14 will be ground unless terminal T18 is brought to ground by the presence of an MSYN signal on the control line 108.

Each of the comparators X2-X12 has one of its pair of inputs linked to one of the store outputs 202-212 and the second of its pair of inputs to the corresponding selector output 302-312. If any one of the pre-selected address bits A2-A12 (or A3-A12 if swich S13 is open) does not match the corresponding stored bit of the test address then the corresponding comparator X2-X12 will have the output brought to ground therefore preventing a SSYN signal appearing at terminal T19.

Because the computer system 100 has peripheral addresses in which the address bits P13-P17 are all binary value 1 it is not necessary to provide a pre-settable store to store these bit values of a test address although they must be tested to ensure they have binary value 1. In the embodiment of Fig. 2 the test address bits 13 to 17 are tested as follows. Address bits 13 to 17 are selected by terminal T13-17 connectable to the respective address lines A13-A17 of the address bus 104. The terminals T13-T17 are connected to the inputs of inverters 113-117 whose outputs 313-317 are connected one to each of five inputs of an eight input NAND GATE 410. The remaining 3 inputs of the NAND GATE are held at +5 volts by connection to a +5 volt rail 410.The output of NAND GATE 410, implemented on an SN7430N integrated circuit, will be at ground as long as all the address bits A13-A17 correspond to an address bit of binary value 1 ie the corresponding address line A13-A17 is at ground. The output of NAND GATE 410 forms one of the input 8 to a comparator X13 the other input being connected to ground. The output of the comparator X13 is connected to the input T. If any one of the terminals T13 to T17 is raised to +5 volts by the presence of a binary value 0 on the corresponding address line the output of the NAND GATE 410 will rise to +5 volts thus causing the output of the comparator X13 and the input T to ground.

If there is no MSYN signal on the MSYN control line 108, the output of the comparator X14 will be at ground preventing any SSYN control signal being transmitted by the aid 150 to the processor 102. If a MSYN signal is present on the control line 108 input T will be at +5 volts and an SSYN signal will be output at terminal T19 if and only if the outputs of each comparator X2-X13 is also at +5 volts, that is if and only if the binary value of each of the selected bits from the address on the address bus 104 matches the binary value of the corresponding bit of the test address.

An intermittent addressing fault in the flight simulator 100 is traced by connecting the terminals T2-T19 of the aid 150 to the address lines A2-A17 of the address bus 104 and the MSYN and SSYN control lines 108 and 110. Bits P2-P12 of the address of the peripheral to be tested are set on the switches S2 to S12, closed corresponding to a binary value 1 and open to a binary value 0. No provision is made in this embodiment to set address bits 0 and 1 as each peripheral is addressable by one of two consecutive, even, word-addresses, ie bit P0 is not used and bit P1 distinguishes between the status and buffer memory of the interfaces 11-14 and so is not used to distinguish between peripherals. The system program is then run for some time to see if the addressing fault recurs.If it does the switches S2 to S12 are reset to the next peripheral address to be tested. This continues until the system does not exhibit the addressing fault which will happen when the test address set on the aid 150 corresponds to the address of the faulty interface, as now the aid is supplying the required SSYN handshake signal at the appropriate time to allow the program to continue.

In the computer system 100 shown in Fig. 1, interface 11 should return an SSYN signal if any one of four consecutive word addresses is on the address bus. To test this peripheral the switch S13 is set open so that only bits 3 to 17 of the address bus are selected to determine if an SSYN signal is to be generated. That is, only address bit 3 to 17 are pre-selected by the selector 300.

Once the fault is traced the faulty interface can be replaced by a working interface. The aid 150 may then be removed or left coupled to the complete system with switch S14 in the open position. It will be apparent to those skilled in the art that other methods of comparing the selected bits on the address bus to the corresponding bits of a test address can be readily devised to regulate the provision of a control signal at the terminal T19 on receipt of an MYSN signal at terminal T18. Also it will be appreciated that different configurations of address and control lines on a particular computer system may necessitate different selections of address bits from the address bus.

The fault finding aid terminals T2-T19 of the aid shown in Fig. 2 are arranged to be connectable to the bus lines of the computer system 100 at those positions common to all the backplanes used for the interface devices thus ensuring that the fault finding aid can be used on any of the computer systems backplanes and so substitute for any one of the interface boards as convenient.

The fault finding aid may be provided with additional terminals so that it may couple to all the bus lines of the computer system. If each terminal is provided with an appropriate termination resitor the bus termination card of the system may be removed and the fault finding aid fitted permanently in its place.

Claims (3)

1. A fault finding aid for a computer system having an address bus, a first and a second control line and a processor in which the processor is arranged to transmit a plurality of bus address bits on the address bus and to transmit and receive a first and second control signal on the first and second control line respectively, the aid comprising:: a pre-settable store arranged to store one or more pre-set test bits forming at least part of a test address and having one or more store outputs, the store being arranged to provide at each store output an electrical signal representative of the binary value of the corresponding pre-set test bit; a selector connectable to the address bus and having one or more selector outputs, the selector being arranged to select one or more selected bits from the bus address bits and provide an electrical signal representative of the binary value of each selected bit at the corresponding selector output; and a signal generator coupled to the store and selector outputs and having a control signal input connectable to the first control line and a control signal output connectable to the second control line, the signal generator being responsive to the receipt of a first control signal to provide a second control signal at the control signal output if and only if the binary value of each of the selected bits matches the binary value of the corresponding bit of the test address.

2. A fault finding aid as claimed in claim 1 in which the selector is pre-settable to select predetermined bus address bits from the address bus.

CLAIMS New claim filed on 28th Jan., 1987 Superseded claims none New Claim 3:

3. A fault finding aid substantially as hereinbefore described with reference to the accom panying Fig. 2.

panying Fig. 2.